Takeshi Nakayama

20 papers A 1B 3Journal 12Unranked 4

Year	Rank	Type	Title / Venue / Authors
2022	J	`jnl`	Frequency Error Compensation of Unsynchronized Bistatic CW- MIMO Radar for Multiple Human-Body Localization. IEEE Trans. Biomed. Circuits Syst. Abudusaimi Abuduaini, Nobuyuki Shiraki, Naoki Honma, Takeshi Nakayama, Shoichi Iizuka
2021	J	`jnl`	Estimation Method of the Number of Targets Using Cooperative Multi-Static MIMO Radar. IEICE Trans. Commun. Nobuyuki Shiraki, Naoki Honma, Kentaro Murata, Takeshi Nakayama, Shoichi Iizuka
2019	J	`jnl`	Human Activity Identification by Height and Doppler RCS Information Detected by MIMO Radar. IEICE Trans. Commun. Dai Sasakawa, Naoki Honma, Takeshi Nakayama, Shoichi Iizuka
2019	—	`conf`	Non-restraint human authentication using MIMO array. IPIN (Short Papers/Work-in-Progress Papers) Shoichi Iizuka, Takeshi Nakayama, Dai Sasakawa, Naoki Honma
2018	J	`jnl`	RSSI-Based Living-Body Radar Using Single RF Front-End and Tunable Parasitic Antennas. IEICE Trans. Commun. Katsumi Sasaki, Naoki Honma, Takeshi Nakayama, Shoichi Iizuka
2016	B	`conf`	Evaluation of fast human localization and tracking using MIMO radar in multi-path environment. PIMRC Dai Sasakawa, Naoki Honma, Kentaro Nishimori, Takeshi Nakayama, Shoichi Iizuka
2001	J	`jnl`	A 126.6-mm IEEE J. Solid State Circuits Tatsuya Ishii, Kazuyoshi Oshima, Hiroshi Sato, Satoshi Noda, Jiro Kishimoto, Hiroaki Kotani, Atsushi Nozoe, Kazunori Furusawa, Takayuki Yoshitake, Masataka Kato, Masahito Takahashi, Akihiko Sato, Shoji Kubono, Kiichi Manita, Kenji Koda, Takeshi Nakayama, Akira Hosogane
1999	J	`jnl`	A 256-Mb multilevel flash memory with 2-MB/s program rate for mass storage applications. IEEE J. Solid State Circuits Atsushi Nozoe, Hiroaki Kotani, Tetsuya Tsujikawa, Keiichi Yoshida, Kazunori Furusawa, Masataka Kato, Toshiaki Nishimoto, Hitoshi Kume, Hideaki Kurata, Naoki Miyamoto, Shoji Kubono, Michitaro Kanamitsu, Kenji Koda, Takeshi Nakayama, Yasuhiro Kouro, Akira Hosogane, Natsuo Ajika, Kiyoteru Kobayashi
1998	B	`conf`	A model-based approach for recognizing folding process of origami. ICPR Jien Kato, Toyohide Watanabe, Takeshi Nakayama, Lishing Guo, Hitoshi Kato
1997	—	`conf`	Application of neuro-based optimization algorithm to three dimensional cylindric puzzles. ICNN Hiroyuki Yamamoto, Takeshi Nakayama, Hiroshi Ninomiya, Hideki Asai
1997	A	`conf`	Recognition of Essential Folding Operations: A Step for Interpreting Illustrated Books of Origami. ICDAR Jien Kato, Toyohide Watanabe, Takeshi Nakayama
1996	B	`conf`	Identifying contents page of documents. ICPR Qin Luo, Takahiro Watanabe, Takeshi Nakayama
1996	—	`conf`	Tiling algorithm with fitting violation function for analog neural array. ICNN Hideki Asai, Takeshi Nakayama, Hiroshi Ninomiya
1995	—	`conf`	Neural network approach to traveling salesman problem based on hierarchical city adjacency. ICNN Hiroshi Ninomiya, Kazumichi Sato, Takeshi Nakayama, Hideki Asai
1994	J	`jnl`	Memory array architecture and decoding scheme for 3 V only sector erasable DINOR flash memory. IEEE J. Solid State Circuits Shin'ichi Kobayashi, Hiroaki Nakai, Yuichi Kunori, Takeshi Nakayama, Yoshikazu Miyawaki, Yasushi Terada, Hiroshi Onoda, Natsuo Ajika, Masahiro Hatanaka, Hirokazu Miyoshi, Tsutomu Yoshihara
1992	J	`jnl`	A new erasing and row decoding scheme for low supply voltage operation 16-Mb/64-Mb flash memories. IEEE J. Solid State Circuits Yoshikazu Miyawaki, Takeshi Nakayama, Shin'ichi Kobayashi, Natsuo Ajika, Makoto Ohi, Yasushi Terada, Hideaki Arima, Tsutomu Yoshihara
1991	J	`jnl`	A 60-ns 16-Mb flash EEPROM with program and erase sequence controller. IEEE J. Solid State Circuits Takeshi Nakayama, Shin'ichi Kobayashi, Yoshikazu Miyawaki, Yasushi Terada, Natsuo Ajika, Makoto Ohi, Hideaki Arima, Takayuki Matsukawa, Tsutomu Yoshihara, Kimio Suzuki
1989	J	`jnl`	120-ns 128 K8-bit/64 K16-bit CMOS EEPROMs. IEEE J. Solid State Circuits Yasushi Terada, Kazuo Kobayashi, Takeshi Nakayama, Masanori Hayashikoshi, Yoshikazu Miyawaki, Natsuo Ajika, Hideaki Arima, Takayuki Matsukawa, Tsutomu Yoshihara
1989	J	`jnl`	A 5 V only one-transistor 256 K EEPROM with page-mode erase. IEEE J. Solid State Circuits Takeshi Nakayama, Yoshikazu Miyawaki, Kazuo Kobayashi, Yasushi Terada, Hideaki Arima, Takayuki Matsukawa, Tsutomu Yoshihara
1988	J	`jnl`	A new architecture for the NVRAM-an EEPROM backed-up dynamic RAM. IEEE J. Solid State Circuits Yasushi Terada, Kazuo Kobayashi, Takeshi Nakayama, Hideaki Arima, Tsutomu Yoshihara