Takeshi Hamamoto

18 papers A 1Misc 1Journal 13Unranked 3
YearRankTypeTitle / Venue / Authors
2018 — conf
Evaluation methodology for current collapse phenomenon of GaN HEMTs.
IRPS
Toru Sugiyama, Kohei Oasa, Yasunobu Saito, Akira Yoshioka, Takuo Kikuchi, Aya Shindome, Tatsuya Ohguro, Takeshi Hamamoto
2011 J jnl
A Scalable Shield-Bitline-Overdrive Technique for Sub-1.5 V Chain FeRAMs.
IEEE J. Solid State Circuits
Daisaburo Takashima, Hidehiro Shiga, Daisuke Hashimoto, Tadashi Miyakawa, Shinichiro Shiratake, Katsuhiko Hoya, Ryu Ogiwara, Ryosuke Takizawa, Ryosuke Doumae, Ryo Fukuda, Yohji Watanabe, Shuso Fujii, Tohru Ozaki, Hiroyuki Kanaya, Susumu Shuto, Koji Yamakawa, Iwao Kunishima, Takeshi Hamamoto, Akihiro Nitayama
2010 J jnl
A 1.6 GB/s DDR2 128 Mb Chain FeRAM With Scalable Octal Bitline and Sensing Schemes.
IEEE J. Solid State Circuits
Hidehiro Shiga, Daisaburo Takashima, Shinichiro Shiratake, Katsuhiko Hoya, Tadashi Miyakawa, Ryu Ogiwara, Ryo Fukuda, Ryosuke Takizawa, Kosuke Hatsuda, Fumiyoshi Matsuoka, Yasushi Nagadomi, Daisuke Hashimoto, Hisaaki Nishimura, Takeshi Hioka, Sumiko M. Doumae, Shoichi Shimizu, Mitsumo Kawano, Toyoki Taguchi, Yohji Watanabe, Shuso Fujii, Tohru Ozaki, Hiroyuki Kanaya, Yoshinori Kumura, Yoshiro Shimojo, Yuki Yamada, Yoshihiro Minami, Susumu Shuto, Koji Yamakawa, Soichi Yamazaki, Iwao Kunishima, Takeshi Hamamoto, Akihiro Nitayama, Tohru Furuyama
2010 — conf
A scalable shield-bitline-overdrive technique for 1.3V Chain FeRAM.
ISSCC
Daisaburo Takashima, Hidehiro Shiga, Daisuke Hashimoto, Tadashi Miyakawa, Shinichiro Shiratake, Katsuhiko Hoya, Ryu Ogiwara, Ryosuke Takizawa, Ryosuke Doumae, Ryo Fukuda, Yohji Watanabe, Shuso Fujii, Tohru Ozaki, Hiroyuki Kanaya, Susumu Shuto, Koji Yamakawa, Iwao Kunishima, Takeshi Hamamoto, Akihiro Nitayama
2009 — conf
A 1.6GB/s DDR2 128Mb chain FeRAM with scalable octal bitline and sensing schemes.
ISSCC
Hidehiro Shiga, Daisaburo Takashima, Shinichiro Shiratake, Katsuhiko Hoya, Tadashi Miyakawa, Ryu Ogiwara, Ryo Fukuda, Ryosuke Takizawa, Kosuke Hatsuda, Fumiyoshi Matsuoka, Yasushi Nagadomi, Daisuke Hashimoto, Hisaaki Nishimura, Takeshi Hioka, Sumiko M. Doumae, Shoichi Shimizu, Mitsumo Kawano, Toyoki Taguchi, Yohji Watanabe, Shuso Fujii, Tohru Ozaki, Hiroyuki Kanaya, Yoshinori Kumura, Yoshiro Shimojo, Yuki Yamada, Yoshihiro Minami, Susumu Shuto, Koji Yamakawa, Soichi Yamazaki, Iwao Kunishima, Takeshi Hamamoto, Akihiro Nitayama, Tohru Furuyama
2006 J jnl
Design of a 128-mb SOI DRAM using the floating body cell (FBC).
IEEE J. Solid State Circuits
Takashi Ohsawa, Katsuyuki Fujita, Kosuke Hatsuda, Tomoki Higashi, Tomoaki Shino, Yoshihiro Minami, Hiroomi Nakajima, Mutsuo Morikado, Kazumi Inoh, Takeshi Hamamoto, Shigeyoshi Watanabe, Shuso Fujii, Tohru Furuyama
2005 J jnl
Highly Flexible Row and Column Redundancy and Cycle Time Adaptive Read Data Path for Double Data Rate Synchronous Memories.
IEICE Trans. Electron.
Kiyohiro Furutani, Takeshi Hamamoto, Takeo Miki, Masaya Nakano, Takashi Kono, Shigeru Kikuda, Yasuhiro Konishi, Tsutomu Yoshihara
2004 J jnl
A 667-Mb/s operating digital DLL architecture for 512-Mb DDR SDRAM.
IEEE J. Solid State Circuits
Takeshi Hamamoto, Kiyohiro Furutani, Takashi Kubo, Satoshi Kawasaki, Hironori Iga, Takashi Kono, Yasuhiro Konishi, Tsutomu Yoshihara
2003 A conf
Effect of Cross-Language IR in Bilingual Lexicon Acquisition from Comparable Corpora.
EACL
Takehito Utsuro, Takashi Horiuchi, Takeshi Hamamoto, Kohei Hino, Takeaki Nakayama
2002 Misc conf
Semi-automatic Compilation of Bilingual Lexicon Entries from Cross-Lingually Relevant News Articles on WWW News Sites.
AMTA
Takehito Utsuro, Takashi Horiuchi, Yasunobu Chiba, Takeshi Hamamoto
2000 J jnl
A 0.18-μm 256-Mb DDR-SDRAM with low-cost post-mold tuning method for DLL replica.
IEEE J. Solid State Circuits
Shigehiro Kuge, Tetsuo Kato, Kiyohiro Furutani, Shigeru Kikuda, Katsuyoshi Mitsui, Takeshi Hamamoto, Jun Setogawa, Kei Hamade, Yuichiro Komiya, Satoshi Kawasaki, Takashi Kono, Teruhiko Amano, Takashi Kubo, Masaru Haraguchi, Yoshito Nakaoka, Mihoko Akiyama, Yasuhiro Konishi, Hideyuki Ozaki, Tsutomu Yoshihara
2000 J jnl
A precharged-capacitor-assisted sensing (PCAS) scheme with novel level controllers for low-power DRAMs.
IEEE J. Solid State Circuits
Takashi Kono, Takeshi Hamamoto, Katsuyoshi Mitsui, Yasuhiro Konishi, Tsutomu Yoshihara, Hideyuki Ozaki
1998 J jnl
400-MHz random column operating SDRAM techniques with self-skew compensation.
IEEE J. Solid State Circuits
Takeshi Hamamoto, Masaki Tsukude, Kazutami Arimoto, Yasuhiro Konishi, Takayuki Miyamoto, Hideyuki Ozaki, Michihiro Yamada
1996 J jnl
Cell-plate-line/bit-line complementary sensing (CBCS) architecture for ultra low-power DRAMs.
IEEE J. Solid State Circuits
Takeshi Hamamoto, Yoshikazu Maroaka, Mikio Asakura, Hideyuki Ozaki
1993 J jnl
An experimental DRAM with a NAND-structured cell.
IEEE J. Solid State Circuits
Takehiro Hasegawa, Daisaburo Takashima, Ryu Ogiwara, Masako Ohta, Shinichiro Shiratake, Takeshi Hamamoto, Takashi Yamada, Masami Aoki, Shigeru Ishibashi, Yukihito Oowaki, Shigeyoshi Watanabe, Fujio Masuoka
1992 J jnl
A 288-kb fully parallel content addressable memory using a stacked-capacitor cell structure.
IEEE J. Solid State Circuits
Tadato Yamagata, Masaaki Mihara, Takeshi Hamamoto, Yasumitsu Murai, Toshifumi Kobayashi, Michihiro Yamada, Hideyuki Ozaki
1989 J jnl
A 45-ns 16-Mbit DRAM with triple-well structure.
IEEE J. Solid State Circuits
Syuso Fujii, Masaki Ogihara, Mitsuru Shimizu, Munehiro Yoshida, Kenji Numata, Takahiko Hara, Shigeyoshi Watanabe, Shizuo Sawada, Tomohisa Mizuno, Junpei Kumagai, Susumu Yoshikawa, Sejii Kaki, Yoshikazu Saito, Hideaki Aochi, Takeshi Hamamoto, Koichi Toita
1989 J jnl
An experimental 16-Mbit CMOS DRAM chip with a 100-MHz serial read/write mode.
IEEE J. Solid State Circuits
Shigeyoshi Watanabe, Yukihito Oowaki, Yasuo Itoh, Koji Sakui, Kenji Numata, Tsuneaki Fuse, Takayuki Kobayashi, Kenji Tsuchida, Masahiko Chiba, Takahiko Hara, Masako Ohta, Fumio Horiguchi, Katsuhiko Hieda, Akihiro Nitayama, Takeshi Hamamoto, Kazunori Ohuchi, Fujio Masuoka