Takeshi Fujino

89 papers A 4C 9Misc 1Journal 42Unranked 33

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Adversarial Examples on Vertical Federated Split Learning by Using Gradient Sign Prediction. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Kota Yoshida, Takeshi Fujino
2025	—	`conf`	Arithmetic Masking Countermeasure to Mitigate Side-Channel-Based Model Extraction Attack on DNN Accelerator. ACNS Workshops (1) Hirokatsu Yamasaki, Kota Yoshida, Yuta Fukuda, Takeshi Fujino
2025	J	`jnl`	CA-SCA: Non-Profiled Deep Learning-Based Side-Channel Attacks by Using Cluster Analysis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yuta Fukuda, Kota Yoshida, Takeshi Fujino
2025	J	`jnl`	Mitigation of Membership Inference Attack by Knowledge Distillation on Federated Learning. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Rei Ueda, Tsunato Nakai, Kota Yoshida, Takeshi Fujino
2025	J	`jnl`	Multi-Bit DDLA: Non-Profiled Deep Learning Side-Channel Attacks Using Multi-Bit Label against Hardware-Implemented AES. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yuta Fukuda, Kota Yoshida, Takeshi Fujino
2024	J	`jnl`	Adversarial Examples Created by Fault Injection Attack on Image Sensor Interface. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Tatsuya Oyama, Kota Yoshida, Shunsuke Okura, Takeshi Fujino
2024	J	`jnl`	Data Poisoning Attack against Neural Network-Based On-Device Learning Anomaly Detector by Physical Attacks on Sensors. Sensors Takahito Ino, Kota Yoshida, Hiroki Matsutani, Takeshi Fujino
2024	—	`conf`	Defense Method Against Adversarial Example Attacks using Thermal Noise of a CMOS Image Sensor. IEEE SENSORS Yuki Rogi, Kota Yoshida, Tatsuya Oyama, Takeshi Fujino, Shunsuke Okura
2024	—	`conf`	Evaluation of Accuracy and Security on Deep Learning Model by Utilizing K-Anonymization With Attribute Selection for Reducing Computational Cost. GCCE Rei Ueda, Kota Yoshida, Takeshi Fujino
2024	—	`conf`	FPGA Implementation of Physically Unclonable Functions Based on Multi-threshold Delay Time Measurement Method to Mitigate Modeling Attacks. ACNS Workshops (1) Tatsuya Oyama, Mika Sakai, Yohei Hori, Toshihiro Katashita, Takeshi Fujino
2024	—	`conf`	Incorporating Cluster Analysis of Feature Vectors for Non-profiled Deep-learning-Based Side-Channel Attacks. ACNS Workshops (1) Yuta Fukuda, Kota Yoshida, Takeshi Fujino
2024	—	`conf`	Model Extraction Attack Without Natural Images. ACNS Workshops (2) Kota Yoshida, Takeshi Fujino
2024	J	`jnl`	SEDMA: Self-Distillation with Model Aggregation for Membership Privacy. Proc. Priv. Enhancing Technol. Tsunato Nakai, Ye Wang, Kota Yoshida, Takeshi Fujino
2023	J	`jnl`	Backdoor Attack on Deep Neural Networks Triggered by Fault Injection Attack on Image Sensor Interface. Sensors Tatsuya Oyama, Shunsuke Okura, Kota Yoshida, Takeshi Fujino
2023	—	`conf`	Evaluation of Membership Inference Attack Against Federated Learning With Differential Privacy on Edge Devices. GCCE Rei Ueda, Tsunato Nakai, Kota Yoshida, Takeshi Fujino
2023	J	`jnl`	Evaluation of Model Quantization Method on Vitis-AI for Mitigating Adversarial Examples. IEEE Access Yuta Fukuda, Kota Yoshida, Takeshi Fujino
2023	J	`jnl`	Exploring Effect of Residual Electric Charges on Cryptographic Circuits: Extended Version. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Mitsuru Shiozaki, Takeshi Sugawara, Takeshi Fujino
2023	—	`conf`	Multispectral Pedestrian Detection with Visible and Far-infrared Images Under Drifting Ambient Light and Temperature. SENSORS Masato Okuda, Kota Yoshida, Takeshi Fujino
2023	J	`jnl`	Practical aspects on non-profiled deep-learning side-channel attacks against AES software implementation with two types of masking countermeasures including RSM. J. Cryptogr. Eng. Kunihiro Kuroda, Yuta Fukuda, Kota Yoshida, Takeshi Fujino
2023	J	`jnl`	Profiling Deep Learning Side-Channel Attacks Using Multi-Label against AES Circuits with RSM Countermeasure. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yuta Fukuda, Kota Yoshida, Hisashi Hashimoto, Kunihiro Kuroda, Takeshi Fujino
2022	J	`jnl`	Adversarial Scan Attack against Scan Matching Algorithm for Pose Estimation in LiDAR-Based SLAM. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Kota Yoshida, Masaya Hojo, Takeshi Fujino
2022	—	`conf`	Deep Learning Side-Channel Attacks against Hardware-Implemented Lightweight Cipher Midori 64. ATAIT Madoka Sakou, Kunihiro Kuroda, Yuta Fukuda, Kota Yoshida, Takeshi Fujino
2022	—	`conf`	Deep Learning-Based Side-Channel Attacks against Software-Implemented RSA using Binary Exponentiation with Dummy Multiplication. ATAIT Seiya Shimada, Kunihiro Kuroda, Yuta Fukuda, Kota Yoshida, Takeshi Fujino
2022	J	`jnl`	Experimental Study of Fault Injection Attack on Image Sensor Interface for Triggering Backdoored DNN Models. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Tatsuya Oyama, Shunsuke Okura, Kota Yoshida, Takeshi Fujino
2022	J	`jnl`	Fault Injection Attacks Utilizing Waveform Pattern Matching against Neural Networks Processing on Microcontroller. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yuta Fukuda, Kota Yoshida, Takeshi Fujino
2022	—	`conf`	Fundamental Study of Adversarial Examples Created by Fault Injection Attack on Image Sensor Interface. AsianHOST Tatsuya Oyama, Kota Yoshida, Shunsuke Okura, Takeshi Fujino
2022	—	`conf`	Towards Isolated AI Accelerators with OP-TEE on SoC-FPGAs. ACNS Workshops Tsunato Nakai, Daisuke Suzuki, Takeshi Fujino
2021	J	`jnl`	Adversarial Black-Box Attacks with Timing Side-Channel Leakage. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Tsunato Nakai, Daisuke Suzuki, Fumio Omatsu, Takeshi Fujino
2021	J	`jnl`	Area-Efficient Post-Processing Circuits for Physically Unclonable Function with 2-Mpixel CMOS Image Sensor. Sensors Shunsuke Okura, Masanori Aoki, Tatsuya Oyama, Masayoshi Shirahata, Takeshi Fujino, Kenichiro Ishikawa, Isao Takayanagi
2021	—	`conf`	Backdoor Attack on Deep Neural Networks Triggered by Fault Injection Attack on Image Sensor Interface. ASHES@CCS Tatsuya Oyama, Shunsuke Okura, Kota Yoshida, Takeshi Fujino
2021	—	`conf`	Deep Learning Side-Channel Attacks Against Lightweight SCA Countermeasure RSM-AES. AsianHOST Yuta Fukuda, Kota Yoshida, Hisashi Hashimoto, Takeshi Fujino
2021	J	`jnl`	Deep learning side-channel attack against hardware implementations of AES. Microprocess. Microsystems Takaya Kubota, Kota Yoshida, Mitsuru Shiozaki, Takeshi Fujino
2021	—	`conf`	Model Evasion Attacks Against Partially Encrypted Deep Neural Networks in Isolated Execution Environment. ACNS Workshops Kota Yoshida, Takeshi Fujino
2021	J	`jnl`	Model Reverse-Engineering Attack against Systolic-Array-Based DNN Accelerator Using Correlation Power Analysis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Kota Yoshida, Mitsuru Shiozaki, Shunsuke Okura, Takaya Kubota, Takeshi Fujino
2021	J	`jnl`	Modeling attacks against device authentication using CMOS image sensor PUF. IEICE Electron. Express Hiroshi Yamada, Shunsuke Okura, Masayoshi Shirahata, Takeshi Fujino
2021	—	`conf`	Practical Aspects on Non-profiled Deep-learning Side-channel Attacks against AES Software Implementation with Two Types of Masking Countermeasures including RSM. ASHES@CCS Kunihiro Kuroda, Yuta Fukuda, Kota Yoshida, Takeshi Fujino
2021	J	`jnl`	Simple electromagnetic analysis attack based on geometric leak on ASIC implementation of ring-oscillator PUF. J. Cryptogr. Eng. Mitsuru Shiozaki, Takeshi Fujino
2021	J	`jnl`	Timing Black-Box Attacks: Crafting Adversarial Examples through Timing Leaks against DNNs on Embedded Devices. IACR Trans. Cryptogr. Hardw. Embed. Syst. Tsunato Nakai, Daisuke Suzuki, Takeshi Fujino
2021	—	`conf`	Towards Trained Model Confidentiality and Integrity Using Trusted Execution Environments. ACNS Workshops Tsunato Nakai, Daisuke Suzuki, Takeshi Fujino
2021	—	`conf`	Towards Trusted IoT Sensing Systems: Implementing PUF as Secure Key Generator for Root of Trust and Message Authentication Code. HASP@MICRO Kota Yoshida, Kuniyasu Suzaki, Takeshi Fujino
2020	C	`conf`	Cause Analysis Method of Entropy Loss in Physically Unclonable Functions. ISCAS Mitsuru Shiozaki, Yohei Hori, Tatsuya Oyama, Masayoshi Shirahata, Takeshi Fujino
2020	—	`conf`	Disabling Backdoor and Identifying Poison Data by using Knowledge Distillation in Backdoor Attacks on Deep Neural Networks. AISec@CCS Kota Yoshida, Takeshi Fujino
2020	J	`jnl`	Entropy Estimation of Physically Unclonable Functions. IACR Cryptol. ePrint Arch. Mitsuru Shiozaki, Yohei Hori, Takeshi Fujino
2020	—	`conf`	Exploring Effect of Residual Electric Charges on Cryptographic Circuits. ASHES@CCS Mitsuru Shiozaki, Takeshi Sugawara, Takeshi Fujino
2020	C	`conf`	Model Reverse-Engineering Attack using Correlation Power Analysis against Systolic Array Based Neural Network Accelerator. ISCAS Kota Yoshida, Takaya Kubota, Shunsuke Okura, Mitsuru Shiozaki, Takeshi Fujino
2019	C	`conf`	Deep Learning Side-Channel Attack Against Hardware Implementations of AES. DSD Takaya Kubota, Kota Yoshida, Mitsuru Shiozaki, Takeshi Fujino
2019	Misc	`conf`	Model-Extraction Attack Against FPGA-DNN Accelerator Utilizing Correlation Electromagnetic Analysis. FCCM Kota Yoshida, Takaya Kubota, Mitsuru Shiozaki, Takeshi Fujino
2019	—	`conf`	Simple Electromagnetic Analysis Attacks based on Geometric Leak on an ASIC Implementation of Ring-Oscillator PUF. ASHES@CCS Mitsuru Shiozaki, Takeshi Fujino
2018	—	`conf`	A Dynamic Soft-Decision Fuzzy Extractor for a CMOS Image Sensor PUF. ISPACS Shunsuke Okura, Ryota Ishiki, Masayoshi Shirahata, Takaya Kubota, Mitsuru Shiozaki, Kenichiro Ishikawa, Isao Takayanagi, Takeshi Fujino
2017	J	`jnl`	Hierarchical-Masked Image Filtering for Privacy-Protection. IEICE Trans. Inf. Syst. Takeshi Kumaki, Takeshi Fujino
2017	—	`conf`	Malicious CAN-message attack against advanced driving assistant system. HOST Mitsuru Shiozaki, Takaya Kubota, Masashi Nakano, Yuuki Nakazawa, Takeshi Fujino
2017	J	`jnl`	Tamper-resistant cryptographic hardware. IEICE Electron. Express Takeshi Fujino, Takaya Kubota, Mitsuru Shiozaki
2015	—	`conf`	Development of LED illumination-based spy photo-prevention system. GCCE Kyosuke Kageyama, Kohei Sugiyama, Takeshi Kumaki, Takeshi Fujino
2015	—	`conf`	Proposal of LED-based Peeping Prevention System. MWSCAS Kyosuke Kageyama, Kohei Sugiyama, Takeshi Kumaki, Takeshi Fujino
2015	J	`jnl`	Reversing stealthy dopant-level circuits. J. Cryptogr. Eng. Takeshi Sugawara, Daisuke Suzuki, Ryoichi Fujii, Shigeaki Tawa, Ryohei Hori, Mitsuru Shiozaki, Takeshi Fujino
2015	C	`conf`	Tamper-resistant authentication system with side-channel attack resistant AES and PUF using MDR-ROM. ISCAS Mitsuru Shiozaki, Takaya Kubota, Tsunato Nakai, Akihiro Takeuchi, Takashi Nishimura, Takeshi Fujino
2014	J	`jnl`	Development of Compression Tolerable and Highly Implementable Watermarking Method for Mobile Devices. IEICE Trans. Inf. Syst. Takeshi Kumaki, Kei Nakao, Kohei Hozumi, Takeshi Ogura, Takeshi Fujino
2014	J	`jnl`	Diffusion Programmable Device : The device to prevent reverse engineering. IACR Cryptol. ePrint Arch. Mitsuru Shiozaki, Ryohei Hori, Takeshi Fujino
2014	—	`conf`	Interleaved-bitslice AES encryption and decryption with massive-parallel mobile embedded processor. APCCAS Takeshi Kumaki, Takeshi Fujino, Tetsushi Koide
2014	J	`jnl`	Intra-Masking Dual-Rail Memory on LUT Implementation for SCA-Resistant AES on FPGA. ACM Trans. Reconfigurable Technol. Syst. Anh-Tuan Hoang, Takeshi Fujino
2014	C	`conf`	Live Demonstration: Hierarchical masked image filtering technology on security-camera for privacy protection. ISCAS Yuki Yanagihara, Toshiya Honda, Takeshi Kumaki, Takeshi Fujino
2014	J	`jnl`	On measurable side-channel leaks inside ASIC design primitives. J. Cryptogr. Eng. Takeshi Sugawara, Daisuke Suzuki, Minoru Saeki, Mitsuru Shiozaki, Takeshi Fujino
2014	A	`conf`	Reversing Stealthy Dopant-Level Circuits. CHES Takeshi Sugawara, Daisuke Suzuki, Ryoichi Fujii, Shigeaki Tawa, Ryohei Hori, Mitsuru Shiozaki, Takeshi Fujino
2014	J	`jnl`	Reversing Stealthy Dopant-Level Circuits. IACR Cryptol. ePrint Arch. Takeshi Sugawara, Daisuke Suzuki, Ryoichi Fujii, Shigeaki Tawa, Ryohei Hori, Mitsuru Shiozaki, Takeshi Fujino
2014	J	`jnl`	Security Evaluation of RG-DTM PUF Using Machine Learning Attacks. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Mitsuru Shiozaki, Kousuke Ogawa, Kota Furuhashi, Takahiko Murayama, Masaya Yoshikawa, Takeshi Fujino
2014	C	`conf`	Side-channel attack resistant AES cryptographic circuits with ROM reducing address-dependent EM leaks. ISCAS Tsunato Nakai, Megumi Shibatani, Mitsuru Shiozaki, Takaya Kubota, Takeshi Fujino
2014	J	`jnl`	Unified Coprocessor Architecture for Secure Key Storage and Challenge-Response Authentication. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Koichi Shimizu, Daisuke Suzuki, Toyohiro Tsurumaru, Takeshi Sugawara, Mitsuru Shiozaki, Takeshi Fujino
2013	—	`conf`	A stable key generation from PUF responses with a Fuzzy Extractor for cryptographic authentications. GCCE Masato Taniguchi, Mitsuru Shiozaki, Hiroshi Kubo, Takeshi Fujino
2013	—	`conf`	Cipher-destroying and secret-key-emitting hardware Trojan against AES core. MWSCAS Takeshi Kumaki, Masaya Yoshikawa, Takeshi Fujino
2013	—	`conf`	Development of effective information-hiding method for embedded systems. MWSCAS Kei Nakao, Kohei Hozumi, Takeshi Kumaki, Takeshi Ogura, Takeshi Fujino
2013	—	`conf`	Hierarchical image-scrambling method with scramble-level controllability for privacy protection. MWSCAS Toshiya Honda, Yuma Murakami, Yuki Yanagihara, Takeshi Kumaki, Takeshi Fujino
2013	A	`conf`	Hybrid masking using intra-masking dual-rail memory on LUT for SCA-Resistant AES implementation on FPGA (abstract only). FPGA Anh-Tuan Hoang, Takeshi Fujino
2013	A	`conf`	On Measurable Side-Channel Leaks Inside ASIC Design Primitives. CHES Takeshi Sugawara, Daisuke Suzuki, Minoru Saeki, Mitsuru Shiozaki, Takeshi Fujino
2013	J	`jnl`	On Measurable Side-Channel Leaks inside ASIC Design Primitives. IACR Cryptol. ePrint Arch. Takeshi Sugawara, Daisuke Suzuki, Minoru Saeki, Mitsuru Shiozaki, Takeshi Fujino
2013	—	`conf`	The implementation of DES circuit on via-programmable structured ASIC architecture VPEX3. VLSI-DAT Ryohei Hori, Taisuke Ueoka, Taku Otani, Masaya Yoshikawa, Takeshi Fujino
2012	C	`conf`	Efficient DPA-Resistance Verification Method with Smaller Number of Power Traces on AES Cryptographic Circuit. DSD Hiroki Ito, Mitsuru Shiozaki, Anh-Tuan Hoang, Takeshi Fujino
2012	J	`jnl`	High Uniqueness Arbiter-Based PUF Circuit Utilizing RG-DTM Scheme for Identification and Authentication Applications. IEICE Trans. Electron. Mitsuru Shiozaki, Kota Furuhashi, Takahiko Murayama, Akitaka Fukushima, Masaya Yoshikawa, Takeshi Fujino
2012	J	`jnl`	Improved Via-Programmable Structured ASIC VPEX3 and Its Evaluation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Ryohei Hori, Tatsuya Kitamori, Taisuke Ueoka, Masaya Yoshikawa, Takeshi Fujino
2012	A	`conf`	Intra-masking dual-rail memory on LUT implementation for tamper-resistant AES on FPGA. FPGA Anh-Tuan Hoang, Takeshi Fujino
2012	J	`jnl`	Via Programmable Structured ASIC Architecture "VPEX3" and CAD Design System. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Ryohei Hori, Taisuke Ueoka, Taku Otani, Masaya Yoshikawa, Takeshi Fujino
2011	—	`conf`	Implementation and verification of DPA-resistant cryptographic DES circuit using Domino-RSL. HOST Katsuhiko Iwai, Mitsuru Shiozaki, Anh-Tuan Hoang, Kenji Kojima, Takeshi Fujino
2011	J	`jnl`	Placement Tool Dedicated for a Via-Programmable Logic Device VPEX. Int. J. Comput. Their Appl. Masaya Yoshikawa, Takeshi Fujino
2011	C	`conf`	The arbiter-PUF with high uniqueness utilizing novel arbiter circuit with Delay-Time Measurement. ISCAS Kota Furuhashi, Mitsuru Shiozaki, Akitaka Fukushima, Takahiko Murayama, Takeshi Fujino
2010	C	`conf`	Placement Tool Dedicated for a Via-programmable Logic Device VPEX. CAINE Masaya Yoshikawa, Yuichi Kokusyo, Takeshi Fujino
2008	J	`jnl`	Regular Fabric of Via Programmable Logic Device Using EXclusive-or Array (VPEX) for EB Direct Writing. IEICE Trans. Electron. Akihiro Nakamura, Masahide Kawarasaki, Kouta Ishibashi, Masaya Yoshikawa, Takeshi Fujino
2007	—	`conf`	Architecture of Via Programmable Logic using Exclusive-OR Array (VPEX) for EB Direct Writing. CICC Akihiro Nakamura, Masahide Kawaharazaki, Masaya Yoshikawa, Takeshi Fujino
2003	J	`jnl`	A Low Power Embedded DRAM Macro for Battery-Operated LSIs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Takeshi Fujino, Akira Yamazaki, Yasuhiko Taito, Mitsuya Kinoshita, Fukashi Morishita, Teruhiko Amano, Masaru Haraguchi, Makoto Hatakenaka, Atsushi Amo, Atsushi Hachisuka, Kazutami Arimoto, Hideyuki Ozaki
2003	J	`jnl`	An embedded DRAM with a 143-MHz SRAM interface using a sense-synchronized read/write. IEEE J. Solid State Circuits Yasuhiko Taito, Tetsushi Tanizaki, Mitsuya Kinoshita, Futoshi Igaue, Takeshi Fujino, Kazutami Arimoto
1997	J	`jnl`	A 1.2- to 3.3-V wide voltage-range/low-power DRAM with a charge-transfer presensing scheme. IEEE J. Solid State Circuits Masaki Tsukude, Shigehiro Kuge, Takeshi Fujino, Kazutami Arimoto