Takayuki Kawahara

75 papers A 1C 5Journal 36Unranked 33

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	Annealing Processing System Capable of Simultaneous Updates of All Spins Using Transition-Based Multi-State Spin. IEEE Access Kazuma Kanai, Takayuki Kawahara
2025	J	`jnl`	Dual Scalable Annealing Processing System That Scales Number of Spins and Interaction Bit Width Simultaneously. IEEE Access Dong Cui, Taichi Megumi, Akari Endo, Takayuki Kawahara
2024	—	`conf`	Efficient Implementation of Parallel Annealing Method with Heisenberg Model. APCCAS Kazuma Kanai, Takayuki Kawahara
2024	J	`jnl`	Implementation and Evaluation of Two Independent Ising Machines on Same FPGA Board by Reducing Number of Interactions Inside Ising Machine. IEEE Access Shinjiro Kitahara, Taichi Megumi, Akari Endo, Takayuki Kawahara
2024	—	`conf`	Method for Measuring Silicon Quantum Dots with TMR Sensor. APCCAS Seiji Komatsu, Takayuki Kawahara
2024	—	`conf`	Proposal and Validation of Annealing-processor-calculation Method Using Error-diffusion Rounded Interaction Matrix. APCCAS Dong Cui, Takayuki Kawahara
2024	—	`conf`	Proposal and Validation of a Dual Scalable Annealing Processing System That Simultaneously Scales Capacity and Precision. ICM Dong Cui, Taichi Megumi, Akari Endo, Takayuki Kawahara
2024	J	`jnl`	Scalable Fully-Coupled Annealing Processing System Implementing 4096 Spins Using 22nm CMOS LSI. IEEE Access Taichi Megumi, Akari Endo, Takayuki Kawahara
2024	J	`jnl`	TGBNN: Training Algorithm of Binarized Neural Network With Ternary Gradients for MRAM-Based Computing-in-Memory Architecture. IEEE Access Yuya Fujiwara, Takayuki Kawahara
2023	C	`conf`	BNN Training Algorithm with Ternary Gradients and BNN based on MRAM Array. TENCON Yuya Fujiwara, Takayuki Kawahara
2023	C	`conf`	Experimental Investigation of the Generalization Performance of Neural Network in Defect Localization System for Steel Pipe Health Monitoring. TENCON Yuya Hayakawa, Yuga Aoki, Kenjiro Mori, Takumi Ito, Takayuki Kawahara
2022	—	`conf`	Bi-directional read method to reduce SOT-specific read disturbance for highly reliable SOT-MRAM. IMW Akihiro Yamada, Yuwa Kishi, Takayuki Kawahara
2022	J	`jnl`	Scalable fully coupled annealing processing system and multi-chip FPGA implementation. Microprocess. Microsystems Kaoru Yamamoto, Takayuki Kawahara
2021	J	`jnl`	Annealing Processing Architecture of 28-nm CMOS Chip for Ising Model With 512 Fully Connected Spins. IEEE Trans. Circuits Syst. I Regul. Pap. Ryoma Iimura, Satoshi Kitamura, Takayuki Kawahara
2021	—	`conf`	FPGA Implementation of Support Vector Machine Using Ising Model for AI on Things. CIVEMSA Yudai Taguchi, Ryoma Iimura, Takayuki Kawahara
2020	J	`jnl`	A novel Ising model processing achieving all interactions only by adjacent spins for a high-speed solver for versatile Ising machines. Microprocess. Microsystems Ryoto Ono, Kenta Someya, Takayuki Kawahara
2020	—	`conf`	Damage-Position Identification of Wooden-House Models for Structural Health Monitoring Using Machine Learning. APCCAS Kohei Koike, Kenta Suzuki, Mengnan Ke, Kenjiro Mori, Takumi Ito, Takayuki Kawahara
2020	—	`conf`	Implementation of Multi Spin-Thread Architecture to Fully-Connected Annealing Processing AI Chips. MWSCAS Ryoma Iimura, Satoshi Kitamura, Takayuki Kawahara
2020	—	`conf`	Improvement of Generalization Performance for Timber Health Monitoring using Machine Learning. APCCAS Kenta Suzuki, Takumi Ito, Kohei Koike, Takayuki Kawahara, Mengnan Ke, Kenjiro Mori
2019	—	`conf`	Effectiveness of Synchronization and Cooperative Behavior of Multiple Robots based on Swarm AI. APCCAS Tatsuya Hiejima, Shun Kawashima, Mengnan Ke, Takayuki Kawahara
2019	—	`conf`	High-speed Sparse Ising Model on FPGA. MWSCAS Akira Minamisawa, Ryoma Iimura, Takayuki Kawahara
2019	—	`conf`	Machine Learning Classification Methods using Data of 3-axis Acceleration Sensors equipped with Wireless Communication Means for Locating Wooden House Structural Damage. APCCAS Ryota Tanida, Jing Ma, Takashi Nakajima, Mikio Hasegawa, Takahiro Yamamoto, Takumi Ito, Takayuki Kawahara, Atsushi Yamamoto, Noriaki Takahashi, Natsuhiko Sakiyama, Sakuya Kishi, Takayuki Kishimoto, So Hasegawa, Kenjiro Mori, Yoichiro Hashizume
2018	C	`conf`	Live Demonstration of IoT and AI System for Recognition of States of Buildings subjected to Seismic Vibration Motion. ISCAS Takumi Ito, Changhoon Choi, Takahiro Yamamoto, Takashi Nakajima, Takayuki Kawahara, Yoichiro Hashizume, Mikio Hasegawa
2018	—	`conf`	Wooden Framed House Structural Health Monitoring by System Identification and Damage Detection under Dynamic Motion with Artificial Intelligence Sensor using a Model of House including Braces. CIVEMSA Ryota Tanida, Ryo Oiwa, Takumi Ito, Takayuki Kawahara
2017	J	`jnl`	A Saturating-Integrator-Based Behavioral Model of Ring Oscillator Facilitating PLL Design. IEICE Trans. Electron. Zule Xu, Takayuki Kawahara
2017	J	`jnl`	Robustness Evaluation of Restricted Boltzmann Machine against Memory and Logic Error. IEICE Trans. Electron. Yasushi Fukuda, Zule Xu, Takayuki Kawahara
2017	—	`conf`	Timber Health Monitoring using piezoelectric sensor and machine learning. CIVEMSA Ryo Oiwa, Takumi Ito, Takayuki Kawahara
2016	—	`conf`	Novel Ising model using dimension-control for high-speed solver for Ising machines. NEWCAS Kenta Someya, Ryoto Ono, Takayuki Kawahara
2015	—	`conf`	An eight-channel FDM system using Mach-Zehnder filters with cosine roll-off band-limiting characteristics. APSITT Isamu Wakabayashi, Yuki Fukushima, Takayuki Kawahara
2015	—	`conf`	Equalization for the FDM System Using Mach-Zehnder Filters. AINA Workshops Yuki Fukushima, Isamu Wakabayashi, Takayuki Kawahara
2015	—	`conf`	STT-RAM read stability in DRAM operating region. NVMTS H. Kazama, Takayuki Kawahara
2014	—	`conf`	What is a good way to expand a silicon value to a solution value? A-SSCC Tzi-Dar Chiueh, Toru Shimizu, Gregory Chen, Chen-Yi Lee, Charles Hsu, Tihao Chiang, Zhihua Wang, Junghwan Choi, Jongwoo Lee, Yasumoto Tomita, Takayuki Kawahara
2013	—	`conf`	On-chip base sequencing using a two-stage reaction-control scheme: 3.6-times-faster and 1/100-reduced-data-volume ISFET-based DNA sequencer. BioCAS Yoshimitsu Yanagawa, Naoshi Itabashi, Sonoko Migitaka, Takahide Yokoi, Makiko Yoshida, Takayuki Kawahara
2012	J	`jnl`	Fluctuation Tolerant Charge-Integration Read Scheme for Ultrafast DNA Sequencing with Nanopore Device. IEICE Trans. Electron. Kazuo Ono, Yoshimitsu Yanagawa, Akira Kotabe, Riichiro Takemura, Tatsuo Nakagawa, Tomio Iwasaki, Takayuki Kawahara
2012	C	`conf`	Fluctuation tolerant read scheme for ultrafast DNA sequencing with nanopore device. ISCAS Yoshimitsu Yanagawa, Kazuo Ono, Akira Kotabe, Riichiro Takemura, Tatsuo Nakagawa, Tomio Iwasaki, Takayuki Kawahara
2012	J	`jnl`	Spin-transfer torque RAM technology: Review and prospect. Microelectron. Reliab. Takayuki Kawahara, Kenchi Ito, Riichiro Takemura, Hideo Ohno
2011	J	`jnl`	Scalable Spin-Transfer Torque RAM Technology for Normally-Off Computing. IEEE Des. Test Comput. Takayuki Kawahara
2010	J	`jnl`	A 32-Mb SPRAM With 2T1R Memory Cell, Localized Bi-Directional Write Driver and '1'/'0' Dual-Array Equalized Reference Scheme. IEEE J. Solid State Circuits Riichiro Takemura, Takayuki Kawahara, Katsuya Miura, Hiroyuki Yamamoto, Jun Hayakawa, Nozomu Matsuzaki, Kazuo Ono, Michihiko Yamanouchi, Kenchi Ito, Hiromasa Takahashi, Shoji Ikeda, Haruhiro Hasegawa, Hideyuki Matsuoka, Hideo Ohno
2008	J	`jnl`	2 Mb SPRAM (SPin-Transfer Torque RAM) With Bit-by-Bit Bi-Directional Current Write and Parallelizing-Direction Current Read. IEEE J. Solid State Circuits Takayuki Kawahara, Riichiro Takemura, Katsuya Miura, Jun Hayakawa, Shoji Ikeda, Young Min Lee, Ryutaro Sasaki, Yasushi Goto, Kenchi Ito, Toshiyasu Meguro, Fumihiro Matsukura, Hiromasa Takahashi, Hideyuki Matsuoka, Hideo Ohno
2008	—	`conf`	A cell-activation-time controlled SRAM for low-voltage operation in DVFS SoCs using dynamic stability analysis. ESSCIRC Masanao Yamaoka, Kenichi Osada, Takayuki Kawahara
2007	—	`conf`	2Mb Spin-Transfer Torque RAM (SPRAM) with Bit-by-Bit Bidirectional Current Write and Parallelizing-Direction Current Read. ISSCC Takayuki Kawahara, Riichiro Takemura, Katsuya Miura, Jun Hayakawa, Shoji Ikeda, Young Min Lee, Ryutaro Sasaki, Yasushi Goto, Kenchi Ito, Toshiyasu Meguro, Fumihiro Matsukura, Hiromasa Takahashi, Hideyuki Matsuoka, Hideo Ohno
2007	—	`conf`	A 512kB Embedded Phase Change Memory with 416kB/s Write Throughput at 100μA Cell Write Current. ISSCC Satoru Hanzawa, Naoki Kitai, Kenichi Osada, Akira Kotabe, Yuichi Matsui, Nozomu Matsuzaki, Norikatsu Takaura, Masahiro Moniwa, Takayuki Kawahara
2007	J	`jnl`	Long-Retention-Time, High-Speed DRAM Array with 12- IEICE Trans. Electron. Riichiro Takemura, Kiyoo Itoh, Tomonori Sekiguchi, Satoru Akiyama, Satoru Hanzawa, Kazuhiko Kajigaya, Takayuki Kawahara
2007	J	`jnl`	Low-Voltage Embedded RAMs in Nanometer Era. IEICE Trans. Electron. Takayuki Kawahara
2007	—	`conf`	Low-voltage limitations of deep-sub-100-nm CMOS LSIs: view of memory designers. ACM Great Lakes Symposium on VLSI Kiyoo Itoh, Masanao Yamaoka, Takayuki Kawahara
2007	—	`conf`	Operating-margin-improved SRAM with column-at-a-time body-bias control technique. ESSCIRC Masanao Yamaoka, Takayuki Kawahara
2007	—	`conf`	SPRAM (SPin-transfer torque RAM) design and its impact on digital systems. ICECS Takayuki Kawahara, Riichiro Takemura, Hiromasa Takahashi, Hideo Ohno
2006	J	`jnl`	90-nm process-variation adaptive embedded SRAM modules with power-line-floating write technique. IEEE J. Solid State Circuits Masanao Yamaoka, Noriaki Maeda, Yoshihiro Shinozaki, Yasuhisa Shimazaki, Koji Nii, Shigeru Shimada, Kazumasa Yanagisawa, Takayuki Kawahara
2006	J	`jnl`	Concordant memory design: an integrated statistical design approach for multi-gigabit DRAM. IEEE J. Solid State Circuits Satoru Akiyama, Tomonori Sekiguchi, Kazuhiko Kajigaya, Satoru Hanzawa, Riichiro Takemura, Takayuki Kawahara
2006	J	`jnl`	SRAM Circuit With Expanded Operating Margin and Reduced Stand-By Leakage Current Using Thin-BOX FD-SOI Transistors. IEEE J. Solid State Circuits Masanao Yamaoka, Ryuta Tsuchiya, Takayuki Kawahara
2006	C	`conf`	Ultra-low voltage nano-scale embedded RAMs. ISCAS Kiyoo Itoh, Masashi Horiguchi, Takayuki Kawahara
2005	J	`jnl`	A large-scale and low-power CAM architecture featuring a one-hot-spot block code for IP-address lookup in a network router. IEEE J. Solid State Circuits Satoru Hanzawa, Takeshi Sakata, Kazuhiko Kajigaya, Riichiro Takemura, Takayuki Kawahara
2005	—	`conf`	A ternary/quaternary CAM architecture with an NPU-side IP-address compression scheme and a dynamic re-configurable CODEC scheme for large-scale flow-table lookup. ICC Satoru Hanzawa, Takeshi Sakata, Kazuhiko Kajigaya, Riichiro Takemura, Tomonori Sekiguchi, Takayuki Kawahara
2005	—	`conf`	An LSI system with locked in temperature insensitive state achieved by using body bias technique. ISCAS (1) Goichi Ono, Masayuki Miyazaki, Kazuki Watanabe, Takayuki Kawahara
2005	J	`jnl`	Constant-charge-injection programming: a novel high-speed programming method for multilevel flash memories. IEEE J. Solid State Circuits Hideaki Kurata, Shunichi Saeki, Takashi Kobayashi, Yoshitaka Sasago, Tsuyoshi Arigane, Kazuo Otsuga, Takayuki Kawahara
2005	—	`conf`	Optimum threshold-voltage tuning for low-power, high-performance microprocessor. ISCAS (1) Masayuki Miyazaki, Goichi Ono, Takayuki Kawahara
2005	—	`conf`	Phase change RAM operated with 1.5-V CMOS as low cost embedded memory. CICC Kenichi Osada, Takayuki Kawahara, Riichiro Takemura, Naoki Kitai, Norikatsu Takaura, Nozomu Matsuzaki, Kenzo Kurotsuchi, Hiroshi Moriya, Masahiro Moniwa
2004	—	`conf`	Analysis of SRAM neutron-induced errors based on the consideration of both charge-collection and parasitic-bipolar failure modes. CICC Kenichi Osada, Naoki Kitai, Shiro Kamohara, Takayuki Kawahara
2004	—	`conf`	Low-Voltage Embedded RAMs - Current Status and Future Trends. PATMOS Kiyoo Itoh, Kenichi Osada, Takayuki Kawahara
2004	J	`jnl`	SRAM immunity to cosmic-ray-induced multierrors based on analysis of an induced parasitic bipolar effect. IEEE J. Solid State Circuits Kenichi Osada, Ken Yamaguchi, Yoshikazu Saitoh, Takayuki Kawahara
2004	—	`conf`	Temperature referenced supply voltage and forward-body-bias control (TSFC) architecture for minimum power consumption [ubiquitous computing processors]. ESSCIRC Goichi Ono, Masayuki Miyazaki, Hidetoshi Tanaka, Nono Ohkubo, Takayuki Kawahara
2003	A	`conf`	Electric-energy generation using variable-capacitive resonator for power-free LSI: efficiency analysis and fundamental experiment. ISLPED Masayuki Miyazaki, Hidetoshi Tanaka, Goichi Ono, Tomohiro Nagano, Norio Ohkubo, Takayuki Kawahara, Kazuo Yano
2003	J	`jnl`	Review and future prospects of low-voltage RAM circuits. IBM J. Res. Dev. Yoshinobu Nakagome, Masashi Horiguchi, Takayuki Kawahara, Kiyoo Itoh
1998	J	`jnl`	20-Mb/s erase/record flash memory by asymmetrical operation. IEEE J. Solid State Circuits Takayuki Kawahara, Yusuke Jyouno, Syun-ichi Saeki, Naoki Miyamoto, Katsutaka Kimura
1998	J	`jnl`	Internal voltage generator for low voltage, quarter-micrometer flash memories. IEEE J. Solid State Circuits Takayuki Kawahara, Syun-ichi Saeki, Yusuke Jyouno, Naoki Miyamoto, Takashi Kobayashi, Katsutaka Kimura
1996	J	`jnl`	Bit-line clamped sensing multiplex and accurate high voltage generator for quarter-micron flash memories. IEEE J. Solid State Circuits Takayuki Kawahara, Takashi Kobayashi, Yusuke Jyouno, Syun-ichi Saeki, Naoki Miyamoto, T. Adachi, Masataka Kato, Akihiko Sato, J. Yugami, Hitoshi Kume, Katsutaka Kimura
1995	J	`jnl`	High reliability electron-ejection method for high density flash memories. IEEE J. Solid State Circuits Takayuki Kawahara, Naoki Miyamoto, Syun-ichi Saeki, Yusuke Jyouno, Masataka Kato, Katsutaka Kimura
1993	J	`jnl`	256-Mb DRAM circuit technologies for file applications. IEEE J. Solid State Circuits Goro Kitsukawa, Masashi Horiguchi, Yoshiki Kawajiri, Takayuki Kawahara, Takesada Akiba, Yasushi Kawase, Toshikazu Tachibana, Takeshi Sakai, Masakazu Aoki, Syoji Shukuri, Kazuhiko Sagara, Ryo Nagai, Yuzuru Ohji, Nono Hasegawa, Natsuki Yokoyama, Teruaki Kisu, Hisaomi Yamashita, Tokuo Kure, Takashi Nishida
1993	J	`jnl`	A high-speed, small-area, threshold-voltage-mismatch compensation sense amplifier for gigabit-scale DRAM arrays. IEEE J. Solid State Circuits Takayuki Kawahara, Takeshi Sakata, Kiyoo Itoh, Yoshiki Kawajiri, Takesada Akiba, Goro Kitsukawa, Masakazu Aoki
1993	J	`jnl`	Subthreshold current reduction for decoded-driver by self-reverse biasing (DRAMs). IEEE J. Solid State Circuits Takayuki Kawahara, Masashi Horiguchi, Yoshiki Kawajiri, Goro Kitsukawa, Tokuo Kure, Masakazu Aoki
1992	J	`jnl`	Deep-submicrometer BiCMOS circuit technology for sub-10-ns ECL 4-Mb DRAM's. IEEE J. Solid State Circuits Takayuki Kawahara, Yoshiki Kawajiri, Goro Kitsukawa, Kazuhiko Sagara, Yoshifumi Kawamoto, Takesada Akiba, Shisei Kato, Yasushi Kawase, Kiyoo Itoh
1991	J	`jnl`	A circuit technology for sub-10-ns ECL 4-Mb BiCMOS DRAM's. IEEE J. Solid State Circuits Takayuki Kawahara, Yoshiki Kawajiri, Goro Kitsukawa, Yoshinobu Nakagome, Kazuhiko Sagara, Yoshifumi Kawamoto, Takesada Akiba, Shisei Kato, Yasushi Kawase, Kiyoo Itoh
1989	J	`jnl`	A 1-Mbit BiCMOS DRAM using temperature-compensation circuit techniques. IEEE J. Solid State Circuits Goro Kitsukawa, Kiyoo Itoh, Ryoichi Hori, Yoshiki Kawajiri, Takao Watanabe, Takayuki Kawahara, Tetsuro Matsumoto, Yutaka Kobayashi
1989	J	`jnl`	Comparison of CMOS and BiCMOS 1-Mbit DRAM performance. IEEE J. Solid State Circuits Takao Watanabe, Goro Kitsukawa, Yoshiki Kawajiri, Kiyoo Itoh, Ryoichi Hori, Yoshiaki Ouchi, Takayuki Kawahara, Tetsuro Matsumoto
1989	J	`jnl`	Substrate current reduction techniques for BiCMOS DRAM. IEEE J. Solid State Circuits Takayuki Kawahara, Goro Kitsukawa, Hisayuki Higuchi, Yoshiki Kawajiri, Takao Watanabe, Kiyoo Itoh, Ryoichi Hori, Yutaka Kobayashi, Tetsuro Matsumoto