Takayasu Sakurai

227 papers A* 5A 20C 6Journal 103Unranked 93

Year	Rank	Type	Title / Venue / Authors
2024	J	`jnl`	Estimating of IGBT Bond Wire Lift-Off Trend Using Convolutional Neural Network (CNN). IEEE Access Thatree Mamee, Zaiqi Lou, Katsuhiro Hata, Makoto Takamiya, Takayasu Sakurai, Shinichi Nishizawa, Wataru Saito
2022	J	`jnl`	A 6.78-MHz Multiple-Transmitter Wireless Power Transfer System With Efficiency Maximization by Adaptive Magnetic Field Adder IC. IEEE J. Solid State Circuits Hao Qiu, Takayasu Sakurai, Makoto Takamiya
2022	J	`jnl`	High-Speed Searching of Optimum Switching Pattern for Digital Active Gate Drive to Adapt to Various Load Conditions. IEEE Trans. Ind. Electron. Yu-Shan Cheng, Daiki Yamaguchi, Tomoyuki Mannen, Keiji Wada, Toru Sai, Koutaro Miyazaki, Makoto Takamiya, Takayasu Sakurai
2021	J	`jnl`	Analysis and Mitigation of Coupling-Dependent Data Flipping in Wireless Power and Data Transfer System. IEEE Trans. Circuits Syst. I Regul. Pap. Hao Qiu, Yuntao Jiang, Yi Shi, Takayasu Sakurai, Makoto Takamiya
2019	J	`jnl`	A 0.90-4.39-V Detection Voltage Range, 56-Level Programmable Voltage Detector Using Fine Voltage-Step Subtraction for Battery Management. IEEE Trans. Circuits Syst. I Regul. Pap. Teruki Someya, Kenichi Matsunaga, Hiroki Morimura, Takayasu Sakurai, Makoto Takamiya
2019	—	`conf`	A 500-Mbps Digital Isolator Circuits using Counter-Pulse Immune Receiver Scheme for Power Electronics. ICICDT Tsukasa Kagaya, Koutaro Miyazaki, Makoto Takamiya, Takayasu Sakurai
2019	J	`jnl`	An 11-nW CMOS Temperature-to-Digital Converter Utilizing Sub-Threshold Current at Sub-Thermal Drain Voltage. IEEE J. Solid State Circuits Teruki Someya, A. K. M. Mahfuzul Islam, Takayasu Sakurai, Makoto Takamiya
2019	—	`conf`	CNN-based Approach for Estimating Degradation of Power Devices by Gate Waveform Monitoring. ICICDT Koutaro Miyazaki, Yang Lo, A. K. M. Mahfuzul Islam, Katsuhiro Hata, Makoto Takamiya, Takayasu Sakurai
2019	C	`conf`	Coupling-Dependent Data Flipping in Wireless Power and Data Transfer System. ISCAS Hao Qiu, Takayasu Sakurai, Makoto Takamiya
2019	C	`conf`	Digital Active Gate Drive with Optimal Switching Patterns to Adapt to Sinusoidal Output Current in a Full Bridge Inverter Circuit. IECON Yu-Shan Cheng, Daiki Yamaguchi, Tomoyuki Mannen, Keiji Wada, Toru Sai, Koutaro Miyazaki, Makoto Takamiya, Takayasu Sakurai
2018	J	`jnl`	2/3 and 1/2 Reconfigurable Switched Capacitor DC-DC Converter With 92.9% Efficiency at 62 mW/mm IEEE Trans. Circuits Syst. II Express Briefs Toru Sai, Yoshitaka Yamauchi, Hajime Kando, Tatsuya Funaki, Takayasu Sakurai, Makoto Takamiya
2018	—	`conf`	A 13nW temperature-to-digital converter utilizing sub-threshold MOSFET operation at sub-thermal drain voltage. CICC Teruki Someya, Islam A. K. M. Mahfuzul, Takayasu Sakurai, Makoto Takamiya
2018	J	`jnl`	Clocked Hysteresis Control Scheme With Power-Law Frequency Scaling in Buck Converter to Improve Light-Load Efficiency for IoT Sensor Nodes. IEEE Trans. Very Large Scale Integr. Syst. Chung-Shiang Wu, Makoto Takamiya, Takayasu Sakurai
2017	J	`jnl`	A Low-Power CMOS Crystal Oscillator Using a Stacked-Amplifier Architecture. IEEE J. Solid State Circuits Shunta Iguchi, Takayasu Sakurai, Makoto Takamiya
2017	—	`conf`	Buck converter with higher than 87% efficiency over 500nA to 20mA load current range for IoT sensor nodes by Clocked Hysteresis Control. CICC Chung-Shiang Wu, Makoto Takamiya, Takayasu Sakurai
2017	J	`jnl`	Design and Analysis of Ultra-Low Power Glitch-Free Programmable Voltage Detector Based on Multiple Voltage Copier. IEICE Trans. Electron. Teruki Someya, Hiroshi Fuketa, Kenichi Matsunaga, Hiroki Morimura, Takayasu Sakurai, Makoto Takamiya
2017	C	`conf`	Modeling of 3-level buck converters in discontinuous conduction mode for stand-by mode power supply. ISCAS Yoshitaka Yamauchi, Toru Sai, Takayasu Sakurai, Makoto Takamiya
2017	J	`jnl`	Programmable Neuron Array Based on a 2-Transistor Multiplier Using Organic Floating-Gate for Intelligent Sensors. IEEE J. Emerg. Sel. Topics Circuits Syst. Islam A. K. M. Mahfuzul, Masamune Hamamatsu, Tomoyuki Yokota, Sunghoon Lee, Wakako Yukita, Makoto Takamiya, Takao Someya, Takayasu Sakurai
2016	—	`conf`	5.7 A 39.25MHz 278dB-FOM 19µW LDO-free stacked-amplifier crystal oscillator (SAXO) operating at I/O voltage. ISSCC Shunta Iguchi, Takayasu Sakurai, Makoto Takamiya
2016	—	`conf`	56-Level programmable voltage detector in steps of 50mV for battery management. A-SSCC Teruki Someya, Kenichi Matsunaga, Hiroki Morimura, Takayasu Sakurai, Makoto Takamiya
2016	J	`jnl`	Variation-Tolerant Quick-Start-Up CMOS Crystal Oscillator With Chirp Injection and Negative Resistance Booster. IEEE J. Solid State Circuits Shunta Iguchi, Hiroshi Fuketa, Takayasu Sakurai, Makoto Takamiya
2015	—	`conf`	16.4 Energy-autonomous fever alarm armband integrating fully flexible solar cells, piezoelectric speaker, temperature detector, and 12V organic complementary FET circuits. ISSCC Hiroshi Fuketa, Masamune Hamamatsu, Tomoyuki Yokota, Wakako Yukita, Teruki Someya, Tsuyoshi Sekitani, Makoto Takamiya, Takao Someya, Takayasu Sakurai
2015	—	`conf`	248pW, 0.11mV/°C glitch-free programmable voltage detector with multiple voltage duplicator for energy harvesting. ESSCIRC Teruki Someya, Hiroshi Fuketa, Kenichi Matsunaga, Hiroki Morimura, Takayasu Sakurai, Makoto Takamiya
2015	—	`conf`	Analysis to optimize sensitivity of RF energy harvester with voltage boost circuit. ECCTD Dan Luo, Hiroshi Fuketa, Kenichi Matsunaga, Hiroki Morimura, Makoto Takamiya, Takayasu Sakurai
2015	—	`conf`	Optimal design to maximize efficiency of single-inductor multiple-output buck converters in discontinuous conduction mode for IoT applications. ICICDT Yoshitaka Yamauchi, Yuki Yanagihara, Hiroshi Fuketa, Takayasu Sakurai, Makoto Takamiya
2015	J	`jnl`	Wireless Power Transfer With Zero-Phase-Difference Capacitance Control. IEEE Trans. Circuits Syst. I Regul. Pap. Shunta Iguchi, Pyungwoo Yeon, Hiroshi Fuketa, Koichi Ishida, Takayasu Sakurai, Makoto Takamiya
2014	J	`jnl`	1 µm-Thickness Ultra-Flexible and High Electrode-Density Surface Electromyogram Measurement Sheet With 2 V Organic Transistors for Prosthetic Hand Control. IEEE Trans. Biomed. Circuits Syst. Hiroshi Fuketa, Kazuaki Yoshioka, Yasuhiro Shinozuka, Koichi Ishida, Tomoyuki Yokota, Naoji Matsuhisa, Yusuke Inoue, Masaki Sekino, Tsuyoshi Sekitani, Makoto Takamiya, Takao Someya, Takayasu Sakurai
2014	—	`conf`	30.3 Organic-transistor-based 2kV ESD-tolerant flexible wet sensor sheet for biomedical applications with wireless power and data transmission using 13.56MHz magnetic resonance. ISSCC Hiroshi Fuketa, Kazuaki Yoshioka, Tomoyuki Yokota, Wakako Yukita, Mari Koizumi, Masaki Sekino, Tsuyoshi Sekitani, Makoto Takamiya, Takao Someya, Takayasu Sakurai
2014	—	`conf`	92% start-up time reduction by variation-tolerant chirp injection (CI) and negative resistance booster (NRB) in 39MHz crystal oscillator. VLSIC Shunta Iguchi, Hiroshi Fuketa, Takayasu Sakurai, Makoto Takamiya
2014	J	`jnl`	A 0.6 V Input CCM/DCM Operating Digital Buck Converter in 40 nm CMOS. IEEE J. Solid State Circuits Xin Zhang, Po-Hung Chen, Yasuyuki Okuma, Koichi Ishida, Yoshikatsu Ryu, Kazunori Watanabe, Takayasu Sakurai, Makoto Takamiya
2014	—	`conf`	An 85-mV input, 50-µs startup fully integrated voltage multiplier with passive clock boost using on-chip transformers for energy harvesting. ESSCIRC Hiroshi Fuketa, Youichi Momiyama, Atsushi Okamoto, Tsuyoshi Sakata, Makoto Takamiya, Takayasu Sakurai
2014	J	`jnl`	Design Method of Class-F Power Amplifier With Output Power of -20 dBm and Efficient Dual Supply Voltage Transmitter. IEEE Trans. Circuits Syst. I Regul. Pap. Shunta Iguchi, Akira Saito, Kazunori Watanabe, Takayasu Sakurai, Makoto Takamiya
2014	—	`conf`	Flexible, large-area, and distributed organic electronics closely contacted with skin for healthcare applications. MWSCAS Makoto Takamiya, Hiroshi Fuketa, Koichi Ishida, Tomoyuki Yokota, Tsuyoshi Sekitani, Takao Someya, Takayasu Sakurai
2014	J	`jnl`	Intermittent Resonant Clocking Enabling Power Reduction at Any Clock Frequency for Near/Sub-Threshold Logic Circuits. IEEE J. Solid State Circuits Hiroshi Fuketa, Masahiro Nomura, Makoto Takamiya, Takayasu Sakurai
2013	—	`conf`	1µm-thickness 64-channel surface electromyogram measurement sheet with 2V organic transistors for prosthetic hand control. ISSCC Hiroshi Fuketa, Kazuaki Yoshioka, Yasuhiro Shinozuka, Koichi Ishida, Tomoyuki Yokota, Naoji Matsuhisa, Yusuke Inoue, Masaki Sekino, Tsuyoshi Sekitani, Makoto Takamiya, Takao Someya, Takayasu Sakurai
2013	—	`conf`	315MHz OOK transceiver with 38-µW receiver and 36-µW transmitter in 40-nm CMOS. ASP-DAC Shunta Iguchi, Akira Saito, Kentaro Honda, Yun Fei Zheng, Kazunori Watanabe, Takayasu Sakurai, Makoto Takamiya
2013	—	`conf`	A low voltage buck DC-DC converter using on-chip gate boost technique in 40nm CMOS. ASP-DAC Xin Zhang, Po-Hung Chen, Yoshikatsu Ryu, Koichi Ishida, Yasuyuki Okuma, Kazunori Watanabe, Takayasu Sakurai, Makoto Takamiya
2013	A*	`conf`	Electrical artificial skin using ultraflexible organic transistor. DAC Tsuyoshi Sekitani, Tomoyuki Yokota, Makoto Takamiya, Takayasu Sakurai, Takao Someya
2013	J	`jnl`	Highly Energy-Efficient SRAM With Hierarchical Bit Line Charge-Sharing Method Using Non-Selected Bit Line Charges. IEEE J. Solid State Circuits Shinji Miyano, Shinichi Moriwaki, Yasue Yamamoto, Atsushi Kawasumi, Toshikazu Suzuki, Takayasu Sakurai, Hirofumi Shinohara
2013	J	`jnl`	Increase of Crosstalk Noise Due to Imbalanced Threshold Voltage Between nMOS and pMOS in Subthreshold Logic Circuits. IEEE J. Solid State Circuits Hiroshi Fuketa, Ryo Takahashi, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai
2013	J	`jnl`	Insole Pedometer With Piezoelectric Energy Harvester and 2 V Organic Circuits. IEEE J. Solid State Circuits Koichi Ishida, Tsung-Ching Huang, Kentaro Honda, Yasuhiro Shinozuka, Hiroshi Fuketa, Tomoyuki Yokota, Ute Zschieschang, Hagen Klauk, Gregory Tortissier, Tsuyoshi Sekitani, Hiroshi Toshiyoshi, Makoto Takamiya, Takao Someya, Takayasu Sakurai
2013	—	`conf`	Intermittent resonant clocking enabling power reduction at any clock frequency for 0.37V 980kHz near-threshold logic circuits. ISSCC Hiroshi Fuketa, Masahiro Nomura, Makoto Takamiya, Takayasu Sakurai
2013	—	`conf`	Large-area and flexible sensors with organic transistors. IWASI Hiroshi Fuketa, Koichi Ishida, Tsuyoshi Sekitani, Makoto Takamiya, Takao Someya, Takayasu Sakurai
2013	J	`jnl`	Minimizing Energy of Integer Unit by Higher Voltage Flip-Flop: V IEEE Trans. Very Large Scale Integr. Syst. Hiroshi Fuketa, Koji Hirairi, Tadashi Yasufuku, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai
2013	—	`conf`	Reducing IR drop in 3D integration to less than 1/4 using Buck Converter on Top die (BCT) scheme. ISQED Yasuhiro Shinozuka, Hiroshi Fuketa, Koichi Ishida, Futoshi Furuta, Kenichi Osada, Kenichi Takeda, Makoto Takamiya, Takayasu Sakurai
2013	—	`conf`	Variation-aware subthreshold logic circuit design. ASICON Hiroshi Fuketa, Ryo Takahashi, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai
2012	A	`conf`	0.35V, 4.1μW, 39MHz crystal oscillator in 40nm CMOS. ISLPED Akira Saito, Yun Fei Zheng, Kazunori Watanabe, Takayasu Sakurai, Makoto Takamiya
2012	—	`conf`	13% Power reduction in 16b integer unit in 40nm CMOS by adaptive power supply voltage control with parity-based error prediction and detection (PEPD) and fully integrated digital LDO. ISSCC Koji Hirairi, Yasuyuki Okuma, Hiroshi Fuketa, Tadashi Yasufuku, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai
2012	—	`conf`	2.1 Times increase of drain efficiency by dual supply voltage scheme in 315MHz class-F Power amplifier at output power of -20dBm. ESSCIRC Shunta Iguchi, Akira Saito, Kazunori Watanabe, Takayasu Sakurai, Makoto Takamiya
2012	—	`conf`	24% Power reduction by post-fabrication dual supply voltage control of 64 voltage domains in V ISQED Tadashi Yasufuku, Koji Hirairi, Yu Pu, Yun Fei Zheng, Ryo Takahashi, Masato Sasaki, Hiroshi Fuketa, Atsushi Muramatsu, Masahiro Nomura, Hirofumi Shinohara, Makoto Takamiya, Takayasu Sakurai
2012	—	`conf`	A 0.45-V input on-chip gate boosted (OGB) buck converter in 40-nm CMOS with more than 90% efficiency in load range from 2µW to 50µW. VLSIC Xin Zhang, Po-Hung Chen, Yoshikatsu Ryu, Koichi Ishida, Yasuyuki Okuma, Kazunori Watanabe, Takayasu Sakurai, Makoto Takamiya
2012	J	`jnl`	A 1-V-Input Switched-Capacitor Voltage Converter With Voltage-Reference-Free Pulse-Density Modulation. IEEE Trans. Circuits Syst. II Express Briefs Xin Zhang, Yu Pu, Koichi Ishida, Yoshikatsu Ryu, Yasuyuki Okuma, Po-Hung Chen, Kazunori Watanabe, Takayasu Sakurai, Makoto Takamiya
2012	J	`jnl`	A 100-V AC Energy Meter Integrating 20-V Organic CMOS Digital and Analog Circuits With a Floating Gate for Process Variation Compensation and a 100-V Organic pMOS Rectifier. IEEE J. Solid State Circuits Koichi Ishida, Tsung-Ching Huang, Kentaro Honda, Tsuyoshi Sekitani, Hiroyoshi Nakajima, Hiroki Maeda, Makoto Takamiya, Takao Someya, Takayasu Sakurai
2012	—	`conf`	A 120-mV input, fully integrated dual-mode charge pump in 65-nm CMOS for thermoelectric energy harvester. ASP-DAC Po-Hung Chen, Koichi Ishida, Xin Zhang, Yasuyuki Okuma, Yoshikatsu Ryu, Makoto Takamiya, Takayasu Sakurai
2012	—	`conf`	A 13.8pJ/Access/Mbit SRAM with charge collector circuits for effective use of non-selected bit line charges. VLSIC Shinichi Moriwaki, Yasuhiro Yamamoto, Atsushi Kawasumi, Toshikazu Suzuki, Shinji Miyano, Takayasu Sakurai, Hirofumi Shinohara
2012	J	`jnl`	A 315 MHz Power-Gated Ultra Low Power Transceiver in 40 nm CMOS for Wireless Sensor Network. IEICE Trans. Electron. Lechang Liu, Takayasu Sakurai, Makoto Takamiya
2012	—	`conf`	Ambient electronics and ultra-low power LSI design. VLSI-DAT Takayasu Sakurai
2012	J	`jnl`	An 80 mV Startup Dual-Mode Boost Converter by Charge-Pumped Pulse Generator and Threshold Voltage Tuned Oscillator With Hot Carrier Injection. IEEE J. Solid State Circuits Po-Hung Chen, Xin Zhang, Koichi Ishida, Yasuyuki Okuma, Yoshikatsu Ryu, Makoto Takamiya, Takayasu Sakurai
2012	—	`conf`	An all 0.5V, 1Mbps, 315MHz OOK transceiver with 38-µW career-frequency-free intermittent sampling receiver and 52-µW class-F transmitter in 40-nm CMOS. VLSIC Akira Saito, Kentaro Honda, Yun Fei Zheng, Shunta Iguchi, Kazunori Watanabe, Takayasu Sakurai, Makoto Takamiya
2012	J	`jnl`	EMI Camera LSI (EMcam) with On-Chip Loop Antenna Matrix to Measure EMI Noise Spectrum and Distribution. IEICE Trans. Electron. Naoki Masunaga, Koichi Ishida, Takayasu Sakurai, Makoto Takamiya
2012	—	`conf`	Increase of crosstalk noise due to imbalanced threshold voltage between NMOS and PMOS in sub-threshold logic circuits. CICC Hiroshi Fuketa, Ryo Takahashi, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai
2012	—	`conf`	Insole pedometer with piezoelectric energy harvester and 2V organic digital and analog circuits. ISSCC Koichi Ishida, Tsung-Ching Huang, Kentaro Honda, Yasuhiro Shinozuka, Hiroshi Fuketa, Tomoyuki Yokota, Ute Zschieschang, Hagen Klauk, Gregory Tortissier, Tsuyoshi Sekitani, Makoto Takamiya, Hiroshi Toshiyoshi, Takao Someya, Takayasu Sakurai
2012	J	`jnl`	Large Within-Die Gate Delay Variations in Sub-Threshold Logic Circuits at Low Temperature. IEEE Trans. Circuits Syst. II Express Briefs Ryo Takahashi, Hidehiro Takata, Tadashi Yasufuku, Hiroshi Fuketa, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai
2012	J	`jnl`	On-Chip Measurement System for Within-Die Delay Variation of Individual Standard Cells in 65-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. Xin Zhang, Koichi Ishida, Hiroshi Fuketa, Makoto Takamiya, Takayasu Sakurai
2012	J	`jnl`	Startup Techniques for 95 mV Step-Up Converter by Capacitor Pass-On Scheme and V IEEE J. Solid State Circuits Po-Hung Chen, Koichi Ishida, Katsuyuki Ikeuchi, Xin Zhang, Kentaro Honda, Yasuyuki Okuma, Yoshikatsu Ryu, Makoto Takamiya, Takayasu Sakurai
2011	J	`jnl`	0.18-V Input Charge Pump with Forward Body Bias to Startup Boost Converter for Energy Harvesting Applications. IEICE Trans. Electron. Po-Hung Chen, Koichi Ishida, Xin Zhang, Yasuyuki Okuma, Yoshikatsu Ryu, Makoto Takamiya, Takayasu Sakurai
2011	—	`conf`	0.4V SRAM with bit line swing suppression charge share hierarchical bit line scheme. CICC Shinichi Moriwaki, Atsushi Kawasumi, Toshikazu Suzuki, Takayasu Sakurai, Shinji Miyano
2011	J	`jnl`	0.5-V Input Digital Low-Dropout Regulator (LDO) with 98.7% Current Efficiency in 65 nm CMOS. IEICE Trans. Electron. Yasuyuki Okuma, Koichi Ishida, Yoshikatsu Ryu, Xin Zhang, Po-Hung Chen, Kazunori Watanabe, Makoto Takamiya, Takayasu Sakurai
2011	J	`jnl`	0.6 V Voltage Shifter and Clocked Comparator for Sampling Correlation-Based Impulse Radio UWB Receiver. IEICE Trans. Electron. Lechang Liu, Takayasu Sakurai, Makoto Takamiya
2011	J	`jnl`	1 Gb/s, 50 µm × 50 µm Pads on Board Wireless Connector Based on Track-and-Charge Scheme Allowing Contacted Signaling. IEICE Trans. Electron. Katsuyuki Ikeuchi, Hideki Kusamitsu, Mutsuo Daito, Gil-Su Kim, Makoto Takamiya, Takayasu Sakurai
2011	J	`jnl`	1.8 V Low-Transient-Energy Adaptive Program-Voltage Generator Based on Boost Converter for 3D-Integrated NAND Flash SSD. IEEE J. Solid State Circuits Koichi Ishida, Tadashi Yasufuku, Shinji Miyamoto, Hiroto Nakai, Makoto Takamiya, Takayasu Sakurai, Ken Takeuchi
2011	—	`conf`	100V AC power meter system-on-a-film (SoF) integrating 20V organic CMOS digital and analog circuits with floating gate for process-variation compensation and 100V organic PMOS rectifier. ISSCC Koichi Ishida, Tsung-Ching Huang, Kentaro Honda, Tsuyoshi Sekitani, Hiroyoshi Nakajima, Hiroki Maeda, Makoto Takamiya, Takao Someya, Takayasu Sakurai
2011	—	`conf`	12% Power reduction by within-functional-block fine-grained adaptive dual supply voltage control in logic circuits with 42 voltage domains. ESSCIRC Atsushi Muramatsu, Tadashi Yasufuku, Masahiro Nomura, Makoto Takamiya, Hirofumi Shinohara, Takayasu Sakurai
2011	A	`conf`	12.7-times energy efficiency increase of 16-bit integer unit by power supply voltage (V ISLPED Hiroshi Fuketa, Koji Hirairi, Tadashi Yasufuku, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai
2011	—	`conf`	A 80-mV input, fast startup dual-mode boost converter with charge-pumped pulse generator for energy harvesting. A-SSCC Po-Hung Chen, Koichi Ishida, Xin Zhang, Yasuyuki Okuma, Yoshikatsu Ryu, Makoto Takamiya, Takayasu Sakurai
2011	—	`conf`	A 95mV-startup step-up converter with Vth-tuned oscillator by fixed-charge programming and capacitor pass-on scheme. ISSCC Po-Hung Chen, Koichi Ishida, Katsuyuki Ikeuchi, Xin Zhang, Kentaro Honda, Yasuyuki Okuma, Yoshikatsu Ryu, Makoto Takamiya, Takayasu Sakurai
2011	J	`jnl`	A Charge-Domain Auto- and Cross-Correlation Based Data Synchronization Scheme With Power- and Area-Efficient PLL for Impulse Radio UWB Receiver. IEEE J. Solid State Circuits Lechang Liu, Takayasu Sakurai, Makoto Takamiya
2011	J	`jnl`	A Variable Output Voltage Switched-Capacitor DC-DC Converter with Pulse Density and Width Modulation (PDWM) for 57% Ripple Reduction at Low Output Voltage. IEICE Trans. Electron. Xin Zhang, Yu Pu, Koichi Ishida, Yoshikatsu Ryu, Yasuyuki Okuma, Po-Hung Chen, Takayasu Sakurai, Makoto Takamiya
2011	A*	`conf`	A closed-form expression for estimating minimum operating voltage (V DAC Hiroshi Fuketa, Satoshi Iida, Tadashi Yasufuku, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai
2011	—	`conf`	An on-chip characterizing system for within-die delay variation measurement of individual standard cells in 65-nm CMOS. ASP-DAC Xin Zhang, Koichi Ishida, Makoto Takamiya, Takayasu Sakurai
2011	—	`conf`	Beyond the horizon: The next 10x reduction in power - Challenges and solutions. ISSCC Jan M. Rabaey, Hugo De Man, Mark Horowitz, Takayasu Sakurai, Jack Sun, Dan Dobberpuhl, Kiyoo Itoh, Philippe Magarshack, Asad A. Abidi, Hermann Eul
2011	J	`jnl`	Capacitively Coupled Non-Contact Probing Circuits for Membrane-Based Wafer-Level Simultaneous Testing. IEEE J. Solid State Circuits Mutsuo Daito, Yoshiro Nakata, Satoshi Sasaki, Hiroyuki Gomyo, Hideki Kusamitsu, Yoshio Komoto, Kunihiko Iizuka, Katsuyuki Ikeuchi, Gil-Su Kim, Makoto Takamiya, Takayasu Sakurai
2011	A	`conf`	Designing ultra-low voltage logic. ISLPED Takayasu Sakurai
2011	A	`conf`	Investigation of determinant factors of minimum operating voltage of logic gates in 65-nm CMOS. ISLPED Tadashi Yasufuku, Satoshi Iida, Hiroshi Fuketa, Koji Hirairi, Masahiro Nomura, Makoto Takamiya, Takayasu Sakurai
2011	J	`jnl`	Post-Silicon Clock Deskew Employing Hot-Carrier Injection Trimming With On-Chip Skew Monitoring and Auto-Stressing Scheme for Sub/Near Threshold Digital Circuits. IEEE Trans. Circuits Syst. II Express Briefs Yu Pu, Xin Zhang, Katsuyuki Ikeuchi, Atsushi Muramatsu, Atsushi Kawasumi, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai
2011	J	`jnl`	Power Supply Voltage Dependence of Within-Die Delay Variation of Regular Manual Layout and Irregular Place-and-Route Layout. IEICE Trans. Electron. Tadashi Yasufuku, Yasumi Nakamura, Piao Zhe, Makoto Takamiya, Takayasu Sakurai
2011	A	`conf`	Reduction of minimum operating voltage (V ISLPED Kentaro Honda, Katsuyuki Ikeuchi, Masahiro Nomura, Makoto Takamiya, Takayasu Sakurai
2011	—	`conf`	Through Silicon Capacitive Coupling (TSCC) interface for 3D stacked dies. 3DIC Katsuyuki Ikeuchi, Makoto Takamiya, Takayasu Sakurai
2011	J	`jnl`	User Customizable Logic Paper (UCLP) With Sea-Of Transmission-Gates (SOTG) of 2-V Organic CMOS and Ink-Jet Printed Interconnects. IEEE J. Solid State Circuits Koichi Ishida, Naoki Masunaga, Ryo Takahashi, Tsuyoshi Sekitani, Shigeki Shino, Ute Zschieschang, Hagen Klauk, Makoto Takamiya, Takao Someya, Takayasu Sakurai
2010	—	`conf`	0.18-V input charge pump with forward body biasing in startup circuit using 65nm CMOS. CICC Po-Hung Chen, Koichi Ishida, Xin Zhang, Yasuaki Okuma, Yoshikatsu Ryu, Makoto Takamiya, Takayasu Sakurai
2010	—	`conf`	0.5-V input digital LDO with 98.7% current efficiency and 2.7-µA quiescent current in 65nm CMOS. CICC Yasuyuki Okuma, Koichi Ishida, Yoshikatsu Ryu, Xin Zhang, Po-Hung Chen, Kazunori Watanabe, Makoto Takamiya, Takayasu Sakurai
2010	J	`jnl`	2 Gb/s 15 pJ/b/chip Inductive-Coupling Programmable Bus for NAND Flash Memory Stacking. IEEE J. Solid State Circuits Mitsuko Saito, Yasufumi Sugimori, Yoshinori Kohama, Yoichi Yoshida, Noriyuki Miura, Hiroki Ishikuro, Takayasu Sakurai, Tadahiro Kuroda
2010	—	`conf`	3D stacked buck converter with 15μm thick spiral inductor on silicon interposer for fine-grain power-supply voltage control in SiP's. 3DIC Koichi Ishida, Koichi Takemura, Kazuhiro Baba, Makoto Takamiya, Takayasu Sakurai
2010	J	`jnl`	A 1.76 mW, 100 Mbps Impulse Radio UWB Receiver with Multiple Sampling Correlators Eliminating Need for Phase Synchronization in 65-nm CMOS. IEICE Trans. Electron. Lechang Liu, Zhiwei Zhou, Takayasu Sakurai, Makoto Takamiya
2010	—	`conf`	A high-speed, low-power capacitive-coupling transceiver for wireless wafer-level testing systems. 3DIC Gil-Su Kim, Katsuyuki Ikeuchi, Mutsuo Daito, Makoto Takamiya, Takayasu Sakurai
2010	—	`conf`	Capacitively coupled non-contact probing circuits for membrane-based wafer-level simultaneous testing. ISSCC Mutsuo Daito, Yoshiro Nakata, Satoshi Sasaki, Hiroyuki Gomyo, Hideki Kusamitsu, Yoshio Komoto, Kunihiko Iizuka, Katsuyuki Ikeuchi, Gil-Su Kim, Makoto Takamiya, Takayasu Sakurai
2010	A	`conf`	Design of large area electronics with organic transistors. ICCAD Makoto Takamiya, Koichi Ishida, Tsuyoshi Sekitani, Takao Someya, Takayasu Sakurai
2010	J	`jnl`	Difficulty of Power Supply Voltage Scaling in Large Scale Subthreshold Logic Circuits. IEICE Trans. Electron. Tadashi Yasufuku, Taro Niiyama, Piao Zhe, Koichi Ishida, Masami Murakata, Makoto Takamiya, Takayasu Sakurai
2010	—	`conf`	EMI Camera LSI (EMcam) with 12 × 4 on-chip loop antenna matrix in 65-nm CMOS to measure EMI noise distribution with 60-µm spatial precision. CICC Naoki Masunaga, Koichi Ishida, Makoto Takamiya, Takayasu Sakurai
2010	J	`jnl`	Inductor and TSV Design of 20-V Boost Converter for Low Power 3D Solid State Drive with NAND Flash Memories. IEICE Trans. Electron. Tadashi Yasufuku, Koichi Ishida, Shinji Miyamoto, Hiroto Nakai, Makoto Takamiya, Takayasu Sakurai, Ken Takeuchi
2010	A	`conf`	Misleading energy and performance claims in sub/near threshold digital systems. ICCAD Yu Pu, Xin Zhang, Jim Huang, Atsushi Muramatsu, Masahiro Nomura, Koji Hirairi, Hidehiro Takata, Taro Sakurabayashi, Shinji Miyano, Makoto Takamiya, Takayasu Sakurai
2010	J	`jnl`	Power gating: Circuits, design methodologies, and best practice for standard-cell VLSI designs. ACM Trans. Design Autom. Electr. Syst. Youngsoo Shin, Jun Seomun, Kyu-Myung Choi, Takayasu Sakurai
2010	—	`conf`	Silicon 3D-integration technology and systems. ISSCC Pascal Urard, Ken Takeuchi, Kerry Bernstein, Hideto Hidaka, Michael Phan, Joo-Sun Choi, Bob Payne, Vladimir Stojanovic, Kees van Berkel, Takayasu Sakurai
2010	J	`jnl`	Stretchable EMI Measurement Sheet With 8 ˟ 8 Coil Array, 2 V Organic CMOS Decoder, and 0.18 μ m Silicon CMOS LSIs for Electric and Magnetic Field Detection. IEEE J. Solid State Circuits Koichi Ishida, Naoki Masunaga, Zhiwei Zhou, Tadashi Yasufuku, Tsuyoshi Sekitani, Ute Zschieschang, Hagen Klauk, Makoto Takamiya, Takao Someya, Takayasu Sakurai
2010	—	`conf`	The semiconductor industry in 2025. ISSCC Azeez Bhavnagarwala, Shekhar Borkar, Takayasu Sakurai, Siva G. Narendra
2010	—	`conf`	User Customizable Logic Paper (UCLP) with organic sea-of-transmission-gates (SOTG) architecture and ink-jet printed interconnects. ISSCC Koichi Ishida, Naoki Masunaga, Ryo Takahashi, Tsuyoshi Sekitani, Shigeki Shino, Ute Zschieschang, Hagen Klauk, Makoto Takamiya, Takao Someya, Takayasu Sakurai
2009	—	`conf`	A 1.8V 30nJ adaptive program-voltage (20V) generator for 3D-integrated NAND flash SSD. ISSCC Koichi Ishida, Tadashi Yasufuku, Shinji Miyamoto, Hiroto Nakai, Makoto Takamiya, Takayasu Sakurai, Ken Takeuchi
2009	J	`jnl`	A 100 Mbps, 4.1 pJ/bit Threshold Detection-Based Impulse Radio UWB Transceiver in 90 nm CMOS. IEICE Trans. Electron. Lechang Liu, Yoshio Miyamoto, Zhiwei Zhou, Kosuke Sakaida, Jisun Ryu, Koichi Ishida, Makoto Takamiya, Takayasu Sakurai
2009	—	`conf`	A 100Mbps, 0.19mW asynchronous threshold detector with DC power-free pulse discrimination for impulse UWB receiver. ASP-DAC Lechang Liu, Yoshio Miyamoto, Zhiwei Zhou, Kosuke Sakaida, Jisun Ryu, Koichi Ishida, Makoto Takamiya, Takayasu Sakurai
2009	J	`jnl`	A 107-pJ/bit 100-kb/s 0.18- muhboxm Capacitive-Coupling Transceiver With Data Edge Signaling and DC Power-Free Pulse Detector for Printable Communication Sheet. IEEE Trans. Circuits Syst. I Regul. Pap. Lechang Liu, Makoto Takamiya, Tsuyoshi Sekitani, Yoshiaki Noguchi, Shintaro Nakano, Koichiro Zaitsu, Tadahiro Kuroda, Takao Someya, Takayasu Sakurai
2009	J	`jnl`	A 25-mV-Sensitivity 2-Gb/s Optimum-Logic-Threshold Capacitive-Coupling Receiver for Wireless Wafer Probing Systems. IEEE Trans. Circuits Syst. II Express Briefs Gil-Su Kim, Makoto Takamiya, Takayasu Sakurai
2009	—	`conf`	A 2Gb/s 15pJ/b/chip Inductive-Coupling programmable bus for NAND Flash memory stacking. ISSCC Yasufumi Sugimori, Yoshinori Kohama, Mitsuko Saito, Yoichi Yoshida, Noriyuki Miura, Hiroki Ishikuro, Takayasu Sakurai, Tadahiro Kuroda
2009	J	`jnl`	A High-Speed Inductive-Coupling Link With Burst Transmission. IEEE J. Solid State Circuits Noriyuki Miura, Yoshinori Kohama, Yasufumi Sugimori, Hiroki Ishikuro, Takayasu Sakurai, Tadahiro Kuroda
2009	—	`conf`	A capacitive coupling interface with high sensitivity for wireless wafer testing. 3DIC Gil-Su Kim, Makoto Takamiya, Takayasu Sakurai
2009	—	`conf`	A stretchable EMI measurement sheet with 8×8 coil array, 2V organic CMOS decoder, and -70dBm EMI detection circuits in 0.18¼m CMOS. ISSCC Koichi Ishida, Naoki Masunaga, Zhiwei Zhou, Tadashi Yasufuku, Tsuyoshi Sekitani, Ute Zschieschang, Hagen Klauk, Makoto Takamiya, Takao Someya, Takayasu Sakurai
2009	J	`jnl`	An On-Chip Noise Canceller with High Voltage Supply Lines for Nanosecond-Range Power Supply Noise. IEICE Trans. Electron. Yasumi Nakamura, Makoto Takamiya, Takayasu Sakurai
2009	—	`conf`	Effect of resistance of TSV's on performance of boost converter for low power 3D SSD with NAND flash memories. 3DIC Tadashi Yasufuku, Koichi Ishida, Shinji Miyamoto, Hiroto Nakai, Makoto Takamiya, Takayasu Sakurai, Ken Takeuchi
2009	A	`conf`	Inductor design of 20-V boost converter for low power 3D solid state drive with NAND flash memories. ISLPED Tadashi Yasufuku, Koichi Ishida, Shinji Miyamoto, Hiroto Nakai, Makoto Takamiya, Takayasu Sakurai, Ken Takeuchi
2009	J	`jnl`	Low Power VLSI Circuit Design with Fine-Grain Voltage Engineering. Inf. Media Technol. Makoto Takamiya, Takayasu Sakurai
2009	J	`jnl`	Low Power VLSI Circuit Design with Fine-Grain Voltage Engineering. IPSJ Trans. Syst. LSI Des. Methodol. Makoto Takamiya, Takayasu Sakurai
2009	—	`conf`	Switched Resonant Clocking (SRC) scheme enabling dynamic frequency scaling and low-speed test. CICC Katsuyuki Ikeuchi, Kosuke Sakaida, Koichi Ishida, Takayasu Sakurai, Makoto Takamiya
2008	—	`conf`	1/5 power reduction by global optimization based on fine-grained body biasing. CICC Yasumi Nakamura, David Levacq, Limin Xiao, Takuya Minakawa, Taro Niiyama, Makoto Takamiya, Takayasu Sakurai
2008	J	`jnl`	A 0.14 pJ/b Inductive-Coupling Transceiver With Digitally-Controlled Precise Pulse Shaping. IEEE J. Solid State Circuits Noriyuki Miura, Hiroki Ishikuro, Kiichi Niitsu, Takayasu Sakurai, Tadahiro Kuroda
2008	—	`conf`	A 107pJ/b 100kb/s 0.18μm Capacitive-Coupling Transceiver for Printable Communication Sheet. ISSCC Lechang Liu, Makoto Takamiya, Tsuyoshi Sekitani, Yoshiaki Noguchi, Shintaro Nakano, Koichiro Zaitsu, Tadahiro Kuroda, Takao Someya, Takayasu Sakurai
2008	—	`conf`	An 11Gb/s Inductive-Coupling Link with Burst Transmission. ISSCC Noriyuki Miura, Yoshinori Kohama, Yasufumi Sugimori, Hiroki Ishikuro, Takayasu Sakurai, Tadahiro Kuroda
2008	J	`jnl`	Backgate Bias Accelerator for sub-100 ns Sleep-to-Active Modes Transition Time. IEEE J. Solid State Circuits David Levacq, Makoto Takamiya, Takayasu Sakurai
2008	—	`conf`	Dependence of Minimum Operating Voltage (VDDmin) on Block Size of 90-nm CMOS Ring Oscillators and its Implications in Low Power DFM. ISQED Taro Niiyama, Piao Zhe, Koichi Ishida, Masami Murakata, Makoto Takamiya, Takayasu Sakurai
2008	—	`conf`	Expected vectorless Teacher-Student Swap (TSS) test method with dual power supply voltages for 0.3V homogeneous multi-core LSI's. CICC Taro Niiyama, Koichi Ishida, Makoto Takamiya, Takayasu Sakurai
2008	—	`conf`	Experimental assessment of logic circuit performance variability with regular fabrics at 90nm technology node. ESSCIRC Sungdae Choi, Katsuyuki Ikeuchi, Hyunkyung Kim, Kenichi Inagaki, Masami Murakata, Nobuyuki Nishiguchi, Makoto Takamiya, Takayasu Sakurai
2008	A	`conf`	Increasing minimum operating voltage (V ISLPED Taro Niiyama, Piao Zhe, Koichi Ishida, Masami Murakata, Makoto Takamiya, Takayasu Sakurai
2008	A	`conf`	Next-generation power-aware design. ISLPED Takayasu Sakurai
2008	—	`conf`	Solving issues of integrated circuits by 3D-stacking meeting with the era of power, integrity attackers and NRE explosion and a bit of future. ESSCIRC Takayasu Sakurai
2007	—	`conf`	A 0.14pJ/b Inductive-Coupling Inter-Chip Data Transceiver with Digitally-Controlled Precise Pulse Shaping. ISSCC Noriyuki Miura, Hiroki Ishikuro, Takayasu Sakurai, Tadahiro Kuroda
2007	J	`jnl`	A 1 Tb/s 3 W Inductive-Coupling Transceiver for 3D-Stacked Inter-Chip Clock and Data Link. IEEE J. Solid State Circuits Noriyuki Miura, Daisuke Mizoguchi, Mari Inoue, Kiichi Niitsu, Yoshihiro Nakagawa, Masamoto Tago, Muneo Fukaishi, Takayasu Sakurai, Tadahiro Kuroda
2007	J	`jnl`	A Self-Alignment Row-by-Row Variable- IEICE Trans. Electron. Fayez Robert Saliba, Hiroshi Kawaguchi, Takayasu Sakurai
2007	—	`conf`	A Wide Range Spatial Frequency Analysis of Intra-Die Variations with 4-mm 4000 × 1 Transistor Arrays in 90nm CMOS. CICC David Levacq, Takuya Minakawa, Makoto Takamiya, Takayasu Sakurai
2007	J	`jnl`	An Organic FET SRAM With Back Gate to Increase Static Noise Margin and Its Application to Braille Sheet Display. IEEE J. Solid State Circuits Makoto Takamiya, Tsuyoshi Sekitani, Yusaku Kato, Hiroshi Kawaguchi, Takao Someya, Takayasu Sakurai
2007	J	`jnl`	An Outside-Rail Opamp Design Relaxing Low-Voltage Constraint on Future Scaled Transistors. IEICE Trans. Electron. Koichi Ishida, Atit Tamtrakarn, Hiroki Ishikuro, Makoto Takamiya, Takayasu Sakurai
2007	J	`jnl`	Closed-Form Expressions for Crosstalk Noise and Worst-Case Delay on Capacitively Coupled Distributed RC Lines. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Hiroshi Kawaguchi, Danardono Dwi Antono, Takayasu Sakurai
2007	J	`jnl`	Crosstalk Countermeasures for High-Density Inductive-Coupling Channel Array. IEEE J. Solid State Circuits Noriyuki Miura, Takayasu Sakurai, Tadahiro Kuroda
2007	J	`jnl`	Daisy Chain Transmitter for Power Reduction in Inductive-Coupling CMOS Link. IEICE Trans. Electron. Kiichi Niitsu, Noriyuki Miura, Mari Inoue, Yoshihiro Nakagawa, Masamoto Tago, Masayuki Mizuno, Takayasu Sakurai, Tadahiro Kuroda
2007	—	`conf`	Design Solutions for a Multi-Object Wireless Power Transmission Sheet Based on Plastic Switches. ISSCC Makoto Takamiya, Tsuyoshi Sekitani, Yoshio Miyamoto, Yoshiaki Noguchi, Hiroshi Kawaguchi, Takao Someya, Takayasu Sakurai
2007	—	`conf`	Half VDD Clock-Swing Flip-Flop with Reduced Contention for up to 60% Power Saving in Clock Distribution. ESSCIRC David Levacq, Muhammad Yazid, Hiroshi Kawaguchi, Makoto Takamiya, Takayasu Sakurai
2007	—	`conf`	Meeting with the Forthcoming IC Design "The Era of Power, Variability and NRE Explosion and a Bit of the Future". ASP-DAC Takayasu Sakurai
2007	—	`conf`	Meeting with the forthcoming IC design. SBCCI Takayasu Sakurai
2007	J	`jnl`	Stacked-Chip Implementation of On-Chip Buck Converter for Distributed Power Supply System in SiPs. IEEE J. Solid State Circuits Kohei Onizuka, Kenichi Inagaki, Hiroshi Kawaguchi, Makoto Takamiya, Takayasu Sakurai
2006	J	`jnl`	$V_rm DD$-Hopping Accelerators for On-Chip Power Supply Circuit to Achieve Nanosecond-Order Transient Time. IEEE J. Solid State Circuits Kohei Onizuka, Hiroshi Kawaguchi, Makoto Takamiya, Takayasu Sakurai
2006	—	`conf`	A 0.5-V sigma-delta modulator using analog T-switch scheme for the subthreshold leakage suppression. ASP-DAC Koichi Ishida, Atit Tamtrakarn, Takayasu Sakurai
2006	J	`jnl`	A 1.2 Gbps Non-contact 3D-Stacked Inter-Chip Data Communications Technology. IEICE Trans. Electron. Daisuke Mizoguchi, Noriyuki Miura, Takayasu Sakurai, Tadahiro Kuroda
2006	J	`jnl`	A 195-gb/s 1.2-W inductive inter-chip wireless superconnect with transmit power control scheme for 3-D-stacked system in a package. IEEE J. Solid State Circuits Noriyuki Miura, Daisuke Mizoguchi, Mari Inoue, Takayasu Sakurai, Tadahiro Kuroda
2006	—	`conf`	A 1Tb/s 3W inductive-coupling transceiver for inter-chip clock and data link. ISSCC Noriyuki Miura, Daisuke Mizoguchi, Mari Inoue, Kiichi Niitsu, Yoshihiro Nakagawa, Masamoto Tago, Muneo Fukaishi, Takayasu Sakurai, Tadahiro Kuroda
2006	—	`conf`	An Organic FET SRAM for Braille Sheet Display with Back Gate to Increase Static Noise Margin. ISSCC Makoto Takamiya, Tsuyoshi Sekitani, Yusaku Kato, Hiroshi Kawaguchi, Teruki Someya, Takayasu Sakurai
2006	—	`conf`	Chip-to-Chip Inductive Wireless Power Transmission System for SiP Applications. CICC Kohei Onizuka, Hiroshi Kawaguchi, Makoto Takamiya, Tadahiro Kuroda, Takayasu Sakurai
2006	—	`conf`	Compact outside-rail circuit structure by single-cascode two-transistor topology. CICC Atit Tamtrakarn, Hiroki Ishikuro, Koichi Ishida, Takayasu Sakurai
2006	J	`jnl`	Leakage-suppressed clock-gating circuit with Zigzag Super Cut-off CMOS (ZSCCMOS) for leakage-dominant sub-70-nm and sub-1-V-V IEEE Trans. Very Large Scale Integr. Syst. Kyeong-Sik Min, Hun-Dae Choi, H.-Y. Choi, Hiroshi Kawaguchi, Takayasu Sakurai
2006	J	`jnl`	Low-Power Low-Leakage FPGA Design Using Zigzag Power Gating, Dual-V IEICE Trans. Electron. Canh Quang Tran, Hiroshi Kawaguchi, Takayasu Sakurai
2006	J	`jnl`	Managing subthreshold leakage in charge-based analog circuits with low-V IEEE J. Solid State Circuits Koichi Ishida, Kouichi Kanda, Atit Tamtrakarn, Hiroshi Kawaguchi, Takayasu Sakurai
2006	J	`jnl`	Simple Waveform Model of Inductive Interconnects by Delayed Quadratic Transfer Function with Application to Scaling Trend of Inductive Effects in VLSI's. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Danardono Dwi Antono, Kenichi Inagaki, Hiroshi Kawaguchi, Takayasu Sakurai
2006	J	`jnl`	Trends of On-Chip Interconnects in Deep Sub-Micron VLSI. IEICE Trans. Electron. Danardono Dwi Antono, Kenichi Inagaki, Hiroshi Kawaguchi, Takayasu Sakurai
2005	J	`jnl`	Analysis and design of inductive coupling and transceiver circuit for inductive inter-chip wireless superconnect. IEEE J. Solid State Circuits Noriyuki Miura, Daisuke Mizoguchi, Takayasu Sakurai, Tadahiro Kuroda
2005	J	`jnl`	Cut-and-paste customization of organic FET integrated circuit and its application to electronic artificial skin. IEEE J. Solid State Circuits Hiroshi Kawaguchi, Takao Someya, Tsuyoshi Sekitani, Takayasu Sakurai
2005	J	`jnl`	Frequency-voltage cooperative CPU power control: A design rule and its application by feedback prediction. Syst. Comput. Jpn. Keisuke Toyama, Satoshi Misaka, Kazuo Aisaka, Toshiyuki Aritsuka, Kunio Uchiyama, Koichiro Ishibashi, Hiroshi Kawaguchi, Takayasu Sakurai
2005	—	`conf`	More than two orders of magnitude leakage current reduction in look-up table for FPGAs. ISCAS (5) Canh Quang Tran, Hiroshi Kawaguchi, Takayasu Sakurai
2005	J	`jnl`	Row-by-Row Dynamic Source-Line Voltage Control (RRDSV) Scheme for Two Orders of Magnitude Leakage Current Reduction of Sub-1-V- IEICE Trans. Electron. Kyeong-Sik Min, Kouichi Kanda, Hiroshi Kawaguchi, Kenichi Inagaki, Fayez Robert Saliba, Hoon-Dae Choi, Hyun-young Choi, Daejeong Kim, Dong Myong Kim, Takayasu Sakurai
2005	—	`conf`	Subthreshold-leakage suppressed switched capacitor circuit based on super cut-off CMOS (SCCMOS). ISCAS (4) Koichi Ishida, Kouichi Kanda, Atit Tamtrakarn, Hiroshi Kawaguchi, Takayasu Sakurai
2005	J	`jnl`	μITRON-LP: power-conscious real-time OS based on cooperative voltage scaling for multimedia applications. IEEE Trans. Multim. Hiroshi Kawaguchi, Youngsoo Shin, Takayasu Sakurai
2004	J	`jnl`	90% write power-saving SRAM using sense-amplifying memory cell. IEEE J. Solid State Circuits Kouichi Kanda, Hattori Sadaaki, Takayasu Sakurai
2004	—	`conf`	Cross talk countermeasures in inductive inter-chip wireless superconnect. CICC Noriyuki Miura, Daisuke Mizoguchi, Takayasu Sakurai, Tadahiro Kuroda
2004	—	`conf`	Low power digital circuit design. ESSCIRC Takayasu Sakurai
2004	—	`conf`	Observation of one-fifth-of-a-clock wake-up time of power-gated circuit. CICC Takayuki Miyazaki, Canh Quang Tran, Hiroshi Kawaguchi, Takayasu Sakurai
2004	J	`jnl`	Statistical leakage current reduction in high-leakage environments using locality of block activation in time domain. IEEE J. Solid State Circuits Jin-Hyeok Choi, Yingxue Xu, Takayasu Sakurai
2003	A*	`conf`	Reshaping EDA for power. DAC Jan M. Rabaey, Dennis Sylvester, David T. Blaauw, Kerry Bernstein, Jerry Frenkil, Mark Horowitz, Wolfgang Nebel, Takayasu Sakurai, Andrew Yang
2003	—	`conf`	Statistical leakage current reduction by self-timed cut-off scheme for high leakage environments. CICC Jin-Hyeok Choi, Takayasu Sakurai
2003	J	`jnl`	VTCMOS characteristics and its optimum conditions predicted by a compact analytical model. IEEE Trans. Very Large Scale Integr. Syst. Hyunsik Im, Takashi Inukai, Hiroyuki Gomyo, Toshiro Hiramoto, Takayasu Sakurai
2002	—	`conf`	CMOS charge pumps using cross-coupled charge transfer switches with improved voltage pumping gain and low gate-oxide stress for low-voltage memory circuits. ISCAS (5) Kyeong-Sik Min, Young-Hee Kim, Jin-Hong Ahn, Jin-Yong Chung, Takayasu Sakurai
2002	J	`jnl`	Energy-Constrained V J. Circuits Syst. Comput. Seongsoo Lee, Seungjun Lee, Takayasu Sakurai
2002	—	`conf`	Low-Power and High-Speed V VLSI Design with Low Supply Voltage through Cooperation between Levels (invited). ISQED Takayasu Sakurai
2002	A	`conf`	Minimizing power across multiple technology and design levels. ICCAD Takayasu Sakurai
2002	J	`jnl`	Power distribution analysis of VLSI interconnects using model orderreduction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Youngsoo Shin, Takayasu Sakurai
2002	A	`conf`	Power-conscious interconnect buffer optimization with improved modeling of driver MOSFET and Its implications to bulk and SOI CMOS technology. ISLPED Koichi Nose, Takayasu Sakurai
2002	J	`jnl`	V IEEE J. Solid State Circuits Koichi Nose, Masayuki Hirabayashi, Hiroshi Kawaguchi, Seongsoo Lee, Takayasu Sakurai
2001	—	`conf`	An LSI for VDD-hopping and MPEG4 system based on the chip. ISCAS (4) Hiroshi Kawaguchi, Gang Zhang, Seongsoo Lee, Takayasu Sakurai
2001	—	`conf`	Cooperative voltage scaling (CVS) between OS and applications for low-power real-time systems. CICC Youngsoo Shin, Hiroshi Kawaguchi, Takayasu Sakurai
2001	A*	`conf`	Coupling-Driven Bus Design for Low-Power Application-Specific Systems. DAC Youngsoo Shin, Takayasu Sakurai
2001	J	`jnl`	Design impact of positive temperature dependence on drain current in sub-1-V CMOS VLSIs. IEEE J. Solid State Circuits Kouichi Kanda, Kouichi Nose, Hiroshi Kawaguchi, Takayasu Sakurai
2001	A	`conf`	Design methodology and optimization strategy for dual-VTH scheme using commercially available tools. ISLPED Masayuki Hirabayashi, Koichi Nose, Takayasu Sakurai
2001	A	`conf`	Estimation of power distribution in VLSI interconnects. ISLPED Youngsoo Shin, Takayasu Sakurai
2001	J	`jnl`	Power-conscious Scheduling for Real-time Embedded Systems Design. VLSI Design Youngsoo Shin, Kiyoung Choi, Takayasu Sakurai
2001	—	`conf`	V CICC Koichi Nose, Masayuki Hirabayashi, Hiroshi Kawaguchi, Seongsoo Lee, Takayasu Sakurai
2001	A	`conf`	VTCMOS characteristics and its optimum conditions predicted by a compact analytical model. ISLPED Hyunsik Im, Takashi Inukai, Hiroyuki Gomyo, Toshiro Hiramoto, Takayasu Sakurai
2001	A	`conf`	Variable threshold CMOS (VTCMOS) in series connected circuits. ISLPED Takashi Inukai, Toshiro Hiramoto, Takayasu Sakurai
2000	J	`jnl`	A super cut-off CMOS (SCCMOS) scheme for 0.5-V supply voltage with picoampere stand-by current. IEEE J. Solid State Circuits Hiroshi Kawaguchi, Koichi Nose, Takayasu Sakurai
2000	J	`jnl`	Analysis and future trend of short-circuit power. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Koichi Nose, Takayasu Sakurai
2000	—	`conf`	Boosted gate MOS (BGMOS): device/circuit cooperation scheme to achieve leakage-free giga-scale integration. CICC Takashi Inukai, Makoto Takamiya, Kouichi Nose, Hiroshi Kawaguchi, Toshiro Hiramoto, Takayasu Sakurai
2000	—	`conf`	Compact yet high performance (CyHP) library for short time-to-market with new technologies. ASP-DAC Nguyen Minh Duc, Takayasu Sakurai
2000	—	`conf`	Design challenges for 0.1um and beyond: embedded tutorial. ASP-DAC Takayasu Sakurai
2000	—	`conf`	Optimization of VDD and VTH for low-power and high speed applications. ASP-DAC Koichi Nose, Takayasu Sakurai
2000	A	`conf`	Power Optimization of Real-Time Embedded Systems on Variable Speed Processors. ICCAD Youngsoo Shin, Kiyoung Choi, Takayasu Sakurai
2000	—	`conf`	Reducing Power Consumption of CMOS VLSI's through VDD and VTH Control. ISQED Takayasu Sakurai
2000	—	`conf`	Run-time power control scheme using software feedback loop for low-power real-time application. ASP-DAC Seongsoo Lee, Takayasu Sakurai
2000	A*	`conf`	Run-time voltage hopping for low-power real-time systems. DAC Seongsoo Lee, Takayasu Sakurai
2000	A	`conf`	Voltage dependent gate capacitance and its impact in estimating power and delay of CMOS digital circuits with low supply voltage (poster session). ISLPED Koichi Nose, Soo-Ik Chae, Takayasu Sakurai
1999	—	`conf`	Design impact of positive temperature dependence of drain current in sub 1 V CMOS VLSIs. CICC Kouichi Kanda, Kouichi Nose, Hiroshi Kawaguchi, Takayasu Sakurai
1998	C	`conf`	A fine-grain, current mode scheme for VLSI proximity search engine. ICCD Seiji Takeuchi, Takayasu Sakurai
1998	J	`jnl`	A reduced clock-swing flip-flop (RCSFF) for 63% power reduction. IEEE J. Solid State Circuits Hiroshi Kawaguchi, Takayasu Sakurai
1998	—	`conf`	Delay and Noise Formulas for Capacitively Coupled Distributed RC Lines. ASP-DAC Hiroshi Kawaguchi, Takayasu Sakurai
1998	—	`conf`	Integrated Current Sensing Device for Micro IDDQ Test. Asian Test Symposium Koichi Nose, Takayasu Sakurai
1998	J	`jnl`	Variable supply-voltage scheme for low-power high-speed CMOS digital design. IEEE J. Solid State Circuits Tadahiro Kuroda, Kojiro Suzuki, Shinji Mita, Tetsuya Fujita, Fumiyuki Yamane, Fumihiko Sano, Akihiko Chiba, Yoshinori Watanabe, Koji Matsuda, Takeo Maeda, Takayasu Sakurai, Tohru Furuyama
1996	J	`jnl`	A 0.9-V, 150-MHz, 10-mW, 4 mm IEEE J. Solid State Circuits Tadahiro Kuroda, Tetsuya Fujita, Shinji Mita, Tetsu Nagamatsu, Shinichi Yoshioka, Kojiro Suzuki, Fumihiko Sano, Masayuki Norishima, Masayuki Murota, Makoto Kako, Masaaki Kinugawa, Masakazu Kakurnu, Takayasu Sakurai
1996	J	`jnl`	A swing restored pass-transistor logic-based multiply and accumulate circuit for multimedia applications. IEEE J. Solid State Circuits Akilesh Parameswar, Hiroyuki Hara, Takayasu Sakurai
1996	A	`conf`	Substrate noise influence on circuit performance in variable threshold-voltage scheme. ISLPED Tadahiro Kuroda, Tetsuya Fujita, Shinji Mita, Toshiaki Mori, Kenji Matsuo, Masakazu Kakumu, Takayasu Sakurai
1996	J	`jnl`	Threshold-Volgage control schemes through substrate-bias for low-power high-speed CMOS LSI design. J. VLSI Signal Process. Tadahiro Kuroda, Takayasu Sakurai
1994	J	`jnl`	A 110-MHz/1-Mb synchronous TagRAM. IEEE J. Solid State Circuits Yasuo Unekawa, Tsuguo Kobayashi, Tsukasa Shirotori, Yukihiro Fujimoto, Takayoshi Shimazawa, Kazutaka Nogami, Takehiko Nakao, Kazukiro Sawada, Masataka Matsui, Takayasu Sakurai, Man Kit Tang, William A. Huffman
1994	J	`jnl`	A 200 MHz 13 mm IEEE J. Solid State Circuits Masataka Matsui, Hiroyuki Hara, Yoshiharu Uetani, Lee-Sup Kim, Tetsu Nagamatsu, Yoshinori Watanabe, Akihiko Chiba, Kouji Matsuda, Takayasu Sakurai
1993	C	`conf`	High-Speed Circuit Design with Scaled-Down MOSFET's and Low Supply Voltage. ISCAS Takayasu Sakurai
1992	J	`jnl`	0.5- mu m 3.3-V BiCMOS standard cells with 32-kilobyte cache and ten-port register file. IEEE J. Solid State Circuits Hiroyuki Hara, Takayasu Sakurai, Tetsu Nagamatsu, Katsuhiro Seta, Hiroshi Momose, Yoichirou Niitsu, Hiroyuki Miyakawa, Kouji Matsuda, Yoshinori Watanabe, Fumihiko Sano, Akihiko Chiba
1992	J	`jnl`	A unified theory for mixed CMOS/BiCMOS buffer optimization. IEEE J. Solid State Circuits Takayasu Sakurai
1992	J	`jnl`	Fast simulated diffusion: an optimization algorithm for multiminimum problems and its application to MOSFET model parameter extraction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Takayasu Sakurai, Bill Lin, A. Richard Newton
1991	J	`jnl`	0.5- mu m 2 M-transistor BiPNMOS channelless gate array. IEEE J. Solid State Circuits Hiroyuki Hara, Takayasu Sakurai, Makoto Noda, Tetsu Nagamatsu, Katsuhiro Seta, Hiroshi Momose, Yoichirou Niitsu, Hiroyuki Miyakawa, Yoshinori Watanabe
1991	J	`jnl`	Delay analysis of series-connected MOSFET circuits. IEEE J. Solid State Circuits Takayasu Sakurai, A. Richard Newton
1990	J	`jnl`	A 9-ns HIT-delay 32-kbyte cache macro for high-speed RISC. IEEE J. Solid State Circuits Kazutaka Nogami, Takayasu Sakurai, Kazuhiro Sawada, Kenji Sakaue, Yuichi Miyazawa, Shinichi Tanaka, Ypocjo Hiruta, Katsuto Katoh, Toshinari Takayanagi, Tsukasa Shirotori, Yasuo Itoh, Masanori Uchida, Tetsuya Iizuka
1990	J	`jnl`	Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas. IEEE J. Solid State Circuits Takayasu Sakurai, A. Richard Newton
1989	J	`jnl`	A 32 kbyte integrated cache memory. IEEE J. Solid State Circuits Kazuhiro Sawada, Takayasu Sakurai, Kazutaka Nogami, Tsukasa Shirotori, Toshinari Takayanagi, Tetsuya Iizuka, Takeo Maeda, Jinichi Matsunaga, Hiromichi Fuji, Kenji Maeguchi, Kiyoshi Kobayashi, Tomoyuki Ando, Yoshiki Hayakashi, Akio Miyoshi, Kazuyuki Sato
1988	J	`jnl`	A 30- mu A data-retention pseudostatic RAM with virtually static RAM mode. IEEE J. Solid State Circuits Kazuhiro Sawada, Takayasu Sakurai, Kazutaka Nogami, Katsuhiko Sato, Tsukasa Shirotori, Masakazu Kakuma, Shigeru Morita, Masaaki Kinugawa, Tetsuya Asami, Kazuhito Narita, Jun-Ichi Matsunaga, Akira Higuchi, Mitsuo Isobe, Tetsuya Iizuka
1988	A	`conf`	CMOS inverter delay and other formulas using alpha -power law MOS model. ICCAD Takayasu Sakurai
1988	C	`conf`	Large memory embedded ASICs. ICCD Tetsuya Iizuka, Takayasu Sakurai, J. Matsunaga, K. Maeguchi, K. Kawagai, T. Kobayashi, Y. Shiotari, K. Kobayashi, T. Miyoshi
1988	J	`jnl`	Optimization of CMOS arbiter and synchronizer circuits with submicrometer MOSFETs. IEEE J. Solid State Circuits Takayasu Sakurai