Takashi Tokairin

13 papers Journal 7Unranked 6
YearRankTypeTitle / Venue / Authors
2018 — conf
A 15mW -105dBm Image-Sparse-Sliding-IF Receiver with Transformer-Based on-Chip Q-Enhanced RF Matching Network for a 113dB-Link-Budget BLE 5.0 TRX.
ESSCIRC
Tuan Thanh Ta, Yosuke Ogasawara, Tong Wang, Masayoshi Oshiro, Naotaka Koide, Akihide Sai, Takashi Tokairin
2018 — conf
An 113DB-Link-Budget Bluetooth-5 SoC with an 8dBm 22%-Efficiency TX.
VLSI Circuits
Tong Wang, Yosuke Ogasawara, Yuki Tuda, Tuan Thanh Ta, Masayoshi Oshiro, Jun Ihara, Tatsuhiko Maruyama, Toru Hashimoto, Akihide Sai, Takashi Tokairin
2017 J jnl
A 3.2mA-RX 3.5mA-TX Fully Integrated SoC for Bluetooth Low Energy System.
IEICE Trans. Electron.
Masayoshi Oshiro, Tatsuhiko Maruyama, Takashi Tokairin, Yuki Tuda, Tong Wang, Naotaka Koide, Yosuke Ogasawara, Tuan Thanh Ta, Hiroshi Yoshida, Kenichi Sami
2016 — conf
26.1 A 5.5mW ADPLL-based receiver with hybrid-loop interference rejection for BLE application in 65nm CMOS.
ISSCC
Hidenori Okuni, Akihide Sai, Tuan Thanh Ta, Satoshi Kondo, Takashi Tokairin, Masanori Furuta, Tetsuro Itakura
2016 — conf
A 3.2 mA-RX 3.5 mA-TX fully integrated SoC for Bluetooth Low Energy.
A-SSCC
Masayoshi Oshiro, Tatsuhiko Maruyama, Takashi Tokairin, Yuki Tuda, Tong Wang, Naotaka Koide, Yosuke Ogasawara, Tuan Thanh Ta, Hiroshi Yoshida, Kenichi Sami
2016 J jnl
A 5.5 mW ADPLL-Based Receiver With a Hybrid Loop Interference Rejection for BLE Application in 65 nm CMOS.
IEEE J. Solid State Circuits
Akihide Sai, Hidenori Okuni, Tuan Thanh Ta, Satoshi Kondo, Takashi Tokairin, Masanori Furuta, Tetsuro Itakura
2012 — conf
A 280nW, 100kHz, 1-cycle start-up time, on-chip CMOS relaxation oscillator employing a feedforward period control scheme.
VLSIC
Takashi Tokairin, Koichi Nose, Koichi Takeda, Koichiro Noguchi, Tadashi Maeda, Kazuyoshi Kawai, Masayuki Mizuno
2011 J jnl
A Low-IF/Zero-IF Reconfigurable Analog Baseband IC With an I/Q Imbalance Cancellation Scheme.
IEEE J. Solid State Circuits
Masaki Kitsunezuka, Takashi Tokairin, Tadashi Maeda, Muneo Fukaishi
2010 J jnl
A 2.1-to-2.8-GHz Low-Phase-Noise All-Digital Frequency Synthesizer With a Time-Windowed Time-to-Digital Converter.
IEEE J. Solid State Circuits
Takashi Tokairin, Mitsuji Okada, Masaki Kitsunezuka, Tadashi Maeda, Muneo Fukaishi
2010 — conf
A 2.1-to-2.8GHz all-digital frequency synthesizer with a time-windowed TDC.
ISSCC
Takashi Tokairin, Mitsuji Okada, Masaki Kitsunezuka, Tadashi Maeda, Muneo Fukaishi
2010 J jnl
Analytical Expression of Quantization Noise in Time-to-Digital Converter Based on the Fourier Series Analysis.
IEEE Trans. Circuits Syst. I Regul. Pap.
Tadashi Maeda, Takashi Tokairin
2006 J jnl
A Low-Power Dual-Band Triple-Mode WLAN CMOS Transceiver.
IEEE J. Solid State Circuits
Tadashi Maeda, Noriaki Matsuno, Shinichi Hori, Tomoyuki Yamase, Takashi Tokairin, Kiyoshi Yanagisawa, Hitoshi Yano, Robert Walkington, Keiichi Numata, Nobuhide Yoshida, Yuji Takahashi, Hikaru Hida
2006 J jnl
Low-power-consumption direct-conversion CMOS transceiver for multi-standard 5-GHz wireless LAN systems with channel bandwidths of 5-20 MHz.
IEEE J. Solid State Circuits
Tadashi Maeda, Hitoshi Yano, Shinichi Hori, Noriaki Matsuno, Tomoyuki Yamase, Takashi Tokairin, Robert Walkington, Nobuhide Yoshida, Keiichi Numata, Kiyoshi Yanagisawa, Yuji Takahashi, Masahiro Fujii, Hikaru Hida