Takashi Takemoto

41 papers B 1C 1Journal 14Unranked 25

Year	Rank	Type	Title / Venue / Authors
2024	B	`conf`	A Monte Carlo Tree Search for Budget-Constrained Combinatorial Optimal Facility Investment Problem with a Blackbox Objective Function. IEEE Big Data Shoma Nameki, Atsuyoshi Nakamura, Yusuke Yasugahira, Hiroshi Uchigaito, Michiaki Hiramatsu, Takashi Takemoto
2021	—	`conf`	4.6 A 144Kb Annealing System Composed of 9× 16Kb Annealing Processor Chips with Scalable Chip-to-Chip Connections for Large-Scale Combinatorial Optimization Problems. ISSCC Takashi Takemoto, Kasho Yamamoto, Chihiro Yoshimura, Masato Hayashi, Masafumi Tada, Hiroaki Saito, Mayumi Mashimo, Masanao Yamaoka
2021	—	`conf`	A 1.3-Mbit Annealing System Composed of Fully-Synchronized 9-board x 9-chip x 16-kbit Annealing Processor Chips for Large-Scale Combinatorial Optimization Problems. A-SSCC Kasho Yamamoto, Takashi Takemoto, Chihiro Yoshimura, Mayumi Mashimo, Masanao Yamaoka
2021	J	`jnl`	Minor-embedding heuristics for large-scale annealing processors with sparse hardware graphs of up to 102, 400 nodes. Soft Comput. Yuya Sugie, Yuki Yoshida, Normann Mertig, Takashi Takemoto, Hiroshi Teramoto, Atsuyoshi Nakamura, Ichigaku Takigawa, Shin-ichi Minato, Masanao Yamaoka, Tamiki Komatsuzaki
2021	J	`jnl`	STATICA: A 512-Spin 0.25M-Weight Annealing Processor With an All-Spin-Updates-at-Once Architecture for Combinatorial Optimization With Complete Spin-Spin Interactions. IEEE J. Solid State Circuits Kasho Yamamoto, Kazushi Kawamura, Kota Ando, Normann Mertig, Takashi Takemoto, Masanao Yamaoka, Hiroshi Teramoto, Akira Sakai, Shinya Takamaeda-Yamazaki, Masato Motomura
2020	—	`conf`	7.3 STATICA: A 512-Spin 0.25M-Weight Full-Digital Annealing Processor with a Near-Memory All-Spin-Updates-at-Once Architecture for Combinatorial Optimization with Complete Spin-Spin Interactions. ISSCC Kasho Yamamoto, Kota Ando, Normann Mertig, Takashi Takemoto, Masanao Yamaoka, Hiroshi Teramoto, Akira Sakai, Shinya Takamaeda-Yamazaki, Masato Motomura
2020	J	`jnl`	A 2× 30k-Spin Multi-Chip Scalable CMOS Annealing Processor Based on a Processing-in-Memory Approach for Solving Large-Scale Combinatorial Optimization Problems. IEEE J. Solid State Circuits Takashi Takemoto, Masato Hayashi, Chihiro Yoshimura, Masanao Yamaoka
2020	—	`conf`	CMOS Annealing Machine: A Domain-Specific Architecture for Combinatorial Optimization Problem. ASP-DAC Chihiro Yoshimura, Masato Hayashi, Takashi Takemoto, Masanao Yamaoka
2020	J	`jnl`	Minor-embedding heuristics for large-scale annealing processors with sparse hardware graphs of up to 102, 400 nodes. CoRR Yuya Sugie, Yuki Yoshida, Normann Mertig, Takashi Takemoto, Hiroshi Teramoto, Atsuyoshi Nakamura, Ichigaku Takigawa, Shin-ichi Minato, Masanao Yamaoka, Tamiki Komatsuzaki
2019	—	`conf`	A 2 ×30k-Spin Multichip Scalable Annealing Processor Based on a Processing-In-Memory Approach for Solving Large-Scale Combinatorial Optimization Problems. ISSCC Takashi Takemoto, Masato Hayashi, Chihiro Yoshimura, Masanao Yamaoka
2019	—	`conf`	A Cloud-ready Scalable Annealing Processor for Solving Large-scale Combinatorial Optimization Problems. VLSI Circuits Masato Hayashi, Takashi Takemoto, Chihiro Yoshimura, Masanao Yamaoka
2019	—	`conf`	CMOS Annealing Machine: an In-memory Computing Accelerator to Process Combinatorial Optimization Problems. CICC Masanao Yamaoka, Takuya Okuyama, Masato Hayashi, Chihiro Yoshimura, Takashi Takemoto
2018	J	`jnl`	A 50-Gb/s High-Sensitivity (-9.2 dBm) Low-Power (7.9 pJ/bit) Optical Receiver Based on 0.18-µm SiGe BiCMOS Technology. IEEE J. Solid State Circuits Takashi Takemoto, Yasunobu Matsuoka, Hiroki Yamashita, Yong Lee, Hideo Arimoto, Masaru Kokubo, Tatemi Ido
2018	—	`conf`	FPGA-Based QBoost with Large-Scale Annealing Processor and Accelerated Hyperparameter Search. ReConFig Takashi Takemoto, Normann Mertig, Masato Hayashi, Saki Susa-Tanaka, Hiroshi Teramoto, Atsuyoshi Nakamura, Ichigaku Takigawa, Shin-ichi Minato, Tamiki Komatsuzaki, Masanao Yamaoka
2018	—	`conf`	Graph Minors from Simulated Annealing for Annealing Machines with Sparse Connectivity. TPNC Yuya Sugie, Yuki Yoshida, Normann Mertig, Takashi Takemoto, Hiroshi Teramoto, Atsuyoshi Nakamura, Ichigaku Takigawa, Shin-ichi Minato, Masanao Yamaoka, Tamiki Komatsuzaki
2016	J	`jnl`	A 50-Gb/s Optical Transmitter Based on a 25-Gb/s-Class DFB-LD and a 0.18-µm SiGe BiCMOS LD Driver. IEICE Trans. Electron. Takashi Takemoto, Yasunobu Matsuoka, Hiroki Yamashita, Takahiro Nakamura, Yong Lee, Hideo Arimoto, Tatemi Ido
2016	—	`conf`	A 50.6-Gb/s 7.8-mW/Gb/s -7.4-dBm sensitivity optical receiver based on 0.18-µm SiGe BiCMOS technology. VLSI Circuits Takashi Takemoto, Yasunobu Matsuoka, Hiroki Yamashita, Yong Lee, Kenichi Akita, Hideo Arimoto, Masaru Kokubo, Tatemi Ido
2016	—	`conf`	A jitter-reduction packaging structure for a 56-Gb/s NRZ modulated optical receiver. OFC Takashi Takemoto, Yasunobu Matsuoka, Hiroki Yamashita, Yong Lee, Kenichi Akita, Hideo Arimoto, Masaru Kokubo
2015	—	`conf`	A 50-Gb/s NRZ-modulated optical transmitter based on a DFB-LD and a 0.18-µm SiGe BiCMOS LD driver. OFC Takashi Takemoto, Yasunobu Matsuoka, Yoshikazu Sugiyama, Hidenori Yonezawa, Hiroki Yamashita, Koichiro Adachi, Takahiro Nakamura, Etsuko Nomoto, Kouji Nakahara, Hideo Arimoto, Kenichi Osada, Tatemi Ido
2015	—	`conf`	An electrical and optical concurrent design methodology for enlarging jitter margin of 25.8-Gb/s optical interconnects. CICC Takashi Takemoto, Hiroki Yamashita, Yasunobu Matsuoka, Yong Lee, Masaru Kokubo
2015	—	`conf`	Wide-temperature-range 103.2 (25.8 × 4)-Gb/s optical link for data-center Interconnects using a 1.3-µm lens-integrated surface-emitting laser array. OFC Koichiro Adachi, Yasunobu Matsuoka, Takashi Takemoto, Takanori Suzuki, Shigehisa Tanaka, Akira Nakanishi, Kazuhiko Naoe
2014	C	`conf`	25-Gbps×4 optical transmitter with adjustable asymmetric pre-emphasis in 65-nm CMOS. ISCAS Toru Yazaki, Norio Chujo, Hiroki Yamashita, Takashi Takemoto, Yong Lee, Yasunobu Matsuoka
2014	J	`jnl`	A 25-Gb/s 2.2-W 65-nm CMOS Optical Transceiver Using a Power-Supply-Variation-Tolerant Analog Front End and Data-Format Conversion. IEEE J. Solid State Circuits Takashi Takemoto, Hiroki Yamashita, Fumio Yuki, Noboru Masuda, Hidehiro Toyoda, Norio Chujo, Yong Lee, Shinji Tsuji, Shinji Nishimura
2014	J	`jnl`	A 25-to-28 Gb/s High-Sensitivity (-9.7 dBm) 65 nm CMOS Optical Receiver for Board-to-Board Interconnects. IEEE J. Solid State Circuits Takashi Takemoto, Hiroki Yamashita, Toru Yazaki, Norio Chujo, Yong Lee, Yasunobu Matsuoka
2013	—	`conf`	A 25-Gb/s × 4-Ch, 8 × 8 mm OFC/NFOEC Norio Chujo, Toru Yazaki, Toshiaki Takai, Daichi Kawamura, Yasunobu Matsuoka, Yong Lee, Toshiki Sugawara, Hiroki Yamashita, Takashi Takemoto, Yoshiaki Ishigami, Kinya Yamazaki, Yoshinori Sunaga, Naoki Matsushima
2013	—	`conf`	A 4× 25-to-28Gb/s 4.9mW/Gb/s -9.7dBm high-sensitivity optical receiver based on 65nm CMOS for board-to-board interconnects. ISSCC Takashi Takemoto, Hiroki Yamashita, Toru Yazaki, Norio Chujo, Yong Lee, Yasunobu Matsuoka
2013	—	`conf`	Compact and power-efficient 100-Gbps CMOS-based transceiver. OFC/NFOEC Takashi Takemoto, Hiroki Yamashita, Fumio Yuki, Shinji Tsuji, Yong Lee, Koichiro Adachi, Kazunori Shinoda, Yasunobu Matsuoka, Toshiki Sugawara, Shinji Nishimura, Norio Chujo, Masaaki Nido, Kazuhiko Kurata, Junji Baba, Yoshinori Watanabe, Naoya Ikeda
2013	—	`conf`	High-frequency circuit design for 25 Gb/s×4 optical transceiver. ASP-DAC Norio Chujo, Takashi Takemoto, Fumio Yuki, Hiroki Yamashita
2012	—	`conf`	A 25-Gb/s 2.2-W optical transceiver using an analog FE tolerant to power supply noise and redundant data format conversion in 65-nm CMOS. VLSIC Takashi Takemoto, Hiroki Yamashita, Takehito Kamimura, Fumio Yuki, Noboru Masuda, Hidehiro Toyoda, Norio Chujo, Kenji Kogo, Yong Lee, Shinji Tsuji, Shinji Nishimura
2012	J	`jnl`	Optical Interconnects for Green Computers and Data Centers. Adv. Comput. Shinji Tsuji, Takashi Takemoto
2011	—	`conf`	10: 4 MUX and 4: 10 DEMUX gearbox LSI for 100-gigabit Ethernet link. ISSCC Goichi Ono, Keiki Watanabe, Takashi Muto, Hiroki Yamashita, Koji Fukuda, Noboru Masuda, Ryo Nemoto, Eiichi Suzuki, Takashi Takemoto, Fumio Yuki, Masayoshi Yagyu, Hidehiro Toyoda, Akihiro Kambe, Tatsuya Saito, Shinji Nishimura
2011	J	`jnl`	A 10: 4 MUX and 4: 10 DEMUX Gearbox LSI for 100-Gigabit Ethernet Link. IEEE J. Solid State Circuits Goichi Ono, Keiki Watanabe, Takashi Muto, Hiroki Yamashita, Koji Fukuda, Noboru Masuda, Ryo Nemoto, Eiichi Suzuki, Takashi Takemoto, Fumio Yuki, Masayoshi Yagyu, Hidehiro Toyoda, Masashi Kono, Akihiro Kambe, Seiichi Umai, Tatsuya Saito, Shinji Nishimura
2010	J	`jnl`	A 12.3-mW 12.5-Gb/s Complete Transceiver in 65-nm CMOS Process. IEEE J. Solid State Circuits Koji Fukuda, Hiroki Yamashita, Goichi Ono, Ryo Nemoto, Eiichi Suzuki, Noboru Masuda, Takashi Takemoto, Fumio Yuki, Tatsuya Saito
2010	—	`conf`	A 12.3mW 12.5Gb/s complete transceiver in 65nm CMOS. ISSCC Koji Fukuda, Hiroki Yamashita, Goichi Ono, Ryo Nemoto, Eiichi Suzuki, Takashi Takemoto, Fumio Yuki, Tatsuya Saito
2010	—	`conf`	A 25 Gb/s × 4-channel 74 mW/ch transimpedance amplifier in 65 nm CMOS. CICC Takashi Takemoto, Fumio Yuki, Hiroki Yamashita, Shinji Tsuji, Tatsuya Saito, Shinji Nishimura
2009	—	`conf`	10Gb/s receiver with track-and-hold-type linear phase detector and charge-redistribution 1 ISSCC Koji Fukuda, Hiroki Yamashita, Fumio Yuki, Goichi Ono, Ryo Nemoto, Eiichi Suzuki, Takashi Takemoto, Tatsuya Saito
2009	J	`jnl`	A 10-Gb/s Receiver With Track-and-Hold-Type Linear Phase Detector and Charge-Redistribution First-Order ΔΣ Modulator in 90-nm CMOS. IEEE J. Solid State Circuits Koji Fukuda, Hiroki Yamashita, Fumio Yuki, Goichi Ono, Ryo Nemoto, Eiichi Suzuki, Takashi Takemoto, Masashi Kono, Tatsuya Saito
2008	—	`conf`	An 8Gb/s Transceiver with 3×-Oversampling 2-Threshold Eye-Tracking CDR Circuit for -36.8dB-loss Backplane. ISSCC Koji Fukuda, Hiroki Yamashita, Fumio Yuki, Masayoshi Yagyu, Ryo Nemoto, Takashi Takemoto, Tatsuya Saito, Norio Chujo, Keiichi Yamamoto, Hisaaki Kanai, Atsuhiro Hayashi
2007	J	`jnl`	Circuit Implementation and Dynamics of a Two-Dimensional MOSFET Neuron Model. Int. J. Bifurc. Chaos Takashi Takemoto, Takashi Kohno, Kazuyuki Aihara
2006	J	`jnl`	MOSFET implementation of class I* neurons coupled by gap junctions. Artif. Life Robotics Takashi Takemoto, Takashi Kohno, Kazuyuki Aihara
2006	—	`conf`	Resolution independent rendering of deformable vector objects using graphics hardware. SIGGRAPH Sketches Yoshiyuki Kokojima, Kaoru Sugita, Takahiro Saito, Takashi Takemoto