Takashi Sato - RankMe

194 papers A* 13A 20B 2C 6Misc 4Journal 86Unranked 63

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	LMESN: A Leakage-Driven MOSFET Reservoir for Scalable and Ultra-Low-Power Temporal Inference. ASP-DAC Haoyuan, Masami Utsunomiya, Ryuko Seki, Quan Cheng, Weirong Dong, Feng Liang, Takashi Sato
2026	J	`jnl`	Prime Factorization Using Partially Constrained Multiple Quantum Annealing With Analytical and Pattern-Based Variable Reduction. IEEE Trans. Computers Xinyi Guo, Geguang Miao, Shinichi Nishizawa, Shinji Kimura, Takashi Sato
2026	J	`jnl`	YATA: Yet Another TFHE Accelerator with Key Compression and Radix-8 NTT. IACR Trans. Cryptogr. Hardw. Embed. Syst. Kotaro Matsuoka, Takashi Sato
2025	—	`conf`	A 22nm Resource-Frugal Hyper-Heterogeneous Multi-Modal System-on-Chip Towards In-Orbit Computing. CICC Quan Cheng, Qiufeng Li, Weirong Dong, Mingtao Zhang, Ruilin Zhang, Mingqiang Huang, Hao Yu, Yiyu Shi, Hiromitsu Awano, Takashi Sato, Longyang Lin, Masanori Hashimoto
2025	J	`jnl`	Beamforming Feedback-Based Respiration and Heart Rate Estimation Toward Firmware-Agnostic WiFi Sensing. IEEE Access Takamochi Kanda, Sota Kondo, Hiroki Shimomura, Takashi Sato, Hiromitsu Awano, Koji Yamamoto
2025	—	`conf`	Cryo-Compact Modeling Based on Sparse Gaussian Process. ASP-DAC Tetsuro Iwasaki, Takashi Sato, Michihiro Shintani
2025	J	`jnl`	Fast Parameter Optimization of Delayed Feedback Reservoir with Backpropagation and Gradient Descent. CoRR Sosei Ikeda, Hiromitsu Awano, Takashi Sato
2025	A	`conf`	Gaitcloud: Leveraging Spatial-Temporal Information for Lidar-Base Gait Recognition With a True-3D Gait Representation. WACV Shaoxiong Zhang, Hiromitsu Awano, Takashi Sato
2025	J	`jnl`	Hardware-Friendly Delayed-Feedback Reservoir for Multivariate Time-Series Classification. CoRR Sosei Ikeda, Hiromitsu Awano, Takashi Sato
2025	A*	`conf`	Lookup Table-based Multiplication-free All-digital DNN Accelerator Featuring Self-Synchronous Pipeline Accumulation. DAC Hiroto Tagata, Takashi Sato, Hiromitsu Awano
2025	J	`jnl`	Lookup Table-based Multiplication-free All-digital DNN Accelerator Featuring Self-Synchronous Pipeline Accumulation. CoRR Hiroto Tagata, Takashi Sato, Hiromitsu Awano
2025	J	`jnl`	Online Training and Inference System on Edge FPGA Using Delayed Feedback Reservoir. CoRR Sosei Ikeda, Hiromitsu Awano, Takashi Sato
2025	J	`jnl`	Online Training and Inference System on Edge FPGA Using Delayed Feedback Reservoir. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Sosei Ikeda, Hiromitsu Awano, Takashi Sato
2025	—	`conf`	Physics-based Modeling to Extend a MOSFET Compact Model for Cryogenic Operation. ASP-DAC Dondee Navarro, Shin Taniguchi, Chika Tanaka, Kazutoshi Kobayashi, Takashi Sato, Michihiro Shintani
2025	—	`conf`	Random Telegraph Noise Observed on 65-nm Bulk pMOS Transistors at 3.8K. ASP-DAC Takuma Kawakami, Takashi Sato, Hiromitsu Awano
2025	A	`conf`	SOME: Symmetric One-Hot Matching Elector - A Lightweight Microsecond Decoder for Quantum Error Correction. ICCAD Xinyi Guo, Geguang Miao, Shinichi Nishizawa, Hiromitsu Awano, Shinji Kimura, Takashi Sato
2025	J	`jnl`	SOME: Symmetric One-Hot Matching Elector - A Lightweight Microsecond Decoder for Quantum Error Correction. CoRR Xinyi Guo, Geguang Miao, Shinichi Nishizawa, Hiromitsu Awano, Shinji Kimura, Takashi Sato
2025	A*	`conf`	Weighted Range-Constrained Ising-Model Decoder for Quantum Error Correction. DAC Xinyi Guo, Hiromitsu Awano, Takashi Sato
2025	C	`conf`	Zero-Aware Regularization for Energy-Efficient Inference on Akida Neuromorphic Processor. ISCAS Takehiro Habara, Takashi Sato, Hiromitsu Awano
2024	—	`conf`	(Invited) Redefining Outliers for On-Wafer Electrical Testing. MLCAD Michihiro Shintani, Takashi Sato
2024	A	`conf`	DNA-Based Similar Image Retrieval via Triplet Network-Driven Encoder. DATE Takefumi Koike, Hiromitsu Awano, Takashi Sato
2024	J	`jnl`	Double MAC on a Cell: A 22-nm 8T-SRAM-Based Analog In-Memory Accelerator for Binary/Ternary Neural Networks Featuring Split Wordline. IEEE Open J. Circuits Syst. Hiroto Tagata, Takashi Sato, Hiromitsu Awano
2024	Misc	`conf`	Exploring Surface Code Decoding via Cryo-CMOS for Fault-Tolerant Quantum Computers. QCE Ruotai Wang, Takashi Sato, Hiromitsu Awano
2024	A	`conf`	Fast Parameter Optimization of Delayed Feedback Reservoir with Backpropagation and Gradient Descent. DATE Sosei Ikeda, Hiromitsu Awano, Takashi Sato
2024	B	`conf`	HOGE: Homomorphic Gate on An FPGA. ASPDAC Kotaro Matsuoka, Song Bian, Takashi Sato
2024	B	`conf`	Logic Locking over TFHE for Securing User Data and Algorithms. ASPDAC Kohei Suemitsu, Kotaro Matsuoka, Takashi Sato, Masanori Hashimoto
2024	Misc	`conf`	Square-Wave Defined Pulse Generator for High Fidelity Gate Operation of Superconducting Qubits. QCE Ryosuke Matsuo, Kazuhisa Ogawa, Hidehisa Shiorni, Makoto Negoro, Ryutaro Ohira, Takefumi Miyoshi, Michihiro Shintani, Hiromitsu Awano, Takashi Sato, Jun Shiomi
2024	A*	`conf`	Triplet Network-Based DNA Encoding for Enhanced Similarity Image Retrieval. DAC Takefumi Koike, Hiromitsu Awano, Takashi Sato
2023	A	`conf`	Improving Efficiency and Robustness of Gaussian Process Based Outlier Detection via Ensemble Learning. ITC Makoto Eiki, Tomoki Nakamura, Masuo Kajiyama, Michiko Inoue, Takashi Sato, Michihiro Shintani
2023	A	`conf`	Invited Paper: Overview of 2023 CAD Contest at ICCAD. ICCAD Takashi Sato, Chun-Yao Wang, Yu-Guang Chen, Tsung-Wei Huang
2023	J	`jnl`	Modular DFR: Digital Delayed Feedback Reservoir Model for Enhancing Design Flexibility. CoRR Sosei Ikeda, Hiromitsu Awano, Takashi Sato
2023	J	`jnl`	Modular DFR: Digital Delayed Feedback Reservoir Model for Enhancing Design Flexibility. ACM Trans. Embed. Comput. Syst. Sosei Ikeda, Hiromitsu Awano, Takashi Sato
2023	J	`jnl`	Uncertainty-Aware Haptic Shared Control With Humanoid Robots for Flexible Object Manipulation. IEEE Robotics Autom. Lett. Takumi Hara, Takashi Sato, Tetsuya Ogata, Hiromitsu Awano
2022	J	`jnl`	Adaptive Outlier Detection for Power MOSFETs Based on Gaussian Process Regression. CoRR Kyohei Shimozato, Michihiro Shintani, Takashi Sato
2022	—	`conf`	Characteristic Degradation of Power MOSFETs by X-Ray Irradiation and Their Recovery. IRPS Masato Shiozaki, Takashi Sato
2022	J	`jnl`	Efficient Analysis for Mitigation of Workload-Dependent Aging Degradation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Shumpei Morita, Song Bian, Michihiro Shintani, Takashi Sato
2022	J	`jnl`	Hardware-Friendly Delayed-Feedback Reservoir for Multivariate Time-Series Classification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Sosei Ikeda, Hiromitsu Awano, Takashi Sato
2022	A	`conf`	Overview of 2022 CAD Contest at ICCAD. ICCAD Yu-Guang Chen, Chun-Yao Wang, Tsung-Wei Huang, Takashi Sato
2022	—	`conf`	Respiratory Rate Estimation Based on WiFi Frame Capture. CCNC Takamochi Kanda, Takashi Sato, Hiromitsu Awano, Sota Kondo, Koji Yamamoto
2022	J	`jnl`	VisualNet: An End-to-End Human Visual System Inspired Framework to Reduce Inference Latency of Deep Neural Networks. IEEE Trans. Computers Tianchen Wang, Jiawei Zhang, Jinjun Xiong, Song Bian, Zheyu Yan, Meiping Huang, Jian Zhuang, Takashi Sato, Xiaowei Xu, Yiyu Shi
2021	J	`jnl`	APAS: Application-Specific Accelerators for RLWE-Based Homomorphic Linear Transformations. IEEE Trans. Inf. Forensics Secur. Song Bian, Dur-e-Shahwar Kundi, Kazuma Hirozawa, Weiqiang Liu, Takashi Sato
2021	J	`jnl`	APAS: Application-Specific Accelerators for RLWE-based Homomorphic Linear Transformations. IACR Cryptol. ePrint Arch. Song Bian, Dur-e-Shahwar Kundi, Kazuma Hirozawa, Weiqiang Liu, Takashi Sato
2021	J	`jnl`	Accelerating Parameter Extraction of Power MOSFET Models Using Automatic Differentiation. CoRR Michihiro Shintani, Aoi Ueda, Takashi Sato
2021	C	`conf`	Automatic Parallelism Tuning for Module Learning with Errors Based Post-Quantum Key Exchanges on GPUs. ISCAS Tatsuki Ono, Song Bian, Takashi Sato
2021	J	`jnl`	Automatic Parallelism Tuning for Module Learning with Errors Based Post-Quantum Key Exchanges on GPUs. IACR Cryptol. ePrint Arch. Tatsuki Ono, Song Bian, Takashi Sato
2021	J	`jnl`	Clonable PUF: On the Design of PUFs That Share Equivalent Responses. IACR Cryptol. ePrint Arch. Takashi Sato, Yuki Tanaka, Song Bian
2021	C	`conf`	Clonable PUF: on the Design of PUFs That Share Equivalent Responses. ISCAS Takashi Sato, Yuki Tanaka, Song Bian
2021	—	`conf`	Heart Rate Variability Extraction using Commodity Wi-Fi Devices via Time Domain Signal Processing. BHI Itsuki Shirakami, Takashi Sato
2021	—	`conf`	Motion Robust Remote Photoplethysmography via Frequency Domain Motion Artifact Reduction. BioCAS Suraj Hebbar, Takashi Sato
2021	A	`conf`	Overview of 2021 CAD Contest at ICCAD. ICCAD Tsung-Wei Huang, Yu-Guang Chen, Chun-Yao Wang, Takashi Sato
2021	A*	`conf`	Privacy-Preserving Medical Image Segmentation via Hybrid Trusted Execution Environment. DAC Song Bian, Weiwen Jiang, Takashi Sato
2021	—	`conf`	Towards Better Standard Cell Library: Optimizing Compound Logic Gates for TFHE. WAHC@CCS Kotaro Matsuoka, Yusuke Hoshizuki, Takashi Sato, Song Bian
2021	A*	`conf`	Virtual Secure Platform: A Five-Stage Pipeline Processor over TFHE. USENIX Security Symposium Kotaro Matsuoka, Ryotaro Banno, Naoki Matsumoto, Takashi Sato, Song Bian
2020	—	`conf`	A Tuning-Free Hardware Reservoir Based on MOSFET Crossbar Array for Practical Echo State Network Implementation. ASP-DAC Yuki Kume, Song Bian, Takashi Sato
2020	—	`conf`	BUNET: Blind Medical Image Segmentation Based on Secure UNET. MICCAI (2) Song Bian, Xiaowei Xu, Weiwen Jiang, Yiyu Shi, Takashi Sato
2020	J	`jnl`	BUNET: Blind Medical Image Segmentation Based on Secure UNET. CoRR Song Bian, Xiaowei Xu, Weiwen Jiang, Yiyu Shi, Takashi Sato
2020	A*	`conf`	Clustering Approach for Solving Traveling Salesman Problems via Ising Model Based Solver. DAC Akira Dan, Riu Shimizu, Takeshi Nishikawa, Song Bian, Takashi Sato
2020	A*	`conf`	ENSEI: Efficient Secure Inference via Frequency-Domain Homomorphic Convolution for Privacy-Preserving Visual Recognition. CVPR Song Bian, Tianchen Wang, Masayuki Hiromoto, Yiyu Shi, Takashi Sato
2020	J	`jnl`	ENSEI: Efficient Secure Inference via Frequency-Domain Homomorphic Convolution for Privacy-Preserving Visual Recognition. CoRR Song Bian, Tianchen Wang, Masayuki Hiromoto, Yiyu Shi, Takashi Sato
2020	J	`jnl`	Ed-PUF: Event-Driven Physical Unclonable Function for Camera Authentication in Reactive Monitoring System. IEEE Trans. Inf. Forensics Secur. Yue Zheng, Xiaojin Zhao, Takashi Sato, Yuan Cao, Chip-Hong Chang
2020	J	`jnl`	FedNNNN: Norm-Normalized Neural Network Aggregation for Fast and Accurate Federated Learning. CoRR Kenta Nagura, Song Bian, Takashi Sato
2020	—	`conf`	Influence of Device Parameter Variability on Current Sharing of Parallel-Connected SiC MOSFETs. ATS Yohei Nakamura, Naotaka Kuroda, Atsushi Yamaguchi, Ken Nakahara, Michihiro Shintani, Takashi Sato
2020	—	`conf`	Measurement of BTI-induced Threshold Voltage Shift for Power MOSFETs under Switching Operation. ATS Aoi Ueda, Michihiro Shintani, Michiko Inoue, Takashi Sato
2020	A	`conf`	NASS: Optimizing Secure Inference via Neural Architecture Search. ECAI Song Bian, Weiwen Jiang, Qing Lu, Yiyu Shi, Takashi Sato
2020	J	`jnl`	NASS: Optimizing Secure Inference via Neural Architecture Search. CoRR Song Bian, Weiwen Jiang, Qing Lu, Yiyu Shi, Takashi Sato
2020	J	`jnl`	Virtual Secure Platform: A Five-Stage Pipeline Processor over TFHE. CoRR Kotaro Matsuoka, Ryotaro Banno, Naoki Matsumoto, Takashi Sato, Song Bian
2019	A	`conf`	DArL: Dynamic Parameter Adjustment for LWE-based Secure Inference. DATE Song Bian, Masayuki Hiromoto, Takashi Sato
2019	A*	`conf`	Filianore: Better Multiplier Architectures for LWE-based Post-Quantum Key Exchange. DAC Song Bian, Masayuki Hiromoto, Takashi Sato
2019	J	`jnl`	GPU-based Ising computing for solving max-cut combinatorial optimization problems. Integr. Chase Cook, Hengyang Zhao, Takashi Sato, Masayuki Hiromoto, Sheldon X.-D. Tan
2019	J	`jnl`	Hardware-Accelerated Secured Naïve Bayesian Filter Based on Partially Homomorphic Encryption. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Song Bian, Masayuki Hiromoto, Takashi Sato
2019	—	`conf`	Heart Rate Estimation during Exercise from Photoplethysmographic Signals Using Convolutional Neural Network. BioCAS Masaki Nakamura, Takashi Sato
2019	—	`conf`	Towards practical homomorphic email filtering: a hardware-accelerated secure naïve bayesian filter. ASP-DAC Song Bian, Masayuki Hiromoto, Takashi Sato
2018	—	`conf`	A study on NBTI-induced delay degradation considering stress frequency dependence. ISQED Zuitoku Shin, Shumpei Morita, Song Bian, Michihiro Shintani, Masayuki Hiromoto, Takashi Sato
2018	J	`jnl`	Area Efficient Annealing Processor for Ising Model without Random Number Generator. IEICE Trans. Inf. Syst. Hidenori Gyoten, Masayuki Hiromoto, Takashi Sato
2018	J	`jnl`	Coin Flipping PUF: A Novel PUF With Improved Resistance Against Machine Learning Attacks. IEEE Trans. Circuits Syst. II Express Briefs Yuki Tanaka, Song Bian, Masayuki Hiromoto, Takashi Sato
2018	A*	`conf`	DWE: decrypting learning with errors with errors. DAC Song Bian, Masayuki Hiromoto, Takashi Sato
2018	J	`jnl`	Efficient Mini-Batch Training on Memristor Neural Network Integrating Gradient Calculation and Weight Update. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Satoshi Yamamori, Masayuki Hiromoto, Takashi Sato
2018	—	`conf`	Efficient worst-case timing analysis of critical-path delay under workload-dependent aging degradation. ASP-DAC Shumpei Morita, Song Bian, Michihiro Shintani, Masayuki Hiromoto, Takashi Sato
2018	A	`conf`	Enhancing the solution quality of hardware ising-model solver via parallel tempering. ICCAD Hidenori Gyoten, Masayuki Hiromoto, Takashi Sato
2018	—	`conf`	Fast And Robust Heart Rate Estimation From Videos Through Dynamic Region Selection. EMBC Yuya Fujita, Masayuki Hiromoto, Takashi Sato
2018	—	`conf`	Interpolation-Based Object Detection Using Motion Vectors for Embedded Real-Time Tracking Systems. CVPR Workshops Takayuki Ujiie, Masayuki Hiromoto, Takashi Sato
2018	A	`conf`	Ising-PUF: A machine learning attack resistant PUF featuring lattice like arrangement of Arbiter-PUFs. DATE Hiromitsu Awano, Takashi Sato
2018	J	`jnl`	MRO-PUF: Physically Unclonable Function with Enhanced Resistance against Machine Learning Attacks Utilizing Instantaneous Output of Ring Oscillator. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Masayuki Hiromoto, Motoki Yoshinaga, Takashi Sato
2018	J	`jnl`	PARHELIA: Particle Filter-Based Heart Rate Estimation From Photoplethysmographic Signals During Physical Exercise. IEEE Trans. Biomed. Eng. Yuya Fujita, Masayuki Hiromoto, Takashi Sato
2017	—	`conf`	Comparative study of path selection and objective function in replacing NBTI mitigation logic. ISQED Shumpei Morita, Song Bian, Michihiro Shintani, Masayuki Hiromoto, Takashi Sato
2017	J	`jnl`	Efficient Aging-Aware Failure Probability Estimation Using Augmented Reliability and Subset Simulation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Hiromitsu Awano, Takashi Sato
2017	—	`conf`	Efficient circuit failure probability calculation along product lifetime considering device aging. ASP-DAC Hiromitsu Awano, Masayuki Hiromoto, Takashi Sato
2017	J	`jnl`	Identification and Application of Invariant Critical Paths under NBTI Degradation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Song Bian, Shumpei Morita, Michihiro Shintani, Hiromitsu Awano, Masayuki Hiromoto, Takashi Sato
2017	A*	`conf`	LSTA: Learning-Based Static Timing Analysis for High-Dimensional Correlated On-Chip Variations. DAC Song Bian, Michihiro Shintani, Masayuki Hiromoto, Takashi Sato
2017	—	`conf`	Pattern based runtime voltage emergency prediction: An instruction-aware block sparse compressed sensing approach. ASP-DAC Yu-Guang Chen, Michihiro Shintani, Takashi Sato, Yiyu Shi, Shih-Chieh Chang
2017	J	`jnl`	RTN in Scaled Transistors for On-Chip Random Seed Generation. IEEE Trans. Very Large Scale Integr. Syst. Abinash Mohanty, Ketul B. Sutaria, Hiromitsu Awano, Takashi Sato, Yu Cao
2017	A	`conf`	SCAM: Secured content addressable memory based on homomorphic encryption. DATE Song Bian, Masayuki Hiromoto, Takashi Sato
2017	J	`jnl`	Scalable Device Array for Statistical Characterization of BTI-Related Parameters. IEEE Trans. Very Large Scale Integr. Syst. Hiromitsu Awano, Shumpei Morita, Takashi Sato
2017	J	`jnl`	Utilization of Path-Clustering in Efficient Stress-Control Gate Replacement for NBTI Mitigation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Shumpei Morita, Song Bian, Michihiro Shintani, Masayuki Hiromoto, Takashi Sato
2016	—	`conf`	Approximated Prediction Strategy for Reducing Power Consumption of Convolutional Neural Network Processor. CVPR Workshops Takayuki Ujiie, Masayuki Hiromoto, Takashi Sato
2016	J	`jnl`	Efficient Aging-Aware SRAM Failure Probability Calculation via Particle Filter-Based Importance Sampling. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Hiromitsu Awano, Masayuki Hiromoto, Takashi Sato
2016	A*	`conf`	Efficient transistor-level timing yield estimation via line sampling. DAC Hiromitsu Awano, Takashi Sato
2016	J	`jnl`	Fast Estimation of NBTI-Induced Delay Degradation Based on Signal Probability. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Song Bian, Michihiro Shintani, Masayuki Hiromoto, Takashi Sato
2016	—	`conf`	Nonlinear delay-table approach for full-chip NBTI degradation prediction. ISQED Song Bian, Michihiro Shintani, Shumpei Morita, Masayuki Hiromoto, Takashi Sato
2016	J	`jnl`	Path Clustering for Test Pattern Reduction of Variation-Aware Adaptive Path Delay Testing. J. Electron. Test. Michihiro Shintani, Takumi Uezono, Kazumi Hatayama, Kazuya Masu, Takashi Sato
2016	C	`conf`	Physically unclonable function using RTN-induced delay fluctuation in ring oscillators. ISCAS Motoki Yoshinaga, Hiromitsu Awano, Masayuki Hiromoto, Takashi Sato
2016	—	`conf`	Runtime NBTI Mitigation for Processor Lifespan Extension via Selective Node Control. ATS Song Bian, Michihiro Shintani, Zheng Wang, Masayuki Hiromoto, Anupam Chattopadhyay, Takashi Sato
2016	—	`conf`	Workload-Aware Worst Path Analysis of Processor-Scale NBTI Degradation. ACM Great Lakes Symposium on VLSI Song Bian, Michihiro Shintani, Shumpei Morita, Hiromitsu Awano, Masayuki Hiromoto, Takashi Sato
2015	J	`jnl`	An Error Correction Scheme through Time Redundancy for Enhancing Persistent Soft-Error Tolerance of CGRAs. IEICE Trans. Electron. Takashi Imagawa, Masayuki Hiromoto, Hiroyuki Ochi, Takashi Sato
2015	A	`conf`	ECRIPSE: an efficient method for calculating RTN-induced failure probability of an SRAM cell. DATE Hiromitsu Awano, Masayuki Hiromoto, Takashi Sato
2015	J	`jnl`	Introduction to: Special Issue on Cross-Layer System Design. ACM J. Emerg. Technol. Comput. Syst. Yiyu Shi, Takashi Sato
2014	J	`jnl`	A Variability-Aware Adaptive Test Flow for Test Quality Improvement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Michihiro Shintani, Takumi Uezono, Tomoyuki Takahashi, Kazumi Hatayama, Takashi Aikyo, Kazuya Masu, Takashi Sato
2014	J	`jnl`	Automation of Model Parameter Estimation for Random Telegraph Noise. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Hirofumi Shimizu, Hiromitsu Awano, Masayuki Hiromoto, Takashi Sato
2014	—	`conf`	Experimental validation of minimum operating-voltage-estimation for low supply voltage circuits. ISQED Takashi Sato, Junya Kawashima, Hiroshi Tsutsui, Hiroyuki Ochi
2014	J	`jnl`	Hypersphere Sampling for Accelerating High-Dimension and Low-Failure Probability Circuit-Yield Analysis. IEICE Trans. Electron. Shiho Hagiwara, Takanori Date, Kazuya Masu, Takashi Sato
2014	J	`jnl`	IDDQ Outlier Screening through Two-Phase Approach: Clustering-Based Filtering and Estimation-Based Current-Threshold Determination. IEICE Trans. Inf. Syst. Michihiro Shintani, Takashi Sato
2014	A	`conf`	Sensorless estimation of global device-parameters based on F ICCAD Michihiro Shintani, Takashi Sato
2014	J	`jnl`	State-Dependence of On-Chip Power Distribution Network Capacitance. IEICE Trans. Electron. Koh Yamanaga, Shiho Hagiwara, Ryo Takahashi, Kazuya Masu, Takashi Sato
2014	—	`conf`	Variability in device degradations: Statistical observation of NBTI for 3996 transistors. ESSDERC Hiromitsu Awano, Masayuki Hiromoto, Takashi Sato
2013	J	`jnl`	A Cost-Effective Selective TMR for Coarse-Grained Reconfigurable Architectures Based on DFG-Level Vulnerability Analysis. IEICE Trans. Electron. Takashi Imagawa, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato
2013	A	`conf`	A cost-effective selective TMR for heterogeneous coarse-grained reconfigurable architectures based on DFG-level vulnerability analysis. DATE Takashi Imagawa, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato
2013	—	`conf`	An adaptive current-threshold determination for IDDQ testing based on Bayesian process parameter estimation. ASP-DAC Michihiro Shintani, Takashi Sato
2013	J	`jnl`	Device-Parameter Estimation through IDDQ Signatures. IEICE Trans. Inf. Syst. Michihiro Shintani, Takashi Sato
2013	—	`conf`	Fast and memory-efficient GPU implementations of krylov subspace methods for efficient power grid analysis. ACM Great Lakes Symposium on VLSI Takumi Morishita, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato
2013	—	`conf`	High-speed DFG-level SEU vulnerability analysis for applying selective TMR to resource-constrained CGRA. ISQED Takashi Imagawa, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato
2013	A	`conf`	Hot-swapping architecture with back-biased testing for mitigation of permanent faults in functional unit array. DATE Zoltán Endre Rákossy, Masayuki Hiromoto, Hiroshi Tsutsui, Takashi Sato, Yukihiro Nakamura, Hiroyuki Ochi
2013	—	`conf`	Multi-trap RTN parameter extraction based on Bayesian inference. ISQED Hiromitsu Awano, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato
2013	J	`jnl`	Parallel Acceleration Scheme for Monte Carlo Based SSTA Using Generalized STA Processing Element. IEICE Trans. Electron. Hiroshi Yuasa, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato
2013	—	`conf`	Realization of frequency-domain circuit analysis through random walk. ASP-DAC Tetsuro Miyakawa, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato
2013	—	`conf`	Statistical simulation methods for circuit performance analysis. ASICON Takashi Sato
2012	Misc	`conf`	A Bayesian-based process parameter estimation using IDDQ current signature. VTS Michihiro Shintani, Takashi Sato
2012	J	`jnl`	A Variability-Aware Energy-Minimization Strategy for Subthreshold Circuits. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Junya Kawashima, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato
2012	J	`jnl`	Bayesian Estimation of Multi-Trap RTN Parameters Using Markov Chain Monte Carlo Method. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Hiromitsu Awano, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato
2012	A*	`conf`	Physics matters: statistical aging prediction under trapping/detrapping. DAC Jyothi Bhaskarr Velamala, Ketul Sutaria, Takashi Sato, Yu Cao
2012	J	`jnl`	Power Distribution Network Optimization for Timing Improvement with Statistical Noise Model and Timing Analysis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Takashi Enami, Takashi Sato, Masanori Hashimoto
2012	—	`conf`	Statistical aging under dynamic voltage scaling: A logarithmic model approach. CICC Jyothi Velamala, Ketul Sutaria, Hirofumi Shimizu, Hiromitsu Awano, Takashi Sato, Yu Cao
2012	—	`conf`	Statistical observations of NBTI-induced threshold voltage shifts on small channel-area devices. ISQED Takashi Sato, Hiromitsu Awano, Hirofttmi Shimizu, Hiroshi Tsutsui, Hiroyuki Ochi
2011	—	`conf`	A design strategy for sub-threshold circuits considering energy-minimization and yield-maximization. SoCC Junya Kawashima, Hiroyuki Ochi, Hiroshi Tsutsui, Takashi Sato
2011	—	`conf`	A fully pipelined implementation of Monte Carlo based SSTA on FPGAs. ISQED Hiroshi Yuasa, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato
2011	—	`conf`	Acceleration of random-walk-based linear circuit analysis using importance sampling. ACM Great Lakes Symposium on VLSI Tetsuro Miyakawa, Koh Yamanaga, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato
2010	J	`jnl`	A New LDMOS Transistor Macro-Modeling for Accurately Predicting Bias Dependence of Gate-Overlap Capacitance. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Takashi Sato, Toshiki Kanamoto, Saiko Kobayashi, Nobuhiko Goto, Takao Sato, Hitoshi Sugihara, Hiroo Masuda
2010	J	`jnl`	A Time-Slicing Ring Oscillator for Capturing Time-Dependent Delay Degradation and Power Supply Voltage Fluctuation. IEICE Trans. Electron. Takumi Uezono, Kazuya Masu, Takashi Sato
2010	J	`jnl`	A Universal Equivalent Circuit Model for Ceramic Capacitors. IEICE Trans. Electron. Koh Yamanaga, Shuhei Amakawa, Kazuya Masu, Takashi Sato
2010	—	`conf`	A routing architecture exploration for coarse-grained reconfigurable architecture with automated seu-tolerance evaluation. SoCC Takashi Imagawa, Masayuki Hiromoto, Hiroyuki Ochi, Takashi Sato
2010	—	`conf`	Application of generalized scattering matrix for prediction of power supply noise. SLIP Koh Yamanaga, Kazuya Masu, Takashi Sato
2010	C	`conf`	Decomposition of drain-current variation into gain-factor and threshold voltage variations. ISCAS Takashi Sato, Takumi Uezono, Noriaki Nakayama, Kazuya Masu
2010	J	`jnl`	Impact of Self-Heating in Wire Interconnection on Timing. IEICE Trans. Electron. Toshiki Kanamoto, Takaaki Okumura, Katsuhiro Furukawa, Hiroshi Takafuji, Atsushi Kurokawa, Koutaro Hachiya, Tsuyoshi Sakata, Masakazu Tanaka, Hidenari Nakashima, Hiroo Masuda, Takashi Sato, Masanori Hashimoto
2010	J	`jnl`	Linear Time Calculation of On-Chip Power Distribution Network Capacitance Considering State-Dependence. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Shiho Hagiwara, Koh Yamanaga, Ryo Takahashi, Kazuya Masu, Takashi Sato
2010	—	`conf`	Linear time calculation of state-dependent power distribution network capacitance. ISQED Shiho Hagiwara, Koh Yamanaga, Ryo Takahashi, Kazuya Masu, Takashi Sato
2010	J	`jnl`	Modeling the Overshooting Effect for CMOS Inverter Delay Analysis in Nanometer Technologies. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Zhangcai Huang, Atsushi Kurokawa, Masanori Hashimoto, Takashi Sato, Minglu Jiang, Yasuaki Inoue
2010	Misc	`conf`	Path clustering for adaptive test. VTS Takumi Uezono, Tomoyuki Takahashi, Michihiro Shintani, Kazumi Hatayama, Kazuya Masu, Hiroyuki Ochi, Takashi Sato
2010	J	`jnl`	Reliability Evaluation Environment for Exploring Design Space of Coarse-Grained Reconfigurable Architectures. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Takashi Imagawa, Masayuki Hiromoto, Hiroyuki Ochi, Takashi Sato
2010	—	`conf`	Robust importance sampling for efficient SRAM yield analysis. ISQED Takanori Date, Shiho Hagiwara, Kazuya Masu, Takashi Sato
2010	C	`conf`	Scan based process parameter estimation through path-delay inequalities. ISCAS Takumi Uezono, Tomoyuki Takahashi, Michihiro Shintani, Kazumi Hatayama, Kazuya Masu, Hiroyuki Ochi, Takashi Sato
2010	A	`conf`	Sequential importance sampling for low-probability and high-dimensional SRAM yield analysis. ICCAD Kentaro Katayama, Shiho Hagiwara, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato
2009	J	`jnl`	2-Port Modeling Technique for Surface-Mount Passive Components Using Partial Inductance Concept. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Koh Yamanaga, Takashi Sato, Kazuya Masu
2009	J	`jnl`	Accurate Array-Based Measurement for Subthreshold-Current of MOS Transistors. IEEE J. Solid State Circuits Takashi Sato, Hiroyuki Ueyama, Noriaki Nakayama, Kazuya Masu
2009	—	`conf`	An Adaptive Test for Parametric Faults Based on Statistical Timing Information. Asian Test Symposium Michihiro Shintani, Takumi Uezono, Tomoyuki Takahashi, Hiroyuki Ueyama, Takashi Sato, Kazumi Hatayama, Takashi Aikyo, Kazuya Masu
2009	J	`jnl`	An Approach for Reducing Leakage Current Variation due to Manufacturing Variability. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Tsuyoshi Sakata, Takaaki Okumura, Atsushi Kurokawa, Hidenari Nakashima, Hiroo Masuda, Takashi Sato, Masanori Hashimoto, Koutaro Hachiya, Katsuhiro Furukawa, Masakazu Tanaka, Hiroshi Takafuji, Toshiki Kanamoto
2009	J	`jnl`	Analytical Estimation of Path-Delay Variation for Multi-Threshold CMOS Circuits. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Shiho Hagiwara, Takashi Sato, Kazuya Masu
2009	J	`jnl`	Improvement in Computational Accuracy of Output Transition Time Variation Considering Threshold Voltage Variations. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Takaaki Okumura, Atsushi Kurokawa, Hiroo Masuda, Toshiki Kanamoto, Masanori Hashimoto, Hiroshi Takafuji, Hidenari Nakashima, Nobuto Ono, Tsuyoshi Sakata, Takashi Sato
2009	J	`jnl`	One-Shot Voltage-Measurement Circuit Utilizing Process Variation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Takumi Uezono, Takashi Sato, Kazuya Masu
2009	J	`jnl`	Physical design challenges to nano-CMOS circuits. IEICE Electron. Express Kazuya Masu, Noboru Ishihara, Noriaki Nakayama, Takashi Sato, Shuhei Amakawa
2008	J	`jnl`	An Evaluation Method of the Number of Monte Carlo STA Trials for Statistical Path Delay Analysis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Masanori Imai, Takashi Sato, Noriaki Nakayama, Kazuya Masu
2008	J	`jnl`	Application of Correlation-Based Regression Analysis for Improvement of Power Distribution Network. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Shiho Hagiwara, Takumi Uezono, Takashi Sato, Kazuya Masu
2008	A	`conf`	Decoupling capacitance allocation for timing with statistical noise model and timing analysis. ICCAD Takashi Enami, Masanori Hashimoto, Takashi Sato
2008	—	`conf`	Determination of optimal polynomial regression function to decompose on-die systematic and random variations. ASP-DAC Takashi Sato, Hiroyuki Ueyama, Noriaki Nakayama, Kazuya Masu
2008	J	`jnl`	Layout-Aware Compact Model of MOSFET Characteristics Variations Induced by STI Stress. IEICE Trans. Electron. Kenta Yamada, Takashi Sato, Shuhei Amakawa, Noriaki Nakayama, Kazuya Masu, Shigetaka Kumashiro
2008	A*	`conf`	Non-parametric statistical static timing analysis: an SSTA framework for arbitrary distribution. DAC Masanori Imai, Takashi Sato, Noriaki Nakayama, Kazuya Masu
2008	J	`jnl`	Timing Analysis Considering Temporal Supply Voltage Fluctuation. IEICE Trans. Inf. Syst. Masanori Hashimoto, Junji Yamaguchi, Takashi Sato, Hidetoshi Onodera
2007	—	`conf`	A MOS Transistor-Array for Accurate Measurement of Subthreshold Leakage Variation. ISQED Takashi Sato, Takumi Uezono, Shiho Hagiwara, Kenichi Okada, Shuhei Amakawa, Noriaki Nakayama, Kazuya Masu
2007	—	`conf`	A Multi-Drop Transmission-Line Interconnect in Si LSI. ASP-DAC Junki Seita, Hiroyuki Ito, Kenichi Okada, Takashi Sato, Kazuya Masu
2007	—	`conf`	Adaptable wire-length distribution with tunable occupation probability. SLIP Shuhei Amakawa, Takumi Uezono, Takashi Sato, Kenichi Okada, Kazuya Masu
2007	—	`conf`	Improvement of power distribution network using correlation-based regression analysis. ACM Great Lakes Symposium on VLSI Shiho Hagiwara, Takumi Uezono, Takashi Sato, Kazuya Masu
2007	J	`jnl`	Proposal of Metrics for SSTA Accuracy Evaluation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Hiroyuki Kobayashi, Nobuto Ono, Takashi Sato, Jiro Iwai, Hidenari Nakashima, Takaaki Okumura, Masanori Hashimoto
2007	J	`jnl`	Validation of a Full-Chip Simulation Model for Supply Noise and Delay Dependence on Average Voltage Drop With On-Chip Delay Measurement. IEEE Trans. Circuits Syst. II Express Briefs Yasuhiro Ogasahara, Takashi Enami, Masanori Hashimoto, Takashi Sato, Takao Onoye
2007	—	`conf`	Weakness Identification for Effective Repair of Power Distribution Network. PATMOS Takashi Sato, Shiho Hagiwara, Takumi Uezono, Kazuya Masu
2006	J	`jnl`	A Method to Derive SSO Design Rule Considering Jitter Constraint. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Koutaro Hachiya, Hiroyuki Kobayashi, Takaaki Okumura, Takashi Sato, Hiroki Oka
2006	—	`conf`	A Time-Slicing Ring Oscillator for Capturing Instantaneous Delay Degradation and Power Supply Voltage Drop. CICC Takashi Sato, Yu Matsumoto, Koji Hirakimoto, Michio Komoda, Junichi Mano
2006	—	`conf`	Measurement results of delay degradation due to power supply noise well correlated with full-chip simulation. CICC Yasuhiro Ogasahara, Takashi Enami, Masanori Hashimoto, Takashi Sato, Takao Onoye
2006	J	`jnl`	On-Chip Thermal Gradient Analysis Considering Interdependence between Leakage Power and Temperature. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Takashi Sato, Junji Ichimiya, Nobuto Ono, Masanori Hashimoto
2006	—	`conf`	Thermal Driven Module Placement Using Sequence-pair. APCCAS Norihide Okada, Chikaaki Kodama, Takashi Sato, Kunihiro Fujiyoshi
2005	J	`jnl`	On-Chip Thermal Gradient Analysis and Temperature Flattening for SoC Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Takashi Sato, Junji Ichimiya, Nobuto Ono, Koutaro Hachiya, Masanori Hashimoto
2005	—	`conf`	On-chip thermal gradient analysis and temperature flattening for SoC design. ASP-DAC Takashi Sato, Junji Ichimiya, Nobuto Ono, Koutaro Hachiya, Masanori Hashimoto
2005	J	`jnl`	Successive Pad Assignment for Minimizing Supply Voltage Drop. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Takashi Sato, Masanori Hashimoto, Hidetoshi Onodera
2005	—	`conf`	Successive pad assignment algorithm to optimize number and location of power supply pad using incremental matrix inversion. ASP-DAC Takashi Sato, Masanori Hashimoto, Hidetoshi Onodera
2005	—	`conf`	Timing analysis considering temporal supply voltage fluctuation. ASP-DAC Masanori Hashimoto, Junji Yamaguchi, Takashi Sato, Hidetoshi Onodera
2004	J	`jnl`	Probabilistic crosstalk delay estimation for ASICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Kan Takeuchi, Kazumasa Yanagisawa, Takashi Sato, Kazuko Sakamoto, Saburo Hojo
2003	—	`conf`	Accurate prediction of the impact of on-chip inductance on interconnect delay using electrical and physical parameter-based RSF. ASP-DAC Takashi Sato, Toshiki Kanamoto, Atsushi Kurokawa, Yoshiyuki Kawakami, Hiroki Oka, Tomoyasu Kitaura, Hiroyuki Kobayashi, Masanori Hashimoto
2003	—	`conf`	Approximate formulae approach for efficient inductance extraction. ASP-DAC Atsushi Kurokawa, Takashi Sato, Hiroo Masuda
2003	J	`jnl`	Approximation Formula Approach for the Efficient Extraction of On-Chip Mutual Inductances. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Atsushi Kurokawa, Takashi Sato, Hiroo Masuda
2003	J	`jnl`	Bidirectional closed-form transformation between on-chip coupling noise waveforms and interconnect delay-change curves. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Takashi Sato, Yu Cao, Kanak Agarwal, Dennis Sylvester, Chenming Hu
2003	—	`conf`	Design and Measurement of an Inductance-Oscillator for Analyzing Inductance Impact on On-Chip Interconnect Delay. ISQED Takashi Sato, Hiroo Masuda
2003	J	`jnl`	Fast On-Chip Inductance Extraction of VLSI Including Angled Interconnects. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Atsushi Kurokawa, Kotaro Hachiya, Takashi Sato, Kazuya Tokumasu, Hiroo Masuda
2002	—	`conf`	Efficient Generation of Delay Change Curves for Noise-Aware Static Timing Analysis. ASP-DAC/VLSI Design Kanak Agarwal, Yu Cao, Takashi Sato, Dennis Sylvester, Chenming Hu
2001	J	`jnl`	Accurate in situ measurement of peak noise and delay change induced by interconnect coupling. IEEE J. Solid State Circuits Takashi Sato, Dennis Sylvester, Yu Cao, Chenming Hu
2000	—	`conf`	New paradigm of predictive MOSFET and interconnect modeling for early circuit simulation. CICC Yu Cao, Takashi Sato, Michael Orshansky, Dennis Sylvester, Chenming Hu
1999	J	`jnl`	A 5-GByte/s data-transfer scheme with bit-to-bit skew control for synchronous DRAM. IEEE J. Solid State Circuits Takashi Sato, Yoji Nishio, Toshio Sugano, Yoshinobu Nakagome
1989	A	`conf`	An efficient algorithm for layout compaction problem with symmetry constraints. ICCAD R. Okuda, Takashi Sato, Hidetoshi Onodera, K. Tamariu