Takashi Ohsawa

19 papers C 1Journal 15Unranked 3
YearRankTypeTitle / Venue / Authors
2024 J jnl
Area-Efficient Binarized Neural Network Inference Accelerator Based on Time-Multiplexed XNOR Multiplier Using Loadless 4T SRAM.
IEICE Trans. Electron.
Yihan Zhu, Takashi Ohsawa
2023 J jnl
A Fully Analog Deep Neural Network Inference Accelerator with Pipeline Registers Based on Master-Slave Switched Capacitors.
IEICE Trans. Electron.
Yaxin Mei, Takashi Ohsawa
2022 J jnl
A Low-Cost Training Method of ReRAM Inference Accelerator Chips for Binarized Neural Networks to Recover Accuracy Degradation due to Statistical Variabilities.
IEICE Trans. Electron.
Zian Chen, Takashi Ohsawa
2021 J jnl
Compact Model of Magnetic Tunnel Junctions for SPICE Simulation Based on Switching Probability.
IEICE Trans. Electron.
Haoyan Liu, Takashi Ohsawa
2020 J jnl
Array Design of High-Density Emerging Memories Making Clamped Bit-Line Sense Amplifier Compatible with Dummy Cell Average Read Scheme.
IEICE Trans. Electron.
Ziyue Zhang, Takashi Ohsawa
2020 J jnl
Co-Design of Binary Processing in Memory ReRAM Array and DNN Model Optimization Algorithm.
IEICE Trans. Electron.
Yue Guan, Takashi Ohsawa
2019 — conf
User- Friendly Compact Model of Magnetic Tunnel Junctions for Circuit Simulation Based on Switching Probability.
VLSI-DAT
Haoyan Liu, Takashi Ohsawa
2018 J jnl
A New Read Scheme for High-Density Emerging Memories.
IEICE Trans. Electron.
Takashi Ohsawa
2013 J jnl
A 1 Mb Nonvolatile Embedded Memory Using 4T2MTJ Cell With 32 b Fine-Grained Power Gating Scheme.
IEEE J. Solid State Circuits
Takashi Ohsawa, Hiroki Koike, Sadahiko Miura, Hiroaki Honjo, Keizo Kinoshita, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh
2012 — conf
1Mb 4T-2MTJ nonvolatile STT-RAM for embedded memories using 32b fine-grained power gating technique with 1.0ns/200ps wake-up/power-off times.
VLSIC
Takashi Ohsawa, Hiroki Koike, Sadahiko Miura, Hiroaki Honjo, Keiichi Tokutome, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh
2012 C conf
High-speed simulator including accurate MTJ models for spintronics integrated circuit design.
ISCAS
Noboru Sakimura, Ryusuke Nebashi, Yukihide Tsuji, Hiroaki Honjo, Tadahiko Sugibayashi, Hiroki Koike, Takashi Ohsawa, Shunsuke Fukami, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh
2012 J jnl
Low Power Nonvolatile Counter Unit with Fine-Grained Power Gating.
IEICE Trans. Electron.
Shuta Togashi, Takashi Ohsawa, Tetsuo Endoh
2011 J jnl
Generation of Accurate Reference Current for Data Sensing in High-Density Memories by Averaging Multiple Pairs of Dummy Cells.
IEEE J. Solid State Circuits
Takashi Ohsawa, Kosuke Hatsuda, Katsuyuki Fujita, Fumiyoshi Matsuoka, Tomoki Higashi
2006 J jnl
Design of a 128-mb SOI DRAM using the floating body cell (FBC).
IEEE J. Solid State Circuits
Takashi Ohsawa, Katsuyuki Fujita, Kosuke Hatsuda, Tomoki Higashi, Tomoaki Shino, Yoshihiro Minami, Hiroomi Nakajima, Mutsuo Morikado, Kazumi Inoh, Takeshi Hamamoto, Shigeyoshi Watanabe, Shuso Fujii, Tohru Furuyama
2005 — conf
A 333MHz random cycle DRAM using the floating body cell.
CICC
Kosuke Hatsuda, Katsuyuki Fujita, Takashi Ohsawa
2002 J jnl
Memory design using a one-transistor gain cell on SOI.
IEEE J. Solid State Circuits
Takashi Ohsawa, Katsuyuki Fujita, Tomoki Higashi, Yoshihisa Iwata, Takeshi Kajiyama, Yoshiaki Asao, Kazumasa Sunouchi
1991 J jnl
A 12 MHz data cycle 4 Mb DRAM with pipeline operation.
IEEE J. Solid State Circuits
Natsuki Kushiyama, Yohji Watanabe, Takashi Ohsawa, Kazuyoshi Muraoka, Yousei Nagahama, Tohru Furuyama
1989 J jnl
A new CR-delay circuit technology for high-density and high-speed DRAMs.
IEEE J. Solid State Circuits
Yohji Watanabe, Takashi Ohsawa, Kiyofumi Sakurai, Tohru Furuyama
1989 J jnl
An experimental 2-bit/cell storage DRAM for macrocell or memory-on-logic application.
IEEE J. Solid State Circuits
Tohru Furuyama, Takashi Ohsawa, Yousei Nagahama, Hiroto Tanaka, Yohji Watanabe, Tohru Kimura, Kazuyoshi Muraoka, Kenji Natori