Takashi Nishida

15 papers C 1Journal 13Unranked 1

Year	Rank	Type	Title / Venue / Authors
2010	J	`jnl`	Electrical Properties of Ba IEICE Trans. Electron. Li Lu, Masahiro Echizen, Takashi Nishida, Kiyoshi Uchiyama, Yukiharu Uraoka
1995	J	`jnl`	A 300-MHz 4-Mb wave-pipeline CMOS SRAM using a multiphase PLL. IEEE J. Solid State Circuits Koichiro Ishibashi, Kunihiro Komiyaji, Hiroshi Toyoshima, Masataka Minami, Nagatoshi Ohki, Hiroshi Ishida, Toshiaki Yamanaka, Takahiro Nagano, Takashi Nishida
1995	J	`jnl`	A 6-ns 4-Mb CMOS SRAM with offset-voltage-insensitive current sense amplifiers. IEEE J. Solid State Circuits Koichiro Ishibashi, Koichi Takasugi, Kunihiro Komiyaji, Hiroshi Toyoshima, Toshiaki Yamanaka, Akira Fukami, Naotaka Hashimoto, Nagatoshi Ohki, Akihiro Shimizu, Takashi Hashimoto, Takahiro Nagano, Takashi Nishida
1995	J	`jnl`	An experimental 220-MHz 1-Gb DRAM with a distributed-column-control architecture. IEEE J. Solid State Circuits Takeshi Sakata, Masashi Horiguchi, Tomonori Sekiguchi, Shigeki Ueda, Hitoshi Tanaka, Eiji Yamasaki, Yoshinobu Nakagome, Masakazu Aoki, Toru Kaga, Makoto Ohkura, Ryo Nagai, Fumio Murai, Toshihiko Tanaka, Shimpei Iijima, Natsuki Yokoyama, Yasushi Gotoh, Ken'ichi Shoji, Teruaki Kisu, Hisaomi Yamashita, Takashi Nishida, Eiji Takeda
1994	—	`conf`	Hearing aid evaluation using variable - speech - rate audiometry. ICSLP Hiroshi Hosoi, Yoshiaki Tsuta, Takashi Nishida, Kiyotaka Murata, Fumihiko Ohta, Tsuyoshi Mekata, Yumiko Kato
1993	J	`jnl`	256-Mb DRAM circuit technologies for file applications. IEEE J. Solid State Circuits Goro Kitsukawa, Masashi Horiguchi, Yoshiki Kawajiri, Takayuki Kawahara, Takesada Akiba, Yasushi Kawase, Toshikazu Tachibana, Takeshi Sakai, Masakazu Aoki, Syoji Shukuri, Kazuhiko Sagara, Ryo Nagai, Yuzuru Ohji, Nono Hasegawa, Natsuki Yokoyama, Teruaki Kisu, Hisaomi Yamashita, Tokuo Kure, Takashi Nishida
1992	J	`jnl`	3.3-V BiCMOS circuit techniques for 250-MHz RISC arithmetic modules. IEEE J. Solid State Circuits Kazuo Yano, Mitsuru Hiraki, Shoji Shukuri, M. Hanawa, Masato Suzuki, S. Morita, A. Kawamata, Nagatoshi Ohki, Takashi Nishida, Koichi Seki
1992	J	`jnl`	A 1.5-V full-swing BiCMOS logic circuit. IEEE J. Solid State Circuits Mitsuru Hiraki, Kazuo Yano, Masataka Minami, Kazushige Sato, Nozomu Matsuzaki, Atsuo Watanabe, Takashi Nishida, Katsuro Sasaki, Koichi Seki
1991	J	`jnl`	A block-oriented RAM with half-sized DRAM cell and quasi-folded data-line architecture. IEEE J. Solid State Circuits Katsutaka Kimura, Takeshi Sakata, Kiyoo Itoh, Toru Kaga, Takashi Nishida, Yoshifumi Kawamoto
1991	J	`jnl`	An experimental 1.5-V 64-Mb DRAM. IEEE J. Solid State Circuits Yoshinobu Nakagome, Hitoshi Tanaka, Kan Takeuchi, Eiji Kume, Yasushi Watanabe, Toru Kaga, Yoshifumi Kawamoto, Fumio Murai, Ryuichi Izawa, Digh Hisamoto, Teruaki Kisu, Takashi Nishida, Eiji Takeda, Kiyoo Itoh
1991	J	`jnl`	Circuit techniques for 1.5-3.6-V battery-operated 64-Mb DRAM. IEEE J. Solid State Circuits Yoshinobu Nakagome, Kiyoo Itoh, Kan Takeuchi, Eiji Kume, Hitoshi Tanaka, Masanori Isoda, Tatsunori Musha, Toru Kaga, Teruaki Kisu, Takashi Nishida, Yoshifumi Kawamoto, Masakazu Aoki
1991	C	`conf`	On-Chip Multiple Superscalar Processors with Secondary Cache Memories. ICCD M. Hanawa, Tadahiko Nishimukai, O. Nishii, Masato Suzuki, Kazuo Yano, Mitsuru Hiraki, Shoji Shukuri, Takashi Nishida
1991	J	`jnl`	Quasi-complementary BiCMOS for sub-3-V digital circuits. IEEE J. Solid State Circuits Kazuo Yano, Mitsuru Hiraki, Shoji Shukuri, Yasuo Onose, Mitsuru Hirao, Nagatoshi Ohki, Takashi Nishida, Koichi Seki, Katsuhiro Shimohigashi
1990	J	`jnl`	A 3.8-ns CMOS 16*16-b multiplier using complementary pass-transistor logic. IEEE J. Solid State Circuits Kazuo Yano, Toshiaki Yamanaka, Takashi Nishida, Masayoshi Saito, Katsuhiro Shimohigashi, Akihiro Shimizu
1989	J	`jnl`	A 9-ns 1-Mbit CMOS SRAM. IEEE J. Solid State Circuits Katsuro Sasaki, Koichiro Ishibashi, Toshiaki Yamanaka, Naotaka Hashimoto, Takashi Nishida, Katsuhiro Shimohigashi, Shoji Hanamura, Shigeru Honjo