Takashi Nakada

46 papers A 1B 1C 8Misc 2Journal 17Unranked 17
YearRankTypeTitle / Venue / Authors
2022 J jnl
A Hybrid Bayesian-Convolutional Neural Network for Adversarial Robustness.
IEICE Trans. Inf. Syst.
Thi Thu Thao Khong, Takashi Nakada, Yasuhiko Nakashima
2021 J jnl
Efficient hardware task migration for heterogeneous FPGA computing using HDL-based checkpointing.
Integr.
Hoang Gia Vu, Takashi Nakada, Yasuhiko Nakashima
2021 J jnl
Flexible Bayesian Inference by Weight Transfer for Robust Deep Neural Networks.
IEICE Trans. Inf. Syst.
Thi Thu Thao Khong, Takashi Nakada, Yasuhiko Nakashima
2020 J jnl
An Energy-Efficient Task Scheduling for Near Real-Time Systems on Heterogeneous Multicore Processors.
IEICE Trans. Inf. Syst.
Takashi Nakada, Hiroyuki Yanagihashi, Kunimaro Imai, Hiroshi Ueki, Takashi Tsuchiya, Masanori Hayashikoshi, Hiroshi Nakamura
2020 — conf
Bayes without Bayesian Learning for Resisting Adversarial Attacks.
CANDAR
Thi Thu Thao Khong, Takashi Nakada, Yasuhiko Nakashima
2020 J jnl
Construction of an Efficient Divided/Distributed Neural Network Model Using Edge Computing.
IEICE Trans. Inf. Syst.
Ryuta Shingai, Yuria Hiraga, Hisakazu Fukuoka, Takamasa Mitani, Takashi Nakada, Yasuhiko Nakashima
2019 — conf
DiaNet: An Efficient Multi-Grained Re-configurable Neural Network in Silicon.
SoCC
Renyuan Zhang, Yan Chen, Takashi Nakada, Yasuhiko Nakashima
2019 — conf
GPGPU Implementation of Variational Bayesian Gaussian Mixture Models.
CANDAR
Hiroki Nishimoto, Takashi Nakada, Yasuhiko Nakashima
2019 J jnl
Programmable Analog Calculation Unit with Two-Stage Architecture: A Solution of Efficient Vector-Computation.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Renyuan Zhang, Takashi Nakada, Yasuhiko Nakashima
2018 J jnl
A Tree-Based Checkpointing Architecture for the Dependability of FPGA Computing.
IEICE Trans. Inf. Syst.
Hoang Gia Vu, Shinya Takamaeda-Yamazaki, Takashi Nakada, Yasuhiko Nakashima
2018 — conf
A programmable analog calculation unit for vector computations.
COOL CHIPS
Noriyuki Uetake, Renyuan Zhang, Takashi Nakada, Yasuhiko Nakashima
2018 J jnl
Design of Programmable Analog Calculation Unit by Implementing Support Vector Regression for Approximate Computing.
IEEE Micro
Renyuan Zhang, Noriyuki Uetake, Takashi Nakada, Yasuhiko Nakashima
2018 — conf
Efficient Multitasking on FPGA Using HDL-Based Checkpointing.
ARC
Hoang Gia Vu, Takashi Nakada, Yasuhiko Nakashima
2017 — conf
A Feasibility Study of Programmable Analog Calculation Unit for Approximate Computing.
CANDAR
Renyuan Zhang, Takashi Nakada, Yasuhiko Nakashima
2017 J jnl
An Energy-Efficient Task Scheduling for Near-Realtime Systems with Execution Time Variation.
IEICE Trans. Inf. Syst.
Takashi Nakada, Tomoki Hatanaka, Hiroshi Ueki, Masanori Hayashikoshi, Toru Shimizu, Hiroshi Nakamura
2017 Misc conf
CPRring: A Structure-Aware Ring-Based Checkpointing Architecture for FPGA Computing.
FCCM
Hoang Gia Vu, Shinya Takamaeda-Yamazaki, Takashi Nakada, Yasuhiko Nakashima
2017 — conf
Compression and Aggregation for Optimizing Information Transmission in Distributed CNN.
CANDAR
Takamasa Mitani, Hisakazu Fukuoka, Yuria Hiraga, Takashi Nakada, Yasuhiko Nakashima
2017 C conf
Energy-aware task scheduling for near real-time periodic tasks on heterogeneous multicore processors.
VLSI-SoC
Takashi Nakada, Hiroyuki Yanagihashi, Hiroshi Nakamura, Kunimaro Imai, Hiroshi Ueki, Takashi Tsuchiya, Masanori Hayashikoshi
2016 — conf
7.2 4Mb STT-MRAM-based cache with memory-access-aware power optimization and write-verify-write / read-modify-write scheme.
ISSCC
Hiroki Noguchi, Kazutaka Ikegami, Satoshi Takaya, Eishi Arima, Keiichi Kushida, Atsushi Kawasumi, Hiroyuki Hara, Keiko Abe, Naoharu Shimomura, Junichi Ito, Shinobu Fujita, Takashi Nakada, Hiroshi Nakamura
2016 J jnl
A Runtime Optimization Selection Framework to Realize Energy Efficient Networks-on-Chip.
IEICE Trans. Inf. Syst.
Yuan He, Masaaki Kondo, Takashi Nakada, Hiroshi Sasaki, Shinobu Miwa, Hiroshi Nakamura
2016 C conf
An adaptive energy-efficient task scheduling under execution time variation based on statistical analysis.
VLSI-SoC
Takashi Nakada, Tomoki Hatanaka, Hiroshi Nakamura, Hiroshi Ueki, Masanori Hayashikoshi, Toru Shimizu
2016 — conf
Normally-off power management for sensor nodes of global navigation satellite system.
ISOCC
Takashi Nakada, Hiroshi Nakamura, Toshifumi Nakamoto, Toru Shimizu
2015 — conf
Energy-Efficient Continuous Task Scheduling for Near Real-Time Periodic Tasks.
DSDIS
Takashi Nakada, Hiroyuki Yanagihashi, Hiroshi Ueki, Takashi Tsuchiya, Masanori Hayashikoshi, Hiroshi Nakamura
2015 C conf
Immediate sleep: Reducing energy impact of peripheral circuits in STT-MRAM caches.
ICCD
Eishi Arima, Hiroki Noguchi, Takashi Nakada, Shinobu Miwa, Susumu Takeda, Shinobu Fujita, Hiroshi Nakamura
2015 C conf
Runtime multi-optimizations for energy efficient on-chip interconnections1.
ICCD
Yuan He, Masaaki Kondo, Takashi Nakada, Hiroshi Sasaki, Shinobu Miwa, Hiroshi Nakamura
2014 J jnl
A Tightly Coupled General Purpose Reconfigurable Accelerator LAPP and Its Power States for HotSpot-Based Energy Reduction.
IEICE Trans. Inf. Syst.
Jun Yao, Yasuhiko Nakashima, Naveen Devisetti, Kazuhiro Yoshimura, Takashi Nakada
2014 — conf
Data-aware power management for periodic real-time systems with non-volatile memory.
NVMSA
Takashi Nakada, Takuya Shigematsu, Toshiya Komoda, Shinobu Miwa, Hiroshi Nakamura, Yohei Sato, Hiroshi Ueki, Masanori Hayashikoshi, Toru Shimizu
2014 J jnl
Design Aid of Multi-core Embedded Systems with Energy Model.
Inf. Media Technol.
Takashi Nakada, Kazuya Okamoto, Toshiya Komoda, Shinobu Miwa, Yohei Sato, Hiroshi Ueki, Masanori Hayashikoshi, Toru Shimizu, Hiroshi Nakamura
2014 — conf
Normally-off computing project: Challenges and opportunities.
ASP-DAC
Hiroshi Nakamura, Takashi Nakada, Shinobu Miwa
2013 A conf
D-MRAM cache: enhancing energy efficiency with 3T-1MTJ DRAM/MRAM hybrid memory.
DATE
Hiroki Noguchi, Kumiko Nomura, Keiko Abe, Shinobu Fujita, Eishi Arima, Kyundong Kim, Takashi Nakada, Shinobu Miwa, Hiroshi Nakamura
2013 C conf
Performance modeling for designing NoC-based multiprocessors.
RSP
Takashi Nakada, Shinobu Miwa, Keisuke Y. Yano, Hiroshi Nakamura
2013 C conf
Power capping of CPU-GPU heterogeneous systems through coordinating DVFS and task mapping.
ICCD
Toshiya Komoda, Shingo Hayashi, Takashi Nakada, Shinobu Miwa, Hiroshi Nakamura
2012 J jnl
RazorProtector: Maintaining Razor DVS Efficiency in Large IR-Drop Zones by an Adaptive Redundant Data-Path.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Yukihiro Sasagawa, Jun Yao, Takashi Nakada, Yasuhiko Nakashima
2011 J jnl
An Instruction Mapping Scheme for FU Array Accelerator.
IEICE Trans. Inf. Syst.
Kazuhiro Yoshimura, Takuya Iwakami, Takashi Nakada, Jun Yao, Hajime Shimada, Yasuhiko Nakashima
2011 — conf
An efficient and reliable 1.5-way processor by fusion of space and time redundancies.
DSN Workshops
Jun Yao, Ryoji Watanabe, Kazuhiro Yoshimura, Takashi Nakada, Hajime Shimada, Yasuhiko Nakashima
2011 — conf
LAPP: A Low Power Array Accelerator with Binary Compatibility.
IPDPS Workshops
Naveen Devisetti, Takuya Iwakami, Kazuhiro Yoshimura, Takashi Nakada, Jun Yao, Yasuhiko Nakashima
2010 C conf
A Minimal Roll-Back Based Recovery Scheme for Fault Toleration in Pipeline Processors.
PRDC
Jun Yao, Ryoji Watanabe, Takashi Nakada, Hajime Shimada, Yasuhiko Nakashima, Kazutoshi Kobayashi
2010 — conf
An Instruction Decomposition Method for Reconfigurable Decoders.
IWIA
Kazuhiro Yoshimura, Takashi Nakada, Yasuhiko Nakashima
2008 C conf
A Functional Unit with Small Variety of Highly Reliable Cells.
PRDC
Kouki Suzuki, Takashi Nakada, Masaki Nakanishi, Shigeru Yamashita, Yasuhiko Nakashima
2008 J jnl
A Simulation-Based Analysis for Worst Case Delay of Single and Multiple Interruptions.
Inf. Media Technol.
Hiroshi Nakashima, Masahiro Konishi, Takashi Nakada
2008 J jnl
A Simulation-Based Analysis for Worst Case Delay of Single and Multiple Interruptions.
IPSJ Trans. Syst. LSI Des. Methodol.
Hiroshi Nakashima, Masahiro Konishi, Takashi Nakada
2007 — conf
An Accurate and Efficient Time-Division Parallelization of Cycle Accurate Architectural Simulators.
Annual Simulation Symposium
Masahiro Yano, Toru Takasaki, Takashi Nakada, Hiroshi Nakashima
2007 J jnl
An Efficient Analysis of Worst Case Flush Timings for Branch Predictors.
Inf. Media Technol.
Masahiro Konishi, Takashi Nakada, Tomoaki Tsumura, Hiroshi Nakashima, Hiroaki Takada
2006 Misc conf
An accurate and efficient simulation-based analysis for worst case interruption delay.
CASES
Hiroshi Nakashima, Masahiro Konishi, Takashi Nakada
2006 — conf
Design and Implementation of aWorkload Specific Simulator.
Annual Simulation Symposium
Takashi Nakada, Tomoaki Tsumura, Hiroshi Nakashima
2004 B conf
Design and Implementation of a High Speed Microprocessor Simulator BurstScalar.
MASCOTS
Takashi Nakada, Hiroshi Nakashima