Takashi Morie - RankMe

134 papers B 16C 13Journal 59Unranked 43

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Harnessing Nonidealities in Analog In-Memory Computing Circuits: A Physical Modeling Approach for Neuromorphic Systems. Adv. Intell. Syst. Yusuke Sakemi, Yuji Okamoto, Takashi Morie, Sou Nobukawa, Takeo Hosomi, Kazuyuki Aihara
2025	C	`conf`	An in-memory computing circuit with carry-over thermometer coding for a hippocampus-inspired model. ISCAS Yuka Shishido, Tomoro Marcus Jones, Hakaru Tamukoh, Takashi Morie
2025	J	`jnl`	Hibikino-Musashi@Home 2025 Team Description Paper. CoRR Ryohei Kobayashi, Kosei Isomoto, Kosei Yamao, Soma Fumoto, Koshun Arimura, Naoki Yamaguchi, Akinobu Mizutani, Tomoya Shiba, Kouki Kimizuka, Yuta Ohno, Ryo Terashima, Hiromasa Yamaguchi, Tomoaki Fujino, Ryoga Maruno, Wataru Yoshimura, Kazuhito Mine, Tang Phu Thien Nhan, Yuga Yano, Yuichiro Tanaka, Takeshi Nishida, Takashi Morie, Hakaru Tamukoh
2025	J	`jnl`	Techniques for Enhancing Memory Capacity of Reservoir Computing. CoRR Atsuki Yokota, Ichiro Kawashima, Yohei Saito, Hakaru Tamukoh, Osamu Nomura, Takashi Morie
2024	B	`conf`	A Hippocampus-Inspired Environment-Specific Knowledge Acquisition System Utilizing Common Knowledge with Contextual Information. IJCNN Akinobu Mizutani, Yuichiro Tanaka, Hakaru Tamukoh, Osamu Nomura, Katsumi Tateno, Takashi Morie
2024	B	`conf`	CMOS digital-analog mixed signal VLSI implementation of a hippocampus-inspired model. IJCNN Yuka Shishido, Osamu Nomura, Katsumi Tateno, Hakaru Tamukoh, Takashi Morie
2024	C	`conf`	Enhancing Memory Capacity of Reservoir Computing with Delayed Input and Efficient Hardware Implementation with Shift Registers. ISCAS Soshi Hirayae, Kanta Yoshioka, Atsuki Yokota, Ichiro Kawashima, Yuichiro Tanaka, Yuichi Katori, Osamu Nomura, Takashi Morie, Hakaru Tamukoh
2024	J	`jnl`	Hibikino-Musashi@Home 2024 Team Description Paper. CoRR Kosei Isomoto, Akinobu Mizutani, Fumiya Matsuzaki, Hikaru Sato, Ikuya Matsumoto, Kosei Yamao, Takuya Kawabata, Tomoya Shiba, Yuga Yano, Atsuki Yokota, Daiju Kanaoka, Hiromasa Yamaguchi, Kazuya Murai, Kim Minje, Lu Shen, Mayo Suzuka, Moeno Anraku, Naoki Yamaguchi, Satsuki Fujimatsu, Shoshi Tokuno, Tadataka Mizo, Tomoaki Fujino, Yuuki Nakadera, Yuka Shishido, Yusuke Nakaoka, Yuichiro Tanaka, Takashi Morie, Hakaru Tamukoh
2024	C	`conf`	Hibikino-Musashi@Home RoboCup@Home DSPL Champion 2024. RoboCup Akinobu Mizutani, Kosei Isomoto, Kosei Yamao, Ryohei Kobayashi, Soma Fumoto, Koshun Arimura, Naoki Yamaguchi, Tomoya Shiba, Kouki Kimizuka, Yuta Ohno, Ryo Terashima, Hiromasa Yamaguchi, Tomoaki Fujino, Ryoga Maruno, Wataru Yoshimura, Kazuhito Mine, Tang Phu Thien Nhan, Yuga Yano, Yuichiro Tanaka, Takeshi Nishida, Takashi Morie, Hakaru Tamukoh
2024	B	`conf`	Robust Binary Encoding for Ternary Neural Networks Toward Deployment on Emerging Memory. IJCNN Ninnart Fuengfusin, Hakaru Tamukoh, Osamu Nomura, Takashi Morie
2024	J	`jnl`	Training Physical Neural Networks for Analog In-Memory Computing. CoRR Yusuke Sakemi, Yuji Okamoto, Takashi Morie, Sou Nobukawa, Takeo Hosomi, Kazuyuki Aihara
2023	J	`jnl`	A Supervised Learning Algorithm for Multilayer Spiking Neural Networks Based on Temporal Coding Toward Energy-Efficient VLSI Processor Design. IEEE Trans. Neural Networks Learn. Syst. Yusuke Sakemi, Kai Morino, Takashi Morie, Kazuyuki Aihara
2023	B	`conf`	Efficient Repetition Coding for Deep Learning Towards Implementation Using Emerging Non-Volatile Memory with Write-Errors. IJCNN Ninnart Fuengfusin, Hakaru Tamukoh, Yuichiro Tanaka, Osamu Nomura, Takashi Morie
2023	B	`conf`	FPGA Implementation of a Chaotic Boltzmann Machine Annealer. IJCNN Kanta Yoshioka, Yuichi Katori, Yuichiro Tanaka, Osamu Nomura, Takashi Morie, Hakaru Tamukoh
2023	J	`jnl`	Hibikino-Musashi@Home 2023 Team Description Paper. CoRR Tomoya Shiba, Akinobu Mizutani, Yuga Yano, Tomohiro Ono, Shoshi Tokuno, Daiju Kanaoka, Yukiya Fukuda, Hayato Amano, Mayu Koresawa, Yoshifumi Sakai, Ryogo Takemoto, Katsunori Tamai, Kazuo Nakahara, Hiroyuki Hayashi, Satsuki Fujimatsu, Yusuke Mizoguchi, Moeno Anraku, Mayo Suzuka, Lu Shen, Kohei Maeda, Fumiya Matsuzaki, Ikuya Matsumoto, Kazuya Murai, Kosei Isomoto, Kim Minje, Yuichiro Tanaka, Takashi Morie, Hakaru Tamukoh
2023	J	`jnl`	Learning Reservoir Dynamics with Temporal Self-Modulation. CoRR Yusuke Sakemi, Sou Nobukawa, Toshitaka Matsuki, Takashi Morie, Kazuyuki Aihara
2022	J	`jnl`	A Neural Network Model of the Entorhinal Cortex and Hippocampus for Event-Order Memory Processing. IEEE Access Hiroki Nakagawa, Katsumi Tateno, Kensuke Takada, Takashi Morie
2022	C	`conf`	A Spiking Neural Network with Resistively Coupled Synapses Using Time-to-First-Spike Coding Towards Efficient Charge-Domain Computing. ISCAS Yusuke Sakemi, Kai Morino, Takashi Morie, Takeo Hosomi, Kazuyuki Aihara
2022	C	`conf`	A memory-based entorhinal-hippocampal model and its FPGA implementation by on-chip RAMs. ISCAS Ichiro Kawashima, Katsumi Tateno, Takashi Morie, Hakaru Tamukoh
2022	J	`jnl`	Hibikino-Musashi@Home 2018 Team Description Paper. CoRR Yutaro Ishida, Sansei Hori, Yuichiro Tanaka, Yuma Yoshimoto, Kouhei Hashimoto, Gouki Iwamoto, Yoshiya Aratani, Kenya Yamashita, Shinya Ishimoto, Kyosuke Hitaka, Fumiaki Yamaguchi, Ryuhei Miyoshi, Kentaro Honda, Yushi Abe, Yoshitaka Kato, Takashi Morie, Hakaru Tamukoh
2022	J	`jnl`	Hibikino-Musashi@Home 2022 Team Description Paper. CoRR Tomoya Shiba, Tomohiro Ono, Shoshi Tokuno, Issei Uchino, Masaya Okamoto, Daiju Kanaoka, Kazutaka Takahashi, Kenta Tsukamoto, Yoshiaki Tsutsumi, Yugo Nakamura, Yukiya Fukuda, Yusuke Hoji, Hayato Amano, Yuma Kubota, Mayu Koresawa, Yoshifumi Sakai, Ryogo Takemoto, Katsunori Tamai, Kazuo Nakahara, Hiroyuki Hayashi, Satsuki Fujimatsu, Akinobu Mizutani, Yusuke Mizoguchi, Yuhei Yoshimitsu, Mayo Suzuka, Ikuya Matsumoto, Yuga Yano, Yuichiro Tanaka, Takashi Morie, Hakaru Tamukoh
2022	J	`jnl`	Robustness of Spiking Neural Networks Based on Time-to-First-Spike Encoding Against Adversarial Attacks. IEEE Trans. Circuits Syst. II Express Briefs Osamu Nomura, Yusuke Sakemi, Takeo Hosomi, Takashi Morie
2021	J	`jnl`	An Energy-Efficient Time-Domain Analog CMOS BinaryConnect Neural Network Processor Based on a Pulse-Width Modulation Approach. IEEE Access Masatoshi Yamaguchi, Goki Iwamoto, Yuta Nishimura, Hakaru Tamukoh, Takashi Morie
2021	—	`conf`	An area-efficient multiply-accumulation architecture and implementations for time-domain neural processing. FPT Ichiro Kawashima, Yuichi Katori, Takashi Morie, Hakaru Tamukoh
2021	J	`jnl`	An efficient hardware-oriented dropout algorithm. Neurocomputing Yoeng Jye Yeoh, Takashi Morie, Hakaru Tamukoh
2021	—	`conf`	Brain-inspired neural network navigation system with hippocampus, prefrontal cortex, and amygdala functions. ISPACS Akinobu Mizutani, Yuichiro Tanaka, Hakaru Tamukoh, Yuichi Katori, Katsumi Tateno, Takashi Morie
2021	J	`jnl`	Effects of VLSI Circuit Constraints on Temporal-Coding Multilayer Spiking Neural Networks. CoRR Yusuke Sakemi, Takashi Morie, Takeo Hosomi, Kazuyuki Aihara
2020	J	`jnl`	A Supervised Learning Algorithm for Multilayer Spiking Neural Networks Based on Temporal Coding Toward Energy-Efficient VLSI Processor Design. CoRR Yusuke Sakemi, Kai Morino, Takashi Morie, Kazuyuki Aihara
2020	J	`jnl`	A hardware intelligent processing accelerator for domestic service robots. Adv. Robotics Yutaro Ishida, Takashi Morie, Hakaru Tamukoh
2020	J	`jnl`	An Amygdala-Inspired Classical Conditioning Model Implemented on an FPGA for Home Service Robots. IEEE Access Yuichiro Tanaka, Takashi Morie, Hakaru Tamukoh
2020	J	`jnl`	FPGA Implementation of Hardware-Oriented Chaotic Boltzmann Machines. IEEE Access Ichiro Kawashima, Takashi Morie, Hakaru Tamukoh
2020	J	`jnl`	Hibikino-Musashi@Home 2019 Team Description Paper. CoRR Yuichiro Tanaka, Yutaro Ishida, Yushi Abe, Tomohiro Ono, Kohei Kabashima, Takuma Sakata, Masashi Fukuyado, Fuyuki Muto, Takumi Yoshii, Kazuki Kanamaru, Daichi Kamimura, Kentaro Nakamura, Yuta Nishimura, Takashi Morie, Hakaru Tamukoh
2020	J	`jnl`	Hibikino-Musashi@Home 2020 Team Description Paper. CoRR Tomohiro Ono, Yuichiro Tanaka, Yutaro Ishida, Yushi Abe, Kazuki Kanamaru, Daichi Kamimura, Kentaro Nakamura, Yuta Nishimura, Shoshi Tokuno, Yuya Mii, Morio Yamauchi, Yuichiro Uemura, Takunori Hashimoto, Yugo Nakamura, Issei Uchino, Daiju Kanaoka, Takeru Hanyu, Kenta Tsukamoto, Takashi Morie, Hakaru Tamukoh
2019	B	`conf`	A Chaotic Boltzmann Machine Working as a Reservoir and Its Analog VLSI Implementation. IJCNN Masatoshi Yamaguchi, Yuichi Katori, Daichi Kamimura, Hakaru Tamukoh, Takashi Morie
2019	J	`jnl`	An Efficient Hardware-Oriented Dropout Algorithm. CoRR Yoeng Jye Yeoh, Takashi Morie, Hakaru Tamukoh
2019	J	`jnl`	An Energy-efficient Time-domain Analog VLSI Neural Network Processor Based on a Pulse-width Modulation Approach. CoRR Masatoshi Yamaguchi, Goki Iwamoto, Hakaru Tamukoh, Takashi Morie
2019	C	`conf`	Live Demonstration: A VLSI Implementation of Time-Domain Analog Weighted-Sum Calculation Model for Intelligent Processing on Robots. ISCAS Masatoshi Yamaguchi, Gouki Iwamoto, Yushi Abe, Yuichiro Tanaka, Yutaro Ishida, Hakaru Tamukoh, Takashi Morie
2019	B	`conf`	Reservoir Computing Based on Dynamics of Pseudo-Billiard System in Hypercube. IJCNN Yuichi Katori, Hakaru Tamukoh, Takashi Morie
2018	C	`conf`	A Hardware Accelerated Robot Middleware Package for Intelligent Processing on Robots. ISCAS Yutaro Ishida, Takashi Morie, Hakaru Tamukoh
2018	J	`jnl`	A Time-domain Analog Weighted-sum Calculation Model for Extremely Low Power VLSI Implementation of Multi-layer Neural Networks. CoRR Quan Wang, Hakaru Tamukoh, Takashi Morie
2018	C	`conf`	Live Demonstration: A Hardware Accelerated Robot Middleware Package for Intelligent Processing on Robots. ISCAS Yutaro Ishida, Takashi Morie, Hakaru Tamukoh
2017	B	`conf`	A CMOS chaotic Boltzmann machine circuit and three-neuron network operation. IJCNN Masatoshi Yamaguchi, Hakaru Tamukoh, Hideyuki Suzuki, Takashi Morie
2017	—	`conf`	A Hardware-Oriented Dropout Algorithm for Efficient FPGA Implementation. ICONIP (6) Yoeng Jye Yeoh, Takashi Morie, Hakaru Tamukoh
2017	J	`jnl`	Hibikino-Musashi@Home 2017 Team Description Paper. CoRR Sansei Hori, Yutaro Ishida, Yuta Kiyama, Yuichiro Tanaka, Yuki Kuroda, Masataka Hisano, Yuto Imamura, Tomotaka Himaki, Yuma Yoshimoto, Yoshiya Aratani, Kouhei Hashimoto, Gouki Iwamoto, Hiroto Fujita, Takashi Morie, Hakaru Tamukoh
2017	J	`jnl`	Synchronization of Pulse-Coupled Phase Oscillators over Multi-FPGA Communication Links. J. Robotics Netw. Artif. Life Dinda Pramanta, Takashi Morie, Hakaru Tamukoh
2016	—	`conf`	A CMOS Unit Circuit Using Subthreshold Operation of MOSFETs for Chaotic Boltzmann Machines. ICONIP (1) Masatoshi Yamaguchi, Takashi Kato, Quan Wang, Hideyuki Suzuki, Hakaru Tamukoh, Takashi Morie
2016	—	`conf`	Depth-Based Visual Servoing Using Low-Accurate Arm. SCIS&ISIS Ludovic Hofer, Michio Tanaka, Hakaru Tamukoh, Amir Ali Forough Nassiraei, Takashi Morie
2016	J	`jnl`	Depth-Based Visual Servoing Using Low-Accurate Arm. CoRR Ludovic Hofer, Michio Tanaka, Hakaru Tamukoh, Amir Ali Forough Nassiraei, Takashi Morie
2016	—	`conf`	FPGA Implementation of Autoencoders Having Shared Synapse Architecture. ICONIP (1) Akihiro Suzuki, Takashi Morie, Hakaru Tamukoh
2016	—	`conf`	Restricted Boltzmann Machines Without Random Number Generators for Efficient Digital Hardware Implementation. ICANN (1) Sansei Hori, Takashi Morie, Hakaru Tamukoh
2016	—	`conf`	Time-Domain Weighted-Sum Calculation for Ultimately Low Power VLSI Neural Networks. ICONIP (1) Quan Wang, Hakaru Tamukoh, Takashi Morie
2015	J	`jnl`	A 4.2 mW 50 MS/s 13 bit CMOS SAR ADC With SNR and SFDR Enhancement Techniques. IEEE J. Solid State Circuits Takuji Miki, Takashi Morie, Kazuo Matsukawa, Yoji Bando, Takeshi Okumoto, Koji Obata, Shiro Sakiyama, Shiro Dosho
2015	J	`jnl`	A PWM-Mode Pixel-Parallel Image-Processing Circuit Performing Directional State-Propagation and Its Application to Subjective Contour Generation. Circuits Syst. Signal Process. Youngjae Kim, Takashi Morie
2015	—	`conf`	A pixel-parallel state-propagation algorithm with self-update of propagation direction for subjective contour generation. ISPACS Hiroki Sou, Takashi Morie
2015	J	`jnl`	Human Detection and Face Recognition Using 3D Structure of Head and Face Surfaces Detected by RGB-D Sensor. J. Robotics Mechatronics Michio Tanaka, Hiroki Matsubara, Takashi Morie
2015	J	`jnl`	Parameterized digital hardware design of pulse-coupled phase oscillator networks. Neurocomputing Yasuhiro Suedomi, Hakaru Tamukoh, Kenji Matsuzaka, Michio Tanaka, Takashi Morie
2014	J	`jnl`	A motion detection model inspired by hippocampal function and its applications to obstacle detection. Neurocomputing Haichao Liang, Takashi Morie
2014	—	`conf`	A silicon nanodisk array structure realizing synaptic response of spiking neuron models with noise. ASP-DAC Takashi Morie, Haichao Liang, Yilai Sun, Takashi Tohara, Makoto Igarashi, Seiji Samukawa
2014	—	`conf`	An ultra-low-power 2-step wake-up receiver for IEEE 802.15.4g wireless sensor networks. VLSIC Takayuki Abe, Takashi Morie, Kazutoshi Satou, Daisuke Nomasaki, Shigeki Nakamura, Yoichiro Horiuchi, Koji Imamura
2014	J	`jnl`	Comparing Effectiveness of Feature Detectors in Obstacles Detection from a Video. J. Robotics Netw. Artif. Life Shaohua Qian, Joo Kooi Tan, Hyoungseop Kim, Seiji Ishikawa, Takashi Morie, Takashi Shinomiya
2014	—	`conf`	Morphological Associative Memory Employing a Split Store Method. ICONIP (3) Hakaru Tamukoh, Kensuke Koga, Hideaki Harada, Takashi Morie
2013	—	`conf`	A 71dB-SNDR 50MS/s 4.2mW CMOS SAR ADC by SNR enhancement techniques utilizing noise. ISSCC Takashi Morie, Takuji Miki, Kazuo Matsukawa, Yoji Bando, Takeshi Okumoto, Koji Obata, Shiro Sakiyama, Shiro Dosho
2013	—	`conf`	Parameterized Digital Hardware Design of Pulse-Coupled Phase Oscillator Model toward Spike-Based Computing. ICONIP (3) Yasuhiro Suedomi, Hakaru Tamukoh, Michio Tanaka, Kenji Matsuzaka, Takashi Morie
2012	J	`jnl`	A Hierarchical Extension of the HOG Model Implemented in the Convolution-net for Human Detection. Inf. Media Technol. Yasuto Arakaki, Hayaru Shouno, Kazuyuki Takahashi, Takashi Morie
2012	J	`jnl`	A Motion Detection Model Inspired by the Neuronal Propagation in the Hippocampus. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Haichao Liang, Takashi Morie
2012	J	`jnl`	An 11-b 300-MS/s Double-Sampling Pipelined ADC With On-Chip Digital Calibration for Memory Effects. IEEE J. Solid State Circuits Takuji Miki, Takashi Morie, Toshiaki Ozeki, Shiro Dosho
2012	—	`conf`	Obstacles Extraction Using a Moving Camera. ACCV Workshops (2) Shaohua Qian, Joo Kooi Tan, Hyoungseop Kim, Seiji Ishikawa, Takashi Morie
2012	—	`conf`	Obstacles Extraction from a Video Taken by a Moving Camera. ICCVE Shaohua Qian, Joo Kooi Tan, Hyoungseop Kim, Seiji Ishikawa, Takashi Morie
2011	—	`conf`	A CMOS nonlinear-map circuit array for threshold-coupled chaotic maps using pulse-modulation approach. ECCTD Takashi Morie, Daisuke Atuti, Kazuki Ifuku, Yoshihiko Horio, Kazuyuki Aihara
2011	—	`conf`	A Motion Detection Model Inspired by Hippocampal Function and Its FPGA Implementation. ICONIP (3) Haichao Liang, Takashi Morie
2011	—	`conf`	A VLSI Spiking Neural Network with Symmetric STDP and Associative Memory Operation. ICONIP (3) Frank L. Maldonado Huayaney, Hideki Tanaka, Takayuki Matsuo, Takashi Morie, Kazuyuki Aihara
2011	C	`conf`	Analog CMOS circuit implementation of a system of pulse-coupled oscillators for spike-based computation. ISCAS Kenji Matsuzaka, Kazuki Nakada, Takashi Morie
2010	C	`conf`	A 2-dimensional Si nanodisk array structure for spiking neuron models. ISCAS Takashi Morie, Yilai Sun, Haichao Liang, Makoto Igarashi, Chi-Hsien Huang, Seiji Samukawa
2010	—	`ch.`	An FPGA-Based Collision Warning System Using Moving-Object Detection Inspired by Neuronal Propagation in the Hippocampus. Brain-Inspired Information Technology Haichao Liang, Youhei Suzuki, Takashi Morie, Kazuki Nakada, Tsutomu Miki, Hatsuo Hayashi
2010	J	`jnl`	Automatic detection of pedestrians from stereo camera images. Artif. Life Robotics Joo Kooi Tan, Kazuki Inumaru, Seiji Ishikawa, Takashi Morie
2010	—	`conf`	Coarse Image Edge Detection using Self-adjusting Resistive-fuse Networks. PRIS Haichao Liang, Takashi Morie
2010	J	`jnl`	Coarse Image Region Segmentation in Spatio-Temporal Domain Using a Region-based Coupled MRF Model with Phase Dynamics. Aust. J. Intell. Inf. Process. Syst. Kazuki Nakada, Kenji Matsuzaka, Takashi Morie
2010	J	`jnl`	On detecting a human and its body direction from a video. Artif. Life Robotics Yuuki Nakashima, Joo Kooi Tan, Seiji Ishikawa, Takashi Morie
2010	—	`conf`	Parametric Control in a Region-Based Coupled MRF Model with Phase Dynamics for Coarse Image Region Segmentation. CSE Haichao Liang, Kazuki Nakada, Kenji Matsuzaka, Takashi Morie, Masato Okada
2010	—	`ch.`	Real-Time Human-Machine Interaction System Based on Face Authentication and Arm Posture Recognition. Brain-Inspired Information Technology Ishtiaq Rasool Khan, Takashi Morie, Hiroyuki Miyamoto, Yasutaka Kuriya, Masaki Shimizu
2010	—	`ch.`	Shadow Elimination Mimicking the Human Visual System. Brain-Inspired Information Technology Takuji Kamada, Akitoshi Hanazawa, Takashi Morie
2009	J	`jnl`	A 125-1250 MHz Process-Independent Adaptive Bandwidth Spread Spectrum Clock Generator With Digital Controlled Self-Calibration. IEEE J. Solid State Circuits Tsuyoshi Ebuchi, Yoshihide Komatsu, Tatsuo Okamoto, Yukio Arima, Yuji Yamada, Kazuaki Sogawa, Kouji Okamoto, Takashi Morie, Takashi Hirata, Shiro Dosho, Takefumi Yoshikawa
2009	J	`jnl`	A CMOS Spiking Neural Network Circuit with Symmetric/Asymmetric STDP Function. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Hideki Tanaka, Takashi Morie, Kazuyuki Aihara
2009	J	`jnl`	A Current-Sampling-Mode CMOS Arbitrary Chaos Generator Circuit Using Pulse Modulation Approach. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Daisuke Atuti, Takashi Morie, Kazuyuki Aihara
2009	—	`conf`	A subjective-contour generation LSI system with expandable pixel-parallel architecture for vision systems. ISSCC Takashi Morie, Youngjae Kim
2009	B	`conf`	Coarse image region segmentation using region-and boundary-based coupled MRF models and their PWM VLSI implementation. IJCNN Yusuke Kawashima, Daisuke Atuti, Kazuki Nakada, Masato Okada, Takashi Morie
2009	—	`conf`	Design methods for pipeline & delta-sigma A-to-D converters with convex optimization. ASP-DAC Kazuo Matsukawa, Takashi Morie, Yusuke Tokunaga, Shiro Sakiyama, Yosuke Mitani, Masao Takayama, Takuji Miki, Akinori Matsumoto, Koji Obata, Shiro Dosho
2009	J	`jnl`	Single-Electron Devices and Circuits Utilizing Stochastic Operation for Intelligent Information Processing. Int. J. Nanotechnol. Mol. Comput. Takashi Morie
2009	B	`conf`	Video Monitoring of Slope Failure Using Spatiotemporal Gabor Filtering. SMC Ken Okamoto, Toshio Watanabe, Akitoshi Hanazawa, Takashi Morie, Hiroshi Ban, Yuji Maeda
2008	J	`jnl`	A Design Method and Developments of a Low-Power and High-Resolution Multiphase Generation System. IEEE J. Solid State Circuits Akinori Matsumoto, Shiro Sakiyama, Yusuke Tokunaga, Takashi Morie, Shiro Dosho
2008	C	`conf`	CMOS pulse-modulation circuit implementation of phase-locked loop neural networks. ISCAS Daisuke Atuti, Kazuki Nakada, Takashi Morie
2008	B	`conf`	Face and arm-posture recognition for secure human-machine interaction. SMC Ishtiaq Rasool Khan, Hiroyuki Miyamoto, Takashi Morie
2007	C	`conf`	An FPGA-based CollisionWarning System Using Hybrid Approach. HIS Haichao Liang, Takashi Morie, Youhei Suzuki, Kazuki Nakada, Tsutomu Miki, Hatsuo Hayashi
2007	J	`jnl`	An Ultra-Wide Range Digitally Adaptive Control Phase Locked Loop with New 3-Phase Switched Capacitor Loop Filter. IEICE Trans. Electron. Shiro Dosho, Naoshi Yanagisawa, Kazuaki Sogawa, Yuji Yamada, Takashi Morie
2007	—	`conf`	CMOS circuit implementation of a coupled phase oscillator system using pulse modulation approach. ECCTD Daisuke Atuti, Naoto Kato, Kazuki Nakada, Takashi Morie
2007	—	`conf`	Projection-Field-Type VLSI Convolutional Neural Networks Using Merged/Mixed Analog-Digital Approach. ICONIP (1) Osamu Nomura, Takashi Morie
2006	J	`jnl`	A -90 dBc@ 10 kHz Phase Noise Fractional-N Frequency Synthesizer with Accurate Loop Bandwidth Control Circuit. IEICE Trans. Electron. Shiro Dosho, Takashi Morie, Koji Okamoto, Yuji Yamada, Kazuaki Sogawa
2006	—	`conf`	A 10.8mA Single Chip Transceiver for 430MHz Narrowband Systems in 0.15µm CMOS. ISSCC George Hayashi, Akihiro Sawada, Takashi Morie, Kazuhiro Matsuyama, Ryangsu Kim, Seichiro Yoshida, Akinori Matsumoto, Katsumasa Hijikata, Kazuo Matsukawa, Yoshihiro Tamura, Jun Ogawa, Toshio Takita
2006	—	`conf`	A Current-Sampling-Mode Arbitrary Chaos Generator Circuit Using Pulse Modulation Approach Driven by Quantized Nonlinear Waveforms. APCCAS Daisuke Atuti, Takashi Morie, Kazuyuki Aihara
2006	—	`conf`	A PLL for a DVD-16 Write System with 63 Output Phases and 32ps Resolution. ISSCC Shiro Dosho, Shiro Sakiyama, Noriaki Takeda, Yusuke Tokunaga, Takashi Morie
2006	J	`jnl`	A VLSI Spiking Feedback Neural Network with Negative Thresholding and Its Application to Associative Memory. IEICE Trans. Electron. Kan'ya Sasaki, Takashi Morie, Atsushi Iwata
2006	J	`jnl`	An Image-Filtering LSI Processor Architecture for Face/Object Recognition Using a Sorted Projection-Field Model Based on a Merged/Mixed Analog-Digital Architecture. IEICE Trans. Electron. Osamu Nomura, Takashi Morie, Keisuke Korekado, Teppei Nakano, Masakazu Matsugu, Atsushi Iwata
2006	J	`jnl`	FPGA Implementation of Resistive-Fuse Networks for Coarse Image-Region Segmentation. Intell. Autom. Soft Comput. Teppei Nakano, Takashi Morie, Hideaki Ishizu, Hiroshi Ando, Atsushi Iwata
2005	J	`jnl`	A Cellular-Automaton-Type Region Extraction Algorithm and its FPGA Implementation. J. Robotics Mechatronics Teppei Nakano, Takashi Morie, Makoto Nagata, Atsushi Iwata
2005	—	`conf`	A Convolutional Neural Network VLSI Architecture Using Sorting Model for Reducing Multiply-and-Accumulation Operations. ICNC (3) Osamu Nomura, Takashi Morie, Masakazu Matsugu, Atsushi Iwata
2005	B	`conf`	A digital LSI architecture of elastic graph matching and its FPGA implementation. IJCNN Teppei Nakano, Takashi Morie
2005	—	`conf`	A pixel-parallel anisotropic diffusion algorithm for subjective contour generation. ISCAS (5) Youngjae Kim, Takashi Morie
2004	—	`conf`	A 0.13um CMOS ultra-compact DVD SoC employing a full digital equalizing PRML read channel. CICC Kouichi Nagano, Koji Okamoto, Akira Yamamoto, Hiroki Mouri, Akira Kawabe, Hirokuni Fujiyama, Takashi Morie, Hiroyuki Nakahira, Masahiro Kuramochi, Minoru Ochiai, Kazutoshi Aida, Youichi Ogura, Toshihiko Takahashi, Toru Kakiage, Masao Takiguchi, Takashi Yamamoto, Hiroshi Kamiyama, Yutaka Katabe
2004	B	`conf`	A Convolutional Neural Network VLSI Architecture Using Thresholding and Weight Decomposition. KES Osamu Nomura, Takashi Morie, Keisuke Korekado, Masakazu Matsugu, Atsushi Iwata
2004	J	`jnl`	A VLSI convolutional neural network for image recognition using merged/mixed analog-digital architecture. J. Intell. Fuzzy Syst. Keisuke Korekado, Takashi Morie, Osamu Nomura, Hiroshi Ando, Teppei Nakano, Masakazu Matsugu, Atsushi Iwata
2004	J	`jnl`	Gabor-Type Filtering using Transient States of Cellular Neural Networks. Intell. Autom. Soft Comput. Takashi Morie, Jun Umezawa, Atsushi Iwata
2003	B	`conf`	A Convolutional Neural Network VLSI for Image Recognition Using Merged/Mixed Analog-Digital Architecture. KES Keisuke Korekado, Takashi Morie, Osamu Nomura, Hiroshi Ando, Teppei Nakano, Masakazu Matsugu, Atsushi Iwata
2003	J	`jnl`	A fully integrated 0.13-μm CMOS mixed-signal SoC for DVD player applications. IEEE J. Solid State Circuits Koji Okamoto, Takashi Morie, Akira Yamamoto, Kouichi Nagano, Koji Sushihara, Hiroyuki Nakahira, Ryusuke Horibe, Kazutoshi Aida, Toshihiko Takahashi, Minoru Ochiai, Akinobu Soneda, Toru Kakiage, Tamaki Iwasaki, Hiroshi Taniuchi, Tadashi Shibata, Takahiro Ochi, Masao Takiguchi, Takashi Yamamoto, Tadayoshi Seike, Akira Matsuzawa
2002	J	`jnl`	A 200-MHz seventh-order equiripple continuous-time filter by design of nonlinearity suppression in 0.25-μm CMOS process. IEEE J. Solid State Circuits Shiro Dosho, Takashi Morie, Hirokuni Fujiyama
2002	—	`conf`	A cellular-automaton-type image extraction algorithm and its implementation using an FPGA. APCCAS (2) Teppei Nakano, Takashi Morie, Makoto Nagata, Atsushi Iwata
2002	J	`jnl`	Image Segmentation/Extraction Using Nonlinear Cellular Networks and Their VLSI Implementation Using Pulse-Modulation Techniques. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Hiroshi Ando, Takashi Morie, Makoto Miyake, Makoto Nagata, Atsushi Iwata
2002	—	`conf`	Modeling substrate noise generation in CMOS digital integrated circuits. CICC Makoto Nagata, Takashi Morie, Atsushi Iwata
2002	—	`conf`	Substrate Noise Analysis with Compact Digital Noise Injection and Substrate Models. ASP-DAC/VLSI Design Makoto Nagata, Yoshitaka Murasaka, Youichi Nishimori, Takashi Morie, Atsushi Iwata
2001	J	`jnl`	A PWM analog memory programming circuit for floating-gate MOSFETs with 75-μs programming time and 11-bit updating resolution. IEEE J. Solid State Circuits Shigeo Kinoshita, Takashi Morie, Makoto Nagata, Atsushi Iwata
2001	—	`conf`	An Efficient Clustering Algorithm Using Stochastic Association Model and Its Implementation Using Nanostructures. NIPS Takashi Morie, Tomohiro Matsuura, Makoto Nagata, Atsushi Iwata
2001	—	`conf`	Chip-Level Substrate Noise Analysis with Network Reduction by Fundamental Matrix Computation. ISQED Yoshitaka Murasaka, Makoto Nagata, Takafumi Ohmoto, Takashi Morie, Atsushi Iwata
2001	J	`jnl`	Physical design guides for substrate noise reduction in CMOS digital circuits. IEEE J. Solid State Circuits Makoto Nagata, Jin Nagai, Katsumasa Hijikata, Takashi Morie, Atsushi Iwata
2001	—	`conf`	Test circuits for substrate noise evaluation in CMOS digital ICs. ASP-DAC Makoto Nagata, Takafumi Ohmoto, Jin Nagai, Takashi Morie, Atsushi Iwata
2000	—	`conf`	A smart imager for the vision processing front-END. ASP-DAC Noriaki Takeda, Mitsuru Homma, Makoto Nagata, Takashi Morie, Atsushi Iwata
2000	—	`conf`	An arbitrary chaos generator core curcuit using PWM/PPM signals. ASP-DAC Kenichi Murakoshi, Takashi Morie, Makoto Nagata, Atsushi Iwata
2000	J	`jnl`	Measurements and analyses of substrate noise waveform inmixed-signal IC environment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Makoto Nagata, Jin Nagai, Takashi Morie, Atsushi Iwata
2000	C	`conf`	Pulse modulation circuit architecture and its application to functional image sensors. ISCAS Atsushi Iwata, Makoto Nagata, Noriaki Takeda, Mitsuru Homma, Takashi Morie
2000	—	`conf`	Quantitative characterization of substrate noise for physical design guides in digital circuits. CICC Makoto Nagata, Jin Nagai, Takashi Morie, Atsushi Iwata
1999	—	`conf`	A Feature Associative Processor for Image Recognition Based on A-D merged Architecture. VLSI Atsushi Iwata, Makoto Nagata, Hiroyuki Nakamoto, Noriaki Takeda, Mitsuru Homma, Hiroto Higashi, Takashi Morie
1999	—	`conf`	Measurements and analyses of substrate noise waveform in mixed signal IC environment. CICC Makoto Nagata, Yoji Kashima, Daisuke Tamura, Takashi Morie, Atsushi Iwata
1998	B	`conf`	Nonlinear Function Generators and Chaotic Signal Generators Based on Pulse-Phase Modulation. ICONIP Souta Sakabayashi, Takashi Morie, Makoto Nagata, Atsushi Iwata
1998	B	`conf`	Oscillator Networks for Image Segmentation and Their Circuits Using Pulse Modulation Method. ICONIP Hiroshi Ando, Takashi Morie, Makoto Nagata, Atsushi Iwata
1995	—	`conf`	Self-learning neural network LSI with high-resolution non-volatile analog memory. ICNN Takashi Morie, Osamu Fujita, Kuniharu Uchimura
1994	J	`jnl`	An all-analog expandable neural network LSI with on-chip backpropagation learning. IEEE J. Solid State Circuits Takashi Morie, Yoshihito Amemiya