Takashi Miyamori

21 papers A 3C 1Misc 1Journal 5Unranked 11
YearRankTypeTitle / Venue / Authors
2015 — conf
18.2 A 1.9TOPS and 564GOPS/W heterogeneous multicore SoC with color-based object classification accelerator for image-recognition applications.
ISSCC
Jun Tanabe, Toru Sano, Yutaka Yamada, Tomoki Watanabe, Mayu Okumura, Manabu Nishiyama, Tadakazu Nomura, Kazushige Oma, Nobuhiro Sato, Moriyasu Banno, Hiroo Hayashi, Takashi Miyamori
2014 — conf
An evaluation of an energy efficient many-core SoC with parallelized face detection.
ASP-DAC
Hiroyuki Usui, Jun Tanabe, Toru Sano, Hui Xu, Takashi Miyamori
2014 J jnl
Architecture and Evaluation of Low Power Many-Core SoC with Two 32-Core Clusters.
IEICE Trans. Electron.
Takashi Miyamori, Hui Xu, Hiroyuki Usui, Soichiro Hosoda, Toru Sano, Kazumasa Yamamoto, Takeshi Kodaka, Nobuhiro Nonogaki, Nau Ozaki, Jun Tanabe
2013 A conf
A near-future prediction method for low power consumption on a many-core processor.
DATE
Takeshi Kodaka, Akira Takeda, Shunsuke Sasaki, Akira Yokosawa, Toshiki Kizu, Takahiro Tokuyoshi, Hui Xu, Toru Sano, Hiroyuki Usui, Jun Tanabe, Takashi Miyamori, Nobu Matsumoto
2013 A conf
Development of low power many-core SoC for multimedia applications.
DATE
Takashi Miyamori, Hui Xu, Takeshi Kodaka, Hiroyuki Usui, Toru Sano, Jun Tanabe
2012 — conf
A 464GOPS 620GOPS/W heterogeneous multi-core SoC for image-recognition applications.
ISSCC
Yasuki Tanabe, Masato Sumiyoshi, Manabu Nishiyama, Itaru Yamazaki, Shinsuke Fujii, Katsuyuki Kimura, Takuma Aoyama, Moriyasu Banno, Hiroo Hayashi, Takashi Miyamori
2012 — conf
A low power many-core SoC with two 32-core clusters connected by tree based NoC for multimedia applications.
VLSIC
Hui Xu, Jun Tanabe, Hiroyuki Usui, Soichiro Hosoda, Toru Sano, Kazumasa Yamamoto, Takeshi Kodaka, Nobuhiro Nonogaki, Nau Ozaki, Takashi Miyamori
2011 J jnl
A 40 nm 222 mW H.264 Full-HD Decoding, 25 Power Domains, 14-Core Application Processor With x512b Stacked DRAM.
IEEE J. Solid State Circuits
Yu Kikuchi, Makoto Takahashi, Tomohisa Maeda, Masatoshi Fukuda, Yasuhiro Koshio, Hiroyuki Hara, Hideho Arakida, Hideaki Yamamoto, Yousuke Hagiwara, Tetsuya Fujita, Manabu Watanabe, Hirokazu Ezawa, Takayoshi Shimazawa, Yasuo Ohara, Takashi Miyamori, Mototsugu Hamada, Masafumi Takahashi, Yukihito Oowaki
2010 — conf
A 222mW H.264 Full-HD decoding application processor with x512b stacked DRAM in 40nm.
ISSCC
Yu Kikuchi, Makoto Takahashi, Tomohisa Maeda, Hiroyuki Hara, Hideho Arakida, Hideaki Yamamoto, Yousuke Hagiwara, Tetsuya Fujita, Manabu Watanabe, Takayoshi Shimazawa, Yasuo Ohara, Takashi Miyamori, Mototsugu Hamada, Yukihito Oowaki
2010 — conf
Signal and power integrity for SoCs.
ISSCC
Don Draper, Fabio Campi, Ram Krishnamurthy, Takashi Miyamori, Shannon Morton, Willy Sansen, Vladimir Stojanovic, John T. Stonick
2009 J jnl
A VLIW Vector Media Coprocessor With Cascaded SIMD ALUs.
IEEE Trans. Very Large Scale Integr. Syst.
Takahisa Wada, Shunichi Ishiwata, Katsuyuki Kimura, Keiri Nakanishi, Masato Sumiyoshi, Takashi Miyamori, Masaki Nakagawa
2008 — conf
A 9.7mW AAC-Decoding, 620mW H.264 720p 60fps Decoding, 8-Core Media Processor with Embedded Forward-Body-Biasing and Power-Gating Circuit in 65nm CMOS Technology.
ISSCC
Shuou Nomura, Fumihiko Tachibana, Tetsuya Fujita, Chen Kong Teh, Hiroyuki Usui, Fumiyuki Yamane, Yukimasa Miyamoto, Chaiyasit Kumtornkittikul, Hiroyuki Hara, Takahiro Yamashita, Jun Tanabe, Masaru Uchiyama, Yoshiro Tsuboi, Takashi Miyamori, Takeshi Kitahara, Hironori Sato, Y. Homma, Shuuji Matsumoto, Keiko Seki, Y. Watanabe, Mototsugu Hamada, Makoto Takahashi
2005 J jnl
Development of Image Recognition Processor Based on Configurable Processor.
J. Robotics Mechatronics
Takashi Miyamori, Jun Tanabe, Yasuhiro Taniguchi, Kenji Furukawa, Tatsuo Kozakaya, Hiroaki Nakai, Yukimasa Miyamoto, Ken-ichi Maeda, Masataka Matsui
2003 J jnl
A single-chip MPEG-2 codec based on customizable media embedded processor.
IEEE J. Solid State Circuits
Shunichi Ishiwata, Tomoo Yamakage, Yoshiro Tsuboi, Takayoshi Shimazawa, Tomoko Kitazawa, Shuji Michinaka, Kunihiko Yahagi, Hideki Takeda, Akihiro Oue, Tomoya Kodama, Nobu Matsumoto, Takayuki Kamei, Mitsuo Saito, Takashi Miyamori, Goichi Ootomo, Masataka Matsui
2003 — conf
Visconti: multi-VLIW image recognition processor based on configurable processor [obstacle detection applications].
CICC
Jun Tanahe, Yasuhiro Taniguchi, Takashi Miyamori, Yukimasa Miyamoto, Hideki Takeda, Masaya Tarui, Hiromitsu Nakayama, Nohuyulu Takeda, Kenichi Maeda, Masataka Matsui
2002 — conf
A single-chip MPEG-2 codec based on customizable media microprocessor.
CICC
Shunichi Ishiwata, Tomoo Yamakage, Yoshiro Tsuboi, Takayoshi Shimazawa, Tomoko Kitazawa, Shuji Michinaka, Kunihiko Yahagi, Hideki Takeda, Akihiro Oue, Tomoya Kodama, Nobu Matsumoto, Takayuki Kamei, Takashi Miyamori, Goichi Ootomo, Masataka Matsui
2002 C conf
Design Methodology and System for a Configurable Media Embedded Processor Extensible to VLIW Architecture.
ICCD
Atsushi Mizuno, Kazuyoshi Kohno, Ryuichiro Ohyama, Takahiro Tokuyoshi, Hironori Uetani, Hans Eichel, Takashi Miyamori, Nobu Matsumoto, Masataka Matsui
1998 Misc conf
A Quantitative Analysis of Reconfigurable Coprocessors for Multimedia Applications.
FCCM
Takashi Miyamori, Kunle Olukotun
1998 A conf
REMARC: Reconfigurable Multimedia Array Coprocessor (Abstract).
FPGA
Takashi Miyamori, Kunle Olukotun
1989 — conf
The effectiveness of TRONCHIP instructions in the TX1 system.
COMPCON
Hidechika Kishigami, Takashi Miyamori, Misao Miyata
1988 — conf
Design Considerations for 32-bit Microprocessor TX3.
COMPCON
Kosei Okamoto, Misao Miyata, Hidechika Kishigami, Takashi Miyamori, Tai Sato