Takashi Ipposhi

14 papers Misc 1Journal 10Unranked 3
YearRankTypeTitle / Venue / Authors
2009 J jnl
A Look-ahead Active Body-biasing scheme for SOI-SRAM with dynamic
IEICE Electron. Express
Kayoko Seto, Masaaki Iijima, Tetsuya Hirose, Masahiro Numa, Akira Tada, Takashi Ipposhi
2008 J jnl
Delayed-ABC SOI for crosstalk noise repair.
IEICE Electron. Express
Akira Tada, Hiromi Notani, Genichi Tanaka, Toshiaki Iwamatsu, Takashi Ipposhi, Masayuki Terai, Masaaki Iijima, Masahiro Numa
2008 J jnl
Low Power SRAM with Boost Driver Generating Pulsed Word Line Voltage for Sub-1V Operation.
J. Comput.
Masaaki Iijima, Kayoko Seto, Masahiro Numa, Akira Tada, Takashi Ipposhi
2007 — conf
A 0.05�?0.05mm2 RFID Chip with Easily Scaled-Down ID-Memory.
ISSCC
Mitsuo Usami, Hisao Tanabe, Akira Sato, Isao Sakama, Yukio Maki, Toshiaki Iwamatsu, Takashi Ipposhi, Yasuo Inoue
2007 J jnl
A Capacitorless Twin-Transistor Random Access Memory (TTRAM) on SOI.
IEICE Trans. Electron.
Fukashi Morishita, Hideyuki Noda, Isamu Hayashi, Takayuki Gyohten, Mako Okamoto, Takashi Ipposhi, Shigeto Maegawa, Katsumi Dosaka, Kazutami Arimoto
2007 J jnl
A Configurable Enhanced TTRAM Macro for System-Level Power Management Unified Memory.
IEEE J. Solid State Circuits
Fukashi Morishita, Isamu Hayashi, Takayuki Gyohten, Hideyuki Noda, Takashi Ipposhi, Hiroki Shimano, Katsumi Dosaka, Kazutami Arimoto
2007 J jnl
A High-Density Scalable Twin Transistor RAM (TTRAM) With Verify Control for SOI Platform Memory IPs.
IEEE J. Solid State Circuits
Kazutami Arimoto, Fukashi Morishita, Isamu Hayashi, Katsumi Dosaka, Hiroki Shimano, Takashi Ipposhi
2007 J jnl
Boosted Voltage Scheme with Active Body-Biasing Control on PD-SOI for Ultra Low Voltage Operation.
IEICE Trans. Electron.
Masaaki Iijima, Masayuki Kitamura, Masahiro Numa, Akira Tada, Takashi Ipposhi, Shigeto Maegawa
2007 J jnl
Charge recycling in MTCMOS circuits with block dividing.
IEICE Electron. Express
Akira Tada, Hiromi Notani, Genichi Tanaka, Takashi Ipposhi, Masaaki Iijima, Masahiro Numa
2007 J jnl
Look-Ahead Dynamic Threshold Voltage Control Scheme for Improving Write Margin of SOI-7T-SRAM.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Masaaki Iijima, Kayoko Seto, Masahiro Numa, Akira Tada, Takashi Ipposhi
2007 Misc conf
Ultra Low Voltage Operation with Bootstrap Scheme for Single Power Supply SOI-SRAM.
VLSI Design
Masaaki Iijima, Masayuki Kitamura, Masahiro Numa, Akira Tada, Takashi Ipposhi
2006 — conf
A Scalable ET2RAM (SETRAM) with Verify Control for SoC Platform Memory IP on SOI.
CICC
Kazutami Arimoto, Fukashi Morishita, Isamu Hayashi, Tetsushi Tanizaki, Takashi Ipposhi, Katsumi Dosaka
2006 J jnl
Dynamic threshold voltage control for dual supply voltage scheme on PD-SOI.
IEICE Electron. Express
Masaaki Iijima, Kenji Hamada, Masayuki Kitamura, Masahiro Numa, Akira Tada, Takashi Ipposhi
2005 — conf
A capacitorless twin-transistor random access memory (TTRAM) on SOI.
CICC
Fukashi Morishita, Hideyuki Noda, Takayuki Gyohten, Mako Okamoto, Takashi Ipposhi, Shigeto Maegawa, Katsumi Dosaka, Kazutami Arimoto