Takashi Hotta

11 papers C 3Journal 7Unranked 1
YearRankTypeTitle / Venue / Authors
1998 — conf
A Triple Redundant Controller which Adopts the Time-Sharing Fault Recovery Method and its Application to a Power Converter Controller.
IEEE Real Time Technology and Applications Symposium
Kotaro Shimamura, Yuichiro Morita, Yoshitaka Takahashi, Takashi Hotta, Shigeta Ueda, Mikiya Nohara, Mitsuyasu Kido, Seji Tanaka, Kazuhiro Imaie, Koji Sakamoto, Tatsuhito Nakajima
1998 J jnl
Instruction fetch and dispatch scheme with flag-in-cache/in-IBR.
Syst. Comput. Jpn.
Shoji Yoshida, Shigeya Tanaka, Kotaro Matsuo, Takashi Hotta, Hideo Sawamoto, Teruhisa Shimizu
1996 J jnl
2.5 V CMOS circuit techniques for a 200 MHz superscalar RISC processor.
IEEE J. Solid State Circuits
Fumio Murabayashi, Tatsumi Yamauchi, Hiromichi Yamada, Takahiro Nishiyama, Kotaro Shimamura, Shigeya Tanaka, Takashi Hotta, Teruhisa Shimizu, Hideo Sawamoto
1995 C conf
A 13.3ns double-precision floating-point ALU and multiplier.
ICCD
Hiromichi Yamada, Takashi Hotta, Takahiro Nishiyama, Fumio Murabayashi, Tatsumi Yamauchi, Hideo Sawamoto
1995 C conf
A superscalar RISC processor with pseudo vector processing feature.
ICCD
Kotaro Shimamura, Shigeya Tanaka, Tetsuya Shimomura, Takashi Hotta, Eiki Kamada, Hideo Sawamoto, Teruhisa Shimizu, Kisaburo Nakazawa
1994 J jnl
3.3-V BiCMOS circuit techniques for a 120-MHz RISC microprocessor.
IEEE J. Solid State Circuits
Fumio Murabayashi, Takashi Hotta, Shigeya Tanaka, Tatsumi Yamauchi, Hiromichi Yamada, Tetsuo Nakano, Yutaka Kobayashi, Tadaaki Bandoh
1994 J jnl
A 120-MHz BiCMOS superscalar RISC processor.
IEEE J. Solid State Circuits
Shigeya Tanaka, Takashi Hotta, Fumio Murabayashi, Hiromichi Yamada, Shoji Yoshida, Kotaro Shimamura, Koyo Katsura, Tadaaki Bandoh, Koichi Ikeda, Kenji Matsubara, Kouji Saitou, Tetsuo Nakano, Teruhisa Shimizu, Ryuichi Satomura
1991 J jnl
PLL-based BiCMOS on-chip clock generator for very high-speed microprocessor.
IEEE J. Solid State Circuits
Kozaburo Kurita, Takashi Hotta, Tetsuo Nakano, Nobuaki Kitamura
1990 J jnl
A 70-MHz 32-b microprocessor with 1.0- mu m BiCMOS macrocell library.
IEEE J. Solid State Circuits
Takashi Hotta, Tadaaki Bandoh, Atsuo Hotta, Tetsuo Nakano, Shoji Iwamoto, Shigemi Adachi
1989 C conf
A high performance BiCMOS 32-bit microprocessor.
ICCD
Yasuhiro Nakatsuka, Takashi Hotta, Shigeya Tanaka, Tadaaki Bandoh, Ryuichi Satomura, Syuichi Nakagami, Tetsuo Nakano, Atsuo Hotta, Takashi Moriyama, Shigemi Adachi, Shoji Iwamoto
1988 J jnl
1.3- mu m CMOS/bipolar standard cell library for VLSI computers.
IEEE J. Solid State Circuits
Takashi Hotta, Kouzaburou Kurita, Hideo Maejima, Masahiro Iwamura, Shigeya Tanaka, Tadaaki Bandoh, Tatsumi Yamauchi, Atsuo Hotta