Takashi Hirayama

23 papers Misc 1Journal 13Unranked 9
YearRankTypeTitle / Venue / Authors
2025 J jnl
Efficient enumeration of transversal edge-partitions.
Discret. Appl. Math.
Koki Shinraku, Katsuhisa Yamanaka, Takashi Hirayama
2025 J jnl
Mystery Tower is Computationally Hard.
J. Inf. Process.
Kyohei Sangodo, Katsuhisa Yamanaka, Takashi Hirayama
2024 — conf
An Improved Lower Bound on the Gate Count of Toffoli-Based Reversible Logic Circuits.
ISMVL
Takashi Hirayama, Ryo Endo, Katsuhisa Yamanaka
2024 J jnl
New Bounds for Quick Computation of the Lower Bound on the Gate Count of Toffoli-Based Reversible Logic Circuits.
IEICE Trans. Inf. Syst.
Takashi Hirayama, Rin Suzuki, Katsuhisa Yamanaka, Yasuaki Nishitani
2023 J jnl
Enumerating Empty and Surrounding Polygons.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Shunta Terui, Katsuhisa Yamanaka, Takashi Hirayama, Takashi Horiyama, Kazuhiro Kurita, Takeaki Uno
2023 — conf
Quick Computation of the Lower Bound on the Gate Count of Toffoli-Based Reversible Logic Circuits.
ISMVL
Takashi Hirayama, Rin Suzuki, Katsuhisa Yamanaka, Yasuaki Nishitani
2022 J jnl
A Polynomial Delay Algorithm for Enumerating 2-Edge-Connected Induced Subgraphs.
IEICE Trans. Inf. Syst.
Taishu Ito, Yusuke Sano, Katsuhisa Yamanaka, Takashi Hirayama
2020 Misc conf
A Polynomial Delay Algorithm for Enumerating 2-Edge-Connected Induced Subgraphs.
FAW
Yusuke Sano, Katsuhisa Yamanaka, Takashi Hirayama
2019 J jnl
Exact Exponential Algorithm for Distance-3 Independent Set Problem.
IEICE Trans. Inf. Syst.
Katsuhisa Yamanaka, Shogo Kawaragi, Takashi Hirayama
2018 J jnl
Function Design for Minimum Multiple-Control Toffoli Circuits of Reversible Adder/Subtractor Blocks and Arithmetic Logic Units.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Md Belayet Ali, Takashi Hirayama, Katsuhisa Yamanaka, Yasuaki Nishitani
2016 — conf
New Two-Qubit Gate Library with Entanglement.
ISMVL
Md Belayet Ali, Takashi Hirayama, Katsuhisa Yamanaka, Yasuaki Nishitani
2014 J jnl
A Lower Bound on the Gate Count of Toffoli-Based Reversible Logic Circuits.
IEICE Trans. Inf. Syst.
Takashi Hirayama, Hayato Sugawara, Katsuhisa Yamanaka, Yasuaki Nishitani
2011 — conf
A Testable Realization for Decimal Multipliers.
ISMVL
Takashi Hirayama, Yasuaki Nishitani, Seiji Kitamura
2009 J jnl
Exact Minimization of and-EXOR Expressions of Practical Benchmark Functions.
J. Circuits Syst. Comput.
Takashi Hirayama, Yasuaki Nishitani
2009 — conf
Let's make a tennis game!: introduction to game programming.
SIGGRAPH ASIA Courses
Takashi Hirayama
2006 — conf
Efficient Search Methods for Obtaining Exact Minimum AND-EXOR Expressions.
DELTA
Takashi Hirayama, Yasuaki Nishitani
2006 — conf
Simplification of Exclusive-or Sum-of-Products Expressions Through Function Transformation.
APCCAS
Takashi Hirayama, Masatoshi Takahashi, Yasuaki Nishitani
2004 J jnl
New Three-Level Boolean Expression Based on EXOR Gates.
IEICE Trans. Inf. Syst.
Ryoji Ishikawa, Takashi Hirayama, Goro Koda, Kensuke Shimizu
2002 J jnl
A Faster Algorithm of Minimizing AND-EXOR Expressions.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Takashi Hirayama, Yasuaki Nishitani, Toru Sato
2002 — conf
A faster algorithm of minimizing AND-EXOR expressions.
APCCAS (2)
Takashi Hirayama, Yasuaki Nishitani, Toru Sato
2002 — conf
Pseudocube-based expressions to enhance testability.
APCCAS (2)
Ryoji Ishikawa, Tomonori Igarashi, Takashi Hirayama, Kensuke Shimizu
1999 J jnl
Exor Decomposition with Common Variables and its Application to Multiple-Output Networks.
J. Circuits Syst. Comput.
Ryoji Ishikawa, Goro Koda, Kensuke Shimizu, Takashi Hirayama
1996 J jnl
A simplification algorithm of and-exor expressions guaranteeing minimality for some class of logic functions.
Syst. Comput. Jpn.
Takashi Hirayama, Yasuaki Nishitani