Takao Toi

13 papers A 1Journal 5Unranked 7
YearRankTypeTitle / Venue / Authors
2024 — conf
20.3 A 23.9TOPS/W @ 0.8V, 130TOPS AI Accelerator with 16× Performance-Accelerable Pruning in 14nm Heterogeneous Embedded MPU for Real-Time Robot Applications.
ISSCC
Koichi Nose, Taro Fujii, Katsumi Togawa, Shunsuke Okumura, Kentaro Mikami, Daichi Hayashi, Teruhito Tanaka, Takao Toi
2021 — conf
A CMOS Image Sensor and an AI Accelerator for Realizing Edge-Computing-Based Surveillance Camera Systems.
VLSI Circuits
Fukashi Morishita, Norihito Kato, Satoshi Okubo, Takao Toi, Mitsuru Hiraki, Sugako Otani, Hideaki Abe, Yuji Shinohara, Hiroyuki Kondo
2018 — conf
New Generation Dynamically Reconfigurable Processor Technology for Accelerating Embedded AI Applications.
VLSI Circuits
Taro Fujii, Takao Toi, Teruhito Tanaka, Katsumi Togawa, Toshiro Kitaoka, Kengo Nishino, Noritsugu Nakamura, Hiroki Nakahara, Masato Motomura
2013 — conf
Optimizing time and space multiplexed computation in a dynamically reconfigurable processor.
FPT
Takao Toi, Noritsugu Nakamura, Taro Fujii, Toshiro Kitaoka, Katsumi Togawa, Koichiro Furuta, Toru Awashima
2011 J jnl
Iterative Synthesis Methods Estimating Programmable-Wire Congestion in a Dynamically Reconfigurable Processor.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Takao Toi, Takumi Okamoto, Toru Awashima, Kazutoshi Wakabayashi, Hideharu Amano
2010 J jnl
High-level Synthesis Challenges for Mapping a Complete Program on a Dynamically Reconfigurable Processor.
Inf. Media Technol.
Takao Toi, Noritsugu Nakamura, Yoshinosuke Kato, Toru Awashima, Kazutoshi Wakabayashi
2010 J jnl
High-level Synthesis Challenges for Mapping a Complete Program on a Dynamically Reconfigurable Processor.
IPSJ Trans. Syst. LSI Des. Methodol.
Takao Toi, Noritsugu Nakamura, Yoshinosuke Kato, Toru Awashima, Kazutoshi Wakabayashi
2010 — conf
Wire congestion aware synthesis for a dynamically reconfigurable processor.
FPT
Takao Toi, Takumi Okamoto, Toru Awashima, Kazutoshi Wakabayashi, Hideharu Amano
2006 — conf
An adaptive Viterbi decoder on the dynamically reconfigurable processor.
FPT
Shohei Abe, Yohei Hasegawa, Takao Toi, Takeshi Inuo, Hideharu Amano
2006 A conf
High-level synthesis challenges and solutions for a dynamically reconfigurable processor.
ICCAD
Takao Toi, Noritsugu Nakamura, Yoshinosuke Kato, Toru Awashima, Kazutoshi Wakabayashi, Li Jing
2004 — conf
Stream applications on the dynamically reconfigurable processor.
FPT
Masayasu Suzuki, Yohei Hasegawa, Yutaka Yamada, Naoto Kaneko, Katsuaki Deguchi, Hideharu Amano, Kenichiro Anjo, Masato Motomura, Kazutoshi Wakabayashi, Takao Toi, Toru Awashima
2000 J jnl
Color signal processing technique for single-chip CCD cameras that employ CPUs with SIMD instruction sets.
IEEE Trans. Consumer Electron.
Takao Toi
1999 J jnl
A subband coding technique for image compression in single CCD cameras with Bayer color filter arrays.
IEEE Trans. Consumer Electron.
Takao Toi, M. Ohita