Takao Marukame

13 papers C 8Journal 3Unranked 2

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	Co-Optimization of Models and Hardware for Neural Network Inference in Variable-Parallelism Processor. CANDARW Yu Inoue, Atsushi Hori, Takao Marukame, Tetsuya Asai, Alexandre Schmid, Kota Ando
2020	C	`conf`	Dynamic Firing on Static Analog/Digital Neuron Circuits with Resistive Synapses for Time-Series Neural Network. ISCAS Takao Marukame, Junichi Sugino, Toshimitsu Kitamura, Kazuo Ishikawa, Koji Takahashi, Yutaka Tamura, Kumiko Nomura, Koichi Mizushima, Yoshifumi Nishi
2019	C	`conf`	Live Demonstration: Low-Power Static Neural Network Circuits for Long-Term Change Detection. ISCAS Takao Marukame, Toshimitsu Kitamura, Junichi Sugino, Kazuo Ishikawa, Koji Takahashi, Yutaka Tamura, Yoshifumi Nishi
2019	C	`conf`	Nonlinear Operation of Static-Binary Neuron Circuits and Dynamic Memristive Devices for STDP Learning. ISCAS Takao Marukame, Junichi Sugino, Toshimitsu Kitamura, Kazuo Ishikawa, Koji Takahashi, Yutaka Tamura, Radu Berdan, Kumiko Nomura, Yoshifumi Nishi
2018	C	`conf`	Live Demonstration: A prototype of Analog/Digital-mixed Neural Networks for reconfigurable learning. ISCAS Takao Marukame, Yutaka Tamura, Koji Takahashi, Toshimitsu Kitamura, Takashi Takebayashi, Yoshifumi Nishi
2018	C	`conf`	Proposal, analysis and demonstration of Analog/Digital-mixed Neural Networks based on memristive device arrays. ISCAS Takao Marukame, Kumiko Nomura, Mari Matusmoto, Satoshi Takaya, Yoshifumi Nishi
2017	J	`jnl`	Error Tolerance Analysis of Deep Learning Hardware Using a Restricted Boltzmann Machine Toward Low-Power Memory Implementation. IEEE Trans. Circuits Syst. II Express Briefs Takao Marukame, Kodai Ueyoshi, Tetsuya Asai, Masato Motomura, Alexandre Schmid, Masamichi Suzuki, Yusuke Higashi, Yuichiro Mitani
2017	C	`conf`	Live demonstration: Feature extraction system using restricted Boltzmann machines on FPGA. ISCAS Kodai Ueyoshi, Takao Marukame, Tetsuya Asai, Masato Motomura, Alexandre Schmid
2017	J	`jnl`	Physically unclonable function using initial waveform of ring oscillators on 65 nm CMOS technology. CoRR Tetsufumi Tanamoto, Satoshi Takaya, Nobuaki Sakamoto, Hirotsugu Kasho, Shinichi Yasuda, Takao Marukame, Shinobu Fujita, Yuichiro Mitani
2016	C	`conf`	Bit-flipping LDPC under noise conditions and its application to physically unclonable functions. ISCAS Takao Marukame, Alexandre Schmid
2016	C	`conf`	Memory-error tolerance of scalable and highly parallel architecture for restricted Boltzmann machines in Deep Belief Network. ISCAS Kodai Ueyoshi, Takao Marukame, Tetsuya Asai, Masato Motomura, Alexandre Schmid
2011	J	`jnl`	Scalability of spin FPGA: A Reconfigurable Architecture based on spin MOSFET CoRR Tetsufumi Tanamoto, Hideyuki Sugiyama, Tomoaki Inokuchi, Takao Marukame, Mizue Ishikawa, Kazutaka Ikegami, Yoshiaki Saito
2007	—	`conf`	Four-State Magnetic Random Access Memory and Ternary Content Addressable Memory Using CoFe-Based Magnetic Tunnel Junctions. ISMVL Tetsuya Uemura, Takao Marukame, Ken-ichi Matsuda, Masafumi Yamamoto