Takahiro Watanabe

93 papers A 2B 7C 5Journal 44Unranked 35

Year	Rank	Type	Title / Venue / Authors
2021	J	`jnl`	Real-Time Cost Minimization of Fog Computing in Mobile-Base-Station Networked Disaster Areas. IEEE Open J. Comput. Soc. Michael Conrad Meyer, Yu Wang, Takahiro Watanabe
2021	J	`jnl`	Self-restructuring of Mesh-Connected Processor Arrays with Spares Assigned on Rotated Orthogonal Side. Trans. Comput. Sci. Itsuo Takanami, Masaru Fukushi, Takahiro Watanabe
2020	J	`jnl`	A Fast Online Task Placement Algorithm for Three-Dimensional Dynamic Partial Reconfigurable Devices. IEEE Access Tingyu Zhou, Tieyuan Pan, Michael Conrad Meyer, Yiping Dong, Takahiro Watanabe
2020	—	`conf`	An Interval-based Mapping Algorithm for Multi-shape Tasks on Dynamic Partial Reconfigurable FPGAs. IPDPS Workshops Tingyu Zhou, Tieyuan Pan, Michael Conrad Meyer, Yiping Dong, Takahiro Watanabe
2020	J	`jnl`	Multi-Shape Task Placement Algorithm Based on Low Fragmentation Resource Management on 2D Heterogeneous Dynamic Partial Reconfigurable Devices. IEEE Access Tingyu Zhou, Tieyuan Pan, Michael Conrad Meyer, Yiping Dong, Takahiro Watanabe
2020	J	`jnl`	Selection System of Robot Type for Cell Assembly Production (Production Efficiency Comparison of Single and Double Arm Robot). J. Robotics Netw. Artif. Life Hidehiko Yamamoto, Takahiro Watanabe, Takayoshi Yamada
2020	J	`jnl`	Two-person pairwise solvable games. Int. J. Game Theory Takuya Iimura, Toshimasa Maruta, Takahiro Watanabe
2019	—	`conf`	A Hotspot-Pattern-Aware Routing Algorithm for Networks-on-Chip. MCSoC Yaoying Luo, Michael Conrad Meyer, Xin Jiang, Takahiro Watanabe
2019	J	`jnl`	A Low-power Shared Cache Design with Modified PID Controller for Efficient Multicore Embedded Systems. J. Inf. Process. Huatao Zhao, Jiongyao Ye, Takahiro Watanabe
2019	—	`conf`	A Traffic-Robust Routing Algorithm for Network-on-Chip Systems. MCSoC Siying Xu, Michael Conrad Meyer, Xin Jiang, Takahiro Watanabe
2019	—	`conf`	Fault-Tolerant Traffic-Aware Routing Algorithm for 3-D Photonic Networks-on-Chip. MCSoC Michael Conrad Meyer, Yu Wang, Takahiro Watanabe
2019	J	`jnl`	Filter router: An enhanced router design for efficient stacked shared cache network. IEICE Electron. Express Huatao Zhao, Xu Jia, Takahiro Watanabe
2019	B	`conf`	Improvement of Agile Software Development Process Based on Automotive SPICE: A Case Study. EuroSPI Toshihiro Komiyama, Shigeo Konno, Takahiro Watanabe, Shigenori Matsui, Masakazu Kase, Issei Igarashi
2019	—	`conf`	Low-Cost Congestion Detection Mechanism for Networks-on-Chip. MCSoC Zhengqian Han, Michael Conrad Meyer, Xin Jiang, Takahiro Watanabe
2019	—	`conf`	Wavelength-Selective Fog-Computing Network for Big-Data Analytics of Wireless Data. ICEIC Michael Conrad Meyer, Yu Wang, Takahiro Watanabe
2018	—	`conf`	A Time-based Leakage-aware Algorithm for Task Placement and Scheduling Problem on Dynamic Reconfigurable FPGA. ICSAI Tingyu Zhou, Tieyuan Pan, Zhiguo Bao, Takahiro Watanabe
2018	J	`jnl`	Binary action games: Deviation properties, semi-strict equilibria and potentials. Discret. Appl. Math. Takuya Iimura, Pierre von Mouche, Takahiro Watanabe
2018	B	`conf`	Nonlinear Optimization Method Based on Stochastic Gradient Descent for Fast Convergence. SMC Takahiro Watanabe, Hitoshi Iima
2018	—	`conf`	PDA-HyPAR: Path-diversity-aware hybrid planar adaptive routing algorithm for 3D NoCs. ISQED Jindun Dai, Renjie Li, Xin Jiang, Takahiro Watanabe
2017	—	`conf`	An Efficient Deadlock-Free Adaptive Routing Algorithm for 3D Network-on-Chips. MCSoC Jindun Dai, Xin Jiang, Renjie Li, Takahiro Watanabe
2017	—	`conf`	An adaptive routing algorithm based on network partitioning for 3D Network-on-Chip. CITS Jindun Dai, Xin Jiang, Takahiro Watanabe
2017	J	`jnl`	High Performance Virtual Channel Based Fully Adaptive 3D NoC Routing for Congestion and Thermal Problem. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Xin Jiang, Xiangyang Lei, Lian Zeng, Takahiro Watanabe
2017	—	`conf`	High performance virtual channel based fully adaptive thermal-aware routing for 3D NoC. ISQED Xin Jiang, Xiangyang Lei, Lian Zeng, Takahiro Watanabe
2017	—	`conf`	Hybrid path-diversity-dominant output selection method for Network-on-Chip systems. ISOCC Jindun Dai, Wenda Ma, Xin Jiang, Takahiro Watanabe
2017	C	`conf`	Osaka urban phased array radar network experiment. IGARSS Tomoo Ushio, Shigeharu Shimamura, Hiroshi Kikuchi, Fumihiko Mizutani, Kenichi Naito, Takahiro Watanabe, Masakazu Wada, Nobuhiro Takahashi
2016	J	`jnl`	A Fast MER Enumeration Algorithm for Online Task Placement on Reconfigurable FPGAs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Tieyuan Pan, Lian Zeng, Yasuhiro Takashima, Takahiro Watanabe
2016	J	`jnl`	An Efficient Highly Adaptive and Deadlock-Free Routing Algorithm for 3D Network-on-Chip. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Lian Zeng, Tieyuan Pan, Xin Jiang, Takahiro Watanabe
2016	J	`jnl`	An Online Task Placement Algorithm Based on MER Enumeration for Partially Reconfigurable Device. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Tieyuan Pan, Li Zhu, Lian Zeng, Takahiro Watanabe, Yasuhiro Takashima
2016	—	`conf`	Coordinated movement algorithm for accompanying cane robot. MHS Shunki Itadera, Takahiro Watanabe, Yasuhisa Hasegawa, Toshio Fukiida, Masanori Tanimoto, Izumi Kondo
2016	J	`jnl`	Pure strategy equilibrium in finite weakly unilaterally competitive games. Int. J. Game Theory Takuya Iimura, Takahiro Watanabe
2015	J	`jnl`	A Performance Enhanced Dual-switch Network-on-chip Architecture. Inf. Media Technol. Lian Zeng, Xin Jiang, Takahiro Watanabe
2015	J	`jnl`	A Performance Enhanced Dual-switch Network-on-chip Architecture. IPSJ Trans. Syst. LSI Des. Methodol. Lian Zeng, Xin Jiang, Takahiro Watanabe
2015	—	`conf`	A length matching routing method for disordered pins in PCB design. ASP-DAC Ran Zhang, Tieyuan Pan, Li Zhu, Takahiro Watanabe
2015	—	`conf`	A performance enhanced dual-switch Network-on-Chip architecture. ASP-DAC Lian Zeng, Takahiro Watanabe
2015	—	`conf`	Application-specific shared last-level cache optimization for low-power embedded systems. NEWCAS Huatao Zhao, Jiongyao Ye, Xian Su, Takahiro Watanabe
2015	J	`jnl`	Layer Assignment and Equal-length Routing for Disordered Pins in PCB Design. Inf. Media Technol. Ran Zhang, Tieyuan Pan, Li Zhu, Takahiro Watanabe
2015	J	`jnl`	Layer Assignment and Equal-length Routing for Disordered Pins in PCB Design. IPSJ Trans. Syst. LSI Des. Methodol. Ran Zhang, Tieyuan Pan, Li Zhu, Takahiro Watanabe
2014	J	`jnl`	A Sophisticated Routing Algorithm in 3D NoC with Fixed TSVs for Low Energy and Latency. Inf. Media Technol. Xin Jiang, Lian Zeng, Takahiro Watanabe
2014	J	`jnl`	A Sophisticated Routing Algorithm in 3D NoC with Fixed TSVs for Low Energy and Latency. IPSJ Trans. Syst. LSI Des. Methodol. Xin Jiang, Lian Zeng, Takahiro Watanabe
2014	—	`conf`	A randomized algorithm for the fixed-length routing problem. APCCAS Tieyuan Pan, Ran Zhang, Yasuhiro Takashima, Takahiro Watanabe
2014	J	`jnl`	Existence of a pure strategy equilibrium in finite symmetric games where payoff functions are integrally concave. Discret. Appl. Math. Takuya Iimura, Takahiro Watanabe
2013	—	`conf`	A sorting-based IO connection assignment for flip-chip designs. ASICON Ran Zhang, Xue Wei, Takahiro Watanabe
2013	J	`jnl`	An Efficient Algorithm for 3D NoC Architecture Optimization. Inf. Media Technol. Xin Jiang, Ran Zhang, Takahiro Watanabe
2013	J	`jnl`	An Efficient Algorithm for 3D NoC Architecture Optimization. IPSJ Trans. Syst. LSI Des. Methodol. Xin Jiang, Ran Zhang, Takahiro Watanabe
2013	—	`conf`	FPGA Blokus Duo Solver using a massively parallel architecture. FPT Takashi Yoza, Retsu Moriwaki, Yuki Torigai, Yuki Kamikubo, Takayuki Kubota, Takahiro Watanabe, Takumi Fujimori, Hiroyuki Ito, Masato Seo, Kouta Akagi, Yuichiro Yamaji, Minoru Watanabe
2013	—	`conf`	Pseudo Dual Path Processing to reduce the branch misprediction penalty in embedded processors. ASICON Huatao Zhao, Jiongyao Ye, Yuxin Sun, Takahiro Watanabe
2012	J	`jnl`	0.18 μm CMOS proess high-sensitivity optially reonfgurable gatearray VLSI. SIGARCH Comput. Archit. News Takahiro Watanabe, Minoru Watanabe
2012	—	`conf`	0.18-um CMOS Process Highly Sensitive Differential Optically Reconfigurable Gate Array VLSI. ISVLSI Takahiro Watanabe, Minoru Watanabe
2012	J	`jnl`	A Behavior-based Adaptive Access-mode for Low-power Set-associative Caches in Embedded Systems. Inf. Media Technol. Jiongyao Ye, Hongfeng Ding, Yingtao Hu, Takahiro Watanabe
2012	J	`jnl`	A Behavior-based Adaptive Access-mode for Low-power Set-associative Caches in Embedded Systems. J. Inf. Process. Jiongyao Ye, Hongfeng Ding, Yingtao Hu, Takahiro Watanabe
2012	—	`conf`	High Speed - Low Power Optical Configuration on an ORGA with a Phase-modulation Type Holographic Memory. IPDPS Workshops Takahiro Watanabe, Minoru Watanabe
2012	—	`conf`	Inversion/non-inversion reconfiguration scheme for a 0.18 J.1m CMOS process optically reconfigurable gate array VLSI. MWSCAS Takahiro Watanabe, Minoru Watanabe
2012	J	`jnl`	Region Oriented Routing FPGA Architecture for Dynamic Power Gating. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Ce Li, Yiping Dong, Takahiro Watanabe
2012	J	`jnl`	Region-Oriented Placement Algorithm for Coarse-Grained Power-Gating FPGA Architecture. IEICE Trans. Inf. Syst. Ce Li, Yiping Dong, Takahiro Watanabe
2012	—	`conf`	Triple Module Redundancy of a Laser Array Driver Circuit for Optically Reconfigurable Gate Arrays. ARC Takahiro Watanabe, Minoru Watanabe
2011	J	`jnl`	A New Recovery Mechanism in Superscalar Microprocessors by Recovering Critical Misprediction. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Jiongyao Ye, Yu Wan, Takahiro Watanabe
2011	—	`conf`	A behavior-based reconfigurable cache for the low-power embedded processor. ASICON Jiongyao Ye, Jiannan Jin, Takahiro Watanabe
2011	J	`jnl`	An Adaptive Various-Width Data Cache for Low Power Design. IEICE Trans. Inf. Syst. Jiongyao Ye, Yu Wan, Takahiro Watanabe
2011	—	`conf`	An FPGA Connect6 Solver with a two-stage pipelined evaluation. FPT Takahiro Watanabe, Retsu Moriwaki, Yuichiro Yamaji, Yuki Kamikubo, Yuki Torigai, Yuki Nihira, Takashi Yoza, Yumiko Ueno, Yuji Aoyama, Minoru Watanabe
2011	—	`conf`	An efficient design algorithm for exploring flexible topologies in custom adaptive 3D NoCs for high performance and low power. ASICON Xin Jiang, Ran Zhang, Takahiro Watanabe
2011	J	`jnl`	Analysis before Starting an Access: A New Power-Efficient Instruction Fetch Mechanism. IEICE Trans. Inf. Syst. Jiongyao Ye, Yingtao Hu, Hongfeng Ding, Takahiro Watanabe
2011	B	`conf`	Dependable Optically Reconfigurable Gate Array with a Phase-Modulation Type Holographic Memory. FPL Takahiro Watanabe, Minoru Watanabe
2011	C	`conf`	Developing a Real-Time System for Measuring the Consumption of Seasoning. ISM Mayumi Ueda, Takuya Funatomi, Atsushi Hashimoto, Takahiro Watanabe, Michihiko Minoh
2011	—	`conf`	Efficient GA Approach Combined with Taguchi Method for Mixed Constrained Circuit Design. ICCSA Workshops Yiwen Su, Zhiguo Bao, Fangfang Wang, Takahiro Watanabe
2011	J	`jnl`	Fault-tolerant image filter design using particle swarm optimization. Artif. Life Robotics Zhiguo Bao, Fangfang Wang, Xiaoming Zhao, Takahiro Watanabe
2011	J	`jnl`	Low Power Placement and Routing for the Coarse-Grained Power Gating FPGA Architecture. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Ce Li, Yiping Dong, Takahiro Watanabe
2011	A	`conf`	New power-aware placement for region-based FPGA architecture combined with dynamic power gating by PCHM. ISLPED Ce Li, Yiping Dong, Takahiro Watanabe
2010	—	`conf`	A hybrid architecture for efficient FPGA-based implementation of multilayer neural network. APCCAS Zhen Lin, Yiping Dong, Yan Li, Takahiro Watanabe
2010	J	`jnl`	Circuit Design Optimization Using Genetic Algorithm with Parameterized Uniform Crossover. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Zhiguo Bao, Takahiro Watanabe
2010	J	`jnl`	Erratum to: Mixed constrained image filter design using particle swarm optimization. Artif. Life Robotics Zhiguo Bao, Takahiro Watanabe
2010	C	`conf`	High performance implementation of Neural Networks by networks on chip with 5-port 2-virtual channels. ISCAS Yiping Dong, Zhen Lin, Yan Li, Takahiro Watanabe
2010	J	`jnl`	Mixed constrained image filter design using particle swarm optimization. Artif. Life Robotics Zhiguo Bao, Takahiro Watanabe
2010	—	`conf`	Othello Solver based on a soft-core MIMD processor array. FPT Takayuki Mabuchi, Takahiro Watanabe, Retsu Moriwaki, Yuji Aoyama, Amarjargal Gundjalam, Yuichiro Yamaji, Hironari Nakada, Minoru Watanabe
2009	C	`conf`	A Novel Genetic Algorithm with Cell Crossover for Circuit Design Optimization. ISCAS Zhiguo Bao, Takahiro Watanabe
2009	J	`jnl`	A novel genetic algorithm with different structure selection for circuit design optimization. Artif. Life Robotics Zhiguo Bao, Takahiro Watanabe
2008	—	`conf`	A Multiprocessor System for a Small Size Soccer Robot Control System. DELTA Ce Li, Yang Jiang, Zhenyu Wu, Takahiro Watanabe
2007	C	`conf`	Construction of an (r11, r12, r22)-Tournament from a Score Sequence Pair. ISCAS Masaya Takahashi, Takahiro Watanabe, Takeshi Yoshimura
2007	J	`jnl`	Generating even triangulations of the projective plane. J. Graph Theory Yusuke Suzuki, Takahiro Watanabe
2007	J	`jnl`	Score Sequence Pair Problems of ( IEICE Trans. Inf. Syst. Masaya Takahashi, Takahiro Watanabe, Takeshi Yoshimura
2006	—	`conf`	On Authentication between Human and Computer. PerCom Workshops Takahiro Watanabe, Yasunobu Nohara, Kensuke Baba, Sozo Inoue, Hiroto Yasuura
2006	—	`conf`	Realizability of Score Sequence Pair of an (r1l, r12, r22)-Tournament. APCCAS Masaya Takahashi, Takahiro Watanabe, Takeshi Yoshimura
2005	—	`conf`	An RFID-based multi-service system for supporting conference events. AMT Takahiro Watanabe, Sozo Inoue, Hiroto Yasuura, Jun Sasaki, Yasushi Aoki, Kazumi Akimoto
2001	B	`conf`	Sealed Bid Mulit-object Auctions with Necessary Bundles and Its Application to Spectrum Auctions. PRIMA Tomomi Matsui, Takahiro Watanabe
1999	J	`jnl`	Real-time gesture recognition using eigenspace from multi-input imagesequences. Syst. Comput. Jpn. Takahiro Watanabe, Masahiko Yachida
1998	B	`conf`	Real Time Gesture Recognition Using Eigenspace from Multi Input Image Sequence. FG Takahiro Watanabe, Masahiko Yachida
1998	B	`conf`	Real time recognition of gesture and gesture degree information using multi input image sequences. ICPR Takahiro Watanabe, Masahiko Yachida
1998	J	`jnl`	Real-time gesture recognition from dynamic images for construction of any interactive system: Application to a virtual conductor system. Syst. Comput. Jpn. Takahiro Watanabe, Chil-Woo Lee, Masahiko Yachida
1997	A	`conf`	Real-time gesture recognition using KL expansion of image sequence. IROS Takahiro Watanabe, Masahiko Yachida
1996	B	`conf`	Identifying contents page of documents. ICPR Qin Luo, Takahiro Watanabe, Takeshi Nakayama
1996	—	`conf`	Real-Time Gesture Recognition Using Maskable Template Model. ICMCS Takahiro Watanabe, Chil-Woo Lee, Akitoshi Tsukamoto, Masahiko Yachida
1993	J	`jnl`	Construction of fault-tolerant mesh-connected highly parallel computer and its performance analysis. Syst. Comput. Jpn. Itsuo Takanami, Katsushi Inoue, Takahiro Watanabe, Minoru Oka
1983	J	`jnl`	An approximation algorithm for the hamiltonian walk problem on maximal planar graphs. Discret. Appl. Math. Takao Nishizeki, Takao Asano, Takahiro Watanabe
1980	J	`jnl`	An upper bound on the length of a Hamiltonian walk of a maximal planar graph. J. Graph Theory Takao Asano, Takao Nishizeki, Takahiro Watanabe