Takahiro Hanyu

262 papers A 5B 2C 18Misc 3Journal 106Unranked 128

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Analog-to-Stochastic Converter Using Magnetic Tunnel Junction Devices for Vision Chips. CoRR Naoya Onizawa, Daisaku Katagiri, Warren J. Gross, Takahiro Hanyu
2026	J	`jnl`	Bit-Width-Aware Design Environment for Few-Shot Learning on Edge AI Hardware. CoRR R. Kanda, Hugo Le Blevec, Naoya Onizawa, Mathieu Léonardon, Vincent Gripon, Takahiro Hanyu
2026	J	`jnl`	Design Environment of Quantization-Aware Edge AI Hardware for Few-Shot Learning. CoRR R. Kanda, Naoya Onizawa, Mathieu Léonardon, Vincent Gripon, Takahiro Hanyu
2026	J	`jnl`	Efficient CMOS Invertible Logic Using Stochastic Computing. CoRR Sean C. Smithson, Naoya Onizawa, Brett H. Meyer, Warren J. Gross, Takahiro Hanyu
2026	J	`jnl`	Efficient Few-Shot Learning for Edge AI via Knowledge Distillation on MobileViT. CoRR Shuhei Tsuyuki, Reda Bensaid, Jérémy Morlier, Mathieu Léonardon, Naoya Onizawa, Vincent Gripon, Takahiro Hanyu
2026	J	`jnl`	Energy-Efficient p-Bit-Based Fully-Connected Quantum-Inspired Simulated Annealer with Dual BRAM Architecture. CoRR Naoya Onizawa, Taiga Kubuta, Duckgyu Shin, Takahiro Hanyu
2026	J	`jnl`	Energy-Efficient p-bit-Based Fully-Connected Quantum-Inspired Simulated Annealer With Dual BRAM Architecture. IEEE Access Naoya Onizawa, Taiga Kubuta, Duckgyu Shin, Takahiro Hanyu
2026	J	`jnl`	Enhanced Convergence in p-bit Based Simulated Annealing with Partial Deactivation for Large-Scale Combinatorial Optimization Problems. CoRR Naoya Onizawa, Takahiro Hanyu
2026	J	`jnl`	GPU-accelerated simulated annealing based on p-bits with real-world device-variability modeling. CoRR Naoya Onizawa, Takahiro Hanyu
2026	J	`jnl`	High Convergence Rates of CMOS Invertible Logic Circuits Based on Many-Body Hamiltonians. CoRR Naoya Onizawa, Takahiro Hanyu
2026	J	`jnl`	Memory-Efficient FPGA Implementation of Stochastic Simulated Annealing. CoRR Duckgyu Shin, Naoya Onizawa, Warren J. Gross, Takahiro Hanyu
2025	—	`conf`	A Nonvolatile IoT Sensor Node Based on Input-Data Driven Power-Gating Scheme and its Emulation Using FPGA and Temperature Sensor. MCSoC Daisuke Suzuki, Takahiro Hanyu
2025	—	`conf`	An FPGA-based rapid-prototyping platform for spintronics-based edge-computing hardware. ISMVL Daisuke Suzuki, Akira Tamakoshi, Tomohiro Yoneda, Masanori Natsui, Yasuhiro Takako, Takahiro Hanyu
2025	C	`conf`	Bit-Width-Aware Design Environment for Few-Shot Learning on Edge AI Hardware. ISCAS R. Kanda, Hugo Le Blevec, Naoya Onizawa, Mathieu Léonardon, Vincent Gripon, Takahiro Hanyu
2025	C	`conf`	Design of a Low-Energy MTJ-Based Nonvolatile Register Based on a Differential Information Storing Scheme. ISCAS Tomoo Yoshida, Masanori Natsui, Takahiro Hanyu
2025	J	`jnl`	Design of a single-capacitor-based threshold-adjustable power management circuit for task-aware waste-minimized energy harvesting. IEICE Electron. Express Fangcen Zhong, Masanori Natsui, Takahiro Hanyu
2025	J	`jnl`	Design of an Intermittent-Computing-Oriented Nonvolatile Register With a Switching-Probability-Aware Store-and-Verify Scheme. IEEE Access Masanori Natsui, Takahiro Hanyu
2025	—	`conf`	Generating Hamiltonians with Known Minimum Energy Based on Ground-State Spin Logic for Probabilistic-Bit-Based Simulated Annealing. ISMVL Naoya Onizawa, Takahiro Hanyu
2025	—	`conf`	Implementation of an MRAM-Based Edge AI Hardware with a Fine-Grained Power-Gating Technique. ISMVL Tomohiro Yoneda, Yasuhiro Takako, Akira Tamakoshi, Masanori Natsui, Daisuke Suzuki, Takahiro Hanyu
2025	—	`conf`	Intelligent Power-Gating Technique with Quick Wake-Up/Sleep Functionality for Spintronics-Based Edge Computing Hardware. ISMVL Fangcen Zhong, Masanori Natsui, Takahiro Hanyu
2025	—	`conf`	Random Forest-Based Approximation for Quantized CNNs on Edge FPGAs. MCSoC Yasuyuki Suzuki, Hiroshi Saito, Shogo Semba, Yoichi Tomioka, Takahiro Hanyu
2024	—	`conf`	Design Environment of Quantization-Aware Edge AI Hardware for Few-Shot Learning. MWSCAS R. Kanda, Naoya Onizawa, Mathieu Léonardon, Vincent Gripon, Takahiro Hanyu
2024	B	`conf`	Design of a High-Speed and Low-Power Threshold Adjustment Unit for Battery-Free Edge Devices. IJCNN Fangcen Zhong, Masanori Natsui, Takahiro Hanyu
2024	—	`conf`	Design of an Energy/Area-Aware MTJ-Based Nonvolatile Register with a Reference-Load Sharing Scheme. MWSCAS Tomoo Yoshida, Masanori Natsui, Takahiro Hanyu
2024	J	`jnl`	Error-Tolerance-Aware Write-Energy Reduction of MTJ-Based Quantized Neural Network Hardware. IEICE Trans. Inf. Syst. Ken Asano, Masanori Natsui, Takahiro Hanyu
2024	—	`conf`	Error-Tolerant Quantized Neural Network Based on Non-Weighted Arithmetic. ISMVL Masanori Natsui, Ken Asano, Takahiro Hanyu
2024	J	`jnl`	Stochastic Simulated Quantum Annealing for Fast Solution of Combinatorial Optimization Problems. IEEE Access Naoya Onizawa, Ryoma Sasaki, Duckgyu Shin, Warren J. Gross, Takahiro Hanyu
2023	—	`conf`	Design of an Error-Tolerant Nonvolatile Register for Energy-Aware Intermittent Computing. MWSCAS Kaede Sakai, Masanori Natsui, Takahiro Hanyu
2023	—	`conf`	Error-Sensitivity-Aware Write-Energy Optimization for an MTJ-Based Binarized Neural Network. ICECS Ken Asano, Masanori Natsui, Takahiro Hanyu
2023	J	`jnl`	Fast-Converging Simulated Annealing for Ising Models Based on Integral Stochastic Computing. IEEE Trans. Neural Networks Learn. Syst. Naoya Onizawa, Kota Katsuki, Duckgyu Shin, Warren J. Gross, Takahiro Hanyu
2023	C	`conf`	High-Performance/Low-Area Power-Gating Switch Linear Array for Energy-Efficient LSIs with an Optimum Switch-Timing Control. ISCAS Fangcen Zhong, Masanori Natsui, Takahiro Hanyu
2023	—	`conf`	Improving Stochastic Quantum-Like Annealing Based on Rerandomization. ICECS Ryoma Sasaki, Duckgyu Shin, Naoya Onizawa, Takahiro Hanyu
2023	J	`jnl`	Local Energy Distribution Based Hyperparameter Determination for Stochastic Simulated Annealing. CoRR Naoya Onizawa, Kyo Kuroki, Duckgyu Shin, Takahiro Hanyu
2023	J	`jnl`	Memory-Efficient FPGA Implementation of Stochastic Simulated Annealing. IEEE J. Emerg. Sel. Topics Circuits Syst. Duckgyu Shin, Naoya Onizawa, Warren J. Gross, Takahiro Hanyu
2023	J	`jnl`	Self-Adaptive Gate Control for Efficient Escape From Local Minimum Energy on Invertible Logic. IEEE Access Naoya Onizawa, Koji Yano, Seiichi Shin, Hiroyuki Fujita, Takahiro Hanyu
2023	—	`conf`	Stochastic Implementation of Simulated Quantum Annealing on PYNQ. ICFPT Taiga Kubuta, Duckgyu Shin, Naoya Onizawa, Takahiro Hanyu
2023	J	`jnl`	Stochastic Quantum Monte Carlo Algorithm for Large-Scale Combinatorial Optimization Problems. CoRR Naoya Onizawa, Ryoma Sasaki, Duckgyu Shin, Warren J. Gross, Takahiro Hanyu
2023	—	`conf`	Write-Energy Relaxation of MTJ-Based Quantized Neural-Network Hardware. ISMVL Ken Asano, Masanori Natsui, Takahiro Hanyu
2022	—	`conf`	A Spintronics-Based Nonvolatile FPGA and Its Application to Edge-AI Accelerator. MCSoC Daisuke Suzuki, Takahiro Hanyu
2022	—	`conf`	Energy-Efficient Nonvolatile RISC-V CPU with a Custom Instruction-Controlled Accelerator. MWSCAS Keisuke Sakamoto, Masanori Natsui, Takahiro Hanyu
2022	—	`conf`	Fast Solving Complete 2000-Node Optimization Using Stochastic-Computing Simulated Annealing. ICECS 2022 Kota Katsuki, Duckgyu Shin, Naoya Onizawa, Takahiro Hanyu
2022	J	`jnl`	Implementation of CMOS Invertible Logic on Zynq-SoC Platform: A Case Study of Training BNN. FLAP Duckgyu Shin, Naoya Onizawa, Takahiro Hanyu
2021	J	`jnl`	A Design Framework for Invertible Logic. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Naoya Onizawa, Kaito Nishino, Sean C. Smithson, Brett H. Meyer, Warren J. Gross, Hitoshi Yamagata, Hiroyuki Fujita, Takahiro Hanyu
2021	—	`conf`	A Memory-Access-Minimized BCNN Accelerator Using Nonvolatile FPGA with Only-Once- Write Shifting. MCSoC Daisuke Suzuki, Takahiro Oka, Takahiro Hanyu
2021	J	`jnl`	Dual-Port SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations Under Field-Assistance-Free Condition. IEEE J. Solid State Circuits Masanori Natsui, Akira Tamakoshi, Hiroaki Honjo, Toshinari Watanabe, Takashi Nasuno, Chaoliang Zhang, Takaho Tanigawa, Hirofumi Inoue, Masaaki Niwa, Toru Yoshiduka, Yasuo Noguchi, Mitsuo Yasuhira, Yitao Ma, Hui Shen, Shunsuke Fukami, Hideo Sato, Shoji Ikeda, Hideo Ohno, Tetsuo Endoh, Takahiro Hanyu
2021	J	`jnl`	Hardware Acceleration of Large-Scale CMOS Invertible Logic Based on Sparse Hamiltonian Matrices. IEEE Open J. Circuits Syst. Naoya Onizawa, Akira Tamakoshi, Takahiro Hanyu
2021	C	`conf`	High Convergence Rates of CMOS Invertible Logic Circuits Based on Many-Body Hamiltonians. ISCAS Naoya Onizawa, Takahiro Hanyu
2021	J	`jnl`	Multi-Context TCAM-Based Selective Computing: Design Space Exploration for a Low-Power NN. IEEE Trans. Circuits Syst. I Regul. Pap. Ren Arakawa, Naoya Onizawa, Jean-Philippe Diguet, Takahiro Hanyu
2021	J	`jnl`	Nonvolatile Field-Programmable Gate Array Using a Standard-Cell-Based Design Flow. IEICE Trans. Inf. Syst. Daisuke Suzuki, Takahiro Hanyu
2021	—	`conf`	Scalable Hardware Architecture for Invertible Logic with Sparse Hamiltonian Matrices. SiPS Naoya Onizawa, Akira Tamakoshi, Takahiro Hanyu
2021	J	`jnl`	Sparse Random Signals for Fast Convergence on Invertible Logic. IEEE Access Naoya Onizawa, Makoto Kato, Hitoshi Yamagata, Koji Yano, Seiichi Shin, Hiroyuki Fujita, Takahiro Hanyu
2020	J	`jnl`	Design Automation of Invertible Logic Circuit from a Standard HDL Description. FLAP Makoto Kato, Naoya Onizawa, Takahiro Hanyu
2020	—	`conf`	Design and Evaluation of a Synthesizable Standard-Cell-Based Nonvolatile FPGA. ISMVL Daisuke Suzuki, Takahiro Hanyu
2020	—	`conf`	Design of an Energy-Efficient True Random Number Generator Based on Triple Read-Write Data-Stream Multiplexing of MTJ Devices. NEWCAS Akira Tamakoshi, Naoya Onizawa, Hitoshi Yamagata, Hiroyuki Fujita, Takahiro Hanyu
2020	J	`jnl`	Design of an MTJ-based Nonvolatile Multi-context Ternary Content-addressable Memory. FLAP Naoya Onizawa, Ren Arakawa, Takahiro Hanyu
2020	—	`conf`	Dual-Port Field-Free SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations under 55-nm CMOS Technology and 1.2-V Supply Voltage. VLSI Circuits Masanori Natsui, Akira Tamakoshi, Hiroaki Honjo, Toshinari Watanabe, Takashi Nasuno, Chaoliang Zhang, Takaho Tanigawa, Hirofumi Inoue, Masaaki Niwa, Toru Yoshiduka, Yasuo Noguchi, Mitsuo Yasuhira, Yitao Ma, Hui Shen, Shunsuke Fukami, Hideo Sato, Shoji Ikeda, Hideo Ohno, Tetsuo Endoh, Takahiro Hanyu
2020	J	`jnl`	Fast Hardware-based Learning Algorithm for Binarized Perceptrons using CMOS Invertible Logic. FLAP Naoya Onizawa, Duckgyu Shin, Takahiro Hanyu
2020	J	`jnl`	High-Throughput/Low-Energy MTJ-Based True Random Number Generator Using a Multi-Voltage/Current Converter. IEEE Trans. Very Large Scale Integr. Syst. Naoya Onizawa, Shogo Mukaida, Akira Tamakoshi, Hitoshi Yamagata, Hiroyuki Fujita, Takahiro Hanyu
2020	J	`jnl`	In-Hardware Training Chip Based on CMOS Invertible Logic for Machine Learning. IEEE Trans. Circuits Syst. I Fundam. Theory Appl. Naoya Onizawa, Sean C. Smithson, Brett H. Meyer, Warren J. Gross, Takahiro Hanyu
2020	J	`jnl`	Memristive Computational Memory Using Memristor Overwrite Logic (MOL). IEEE Trans. Very Large Scale Integr. Syst. Khaled Alhaj Ali, Mostafa Rizk, Amer Baghdadi, Jean-Philippe Diguet, Jalal Jomaah, Naoya Onizawa, Takahiro Hanyu
2020	J	`jnl`	Training Hardware for Binarized Convolutional Neural Network Based on CMOS Invertible Logic. IEEE Access Duckgyu Shin, Naoya Onizawa, Warren J. Gross, Takahiro Hanyu
2019	J	`jnl`	A 47.14-µW 200-MHz MOS/MTJ-Hybrid Nonvolatile Microcontroller Unit Embedding STT-MRAM and FPGA for IoT Applications. IEEE J. Solid State Circuits Masanori Natsui, Daisuke Suzuki, Akira Tamakoshi, Toshinari Watanabe, Hiroaki Honjo, Hiroki Koike, Takashi Nasuno, Yitao Ma, Takaho Tanigawa, Yasuo Noguchi, Mitsuo Yasuhira, Hideo Sato, Shoji Ikeda, Hideo Ohno, Tetsuo Endoh, Takahiro Hanyu
2019	Misc	`conf`	A Design Framework for Invertible Logic. ACSSC Naoya Onizawa, Kaito Nishino, Sean C. Smithson, Brett H. Meyer, Warren J. Gross, Hitoshi Yamagata, Hiroyuki Fujita, Takahiro Hanyu
2019	—	`conf`	An FPGA-Accelerated Fully Nonvolatile Microcontroller Unit for Sensor-Node Applications in 40nm CMOS/MTJ-Hybrid Technology Achieving 47.14μW Operation at 200MHz. ISSCC Masanori Natsui, Daisuke Suzuki, Akira Tamakoshi, Toshinari Watanabe, Hiroaki Honjo, Hiroki Koike, Takashi Nasuno, Yitao Ma, Takaho Tanigawa, Yasuo Noguchi, Mitsuo Yasuhira, Hideo Sato, Shoji Ikeda, Hideo Ohno, Tetsuo Endoh, Takahiro Hanyu
2019	J	`jnl`	Circuit optimization technique of nonvolatile logic-in-memory based lookup table circuits using magnetic tunnel junction devices. Microelectron. J. Daisuke Suzuki, Takahiro Oka, Takahiro Hanyu
2019	—	`conf`	Design of a Current-Mode Linear-Sum-Based Bitcounting Circuit with an MTJ-Based Compensator for Binarized Neural Networks. ISMVL Tomoki Chiba, Masanori Natsui, Takahiro Hanyu
2019	J	`jnl`	Efficient CMOS Invertible Logic Using Stochastic Computing. IEEE Trans. Circuits Syst. I Regul. Pap. Sean C. Smithson, Naoya Onizawa, Brett H. Meyer, Warren J. Gross, Takahiro Hanyu
2019	—	`conf`	FPGA Implementation of Binarized Perceptron Learning Hardware Using CMOS Invertible Logic. ICECS Duckgyu Shin, Naoya Onizawa, Takahiro Hanyu
2019	—	`conf`	Multi-Context TCAM Based Selective Computing Architecture for a Low-Power NN. ICECS Ren Arakawa, Naoya Onizawa, Jean-Philippe Diguet, Takahiro Hanyu
2019	—	`conf`	Stochastic-Computing Based Brainwave LSI Towards an Intelligence Edge. ICECS Naoya Onizawa, Warren J. Gross, Takahiro Hanyu
2018	J	`jnl`	A Generalized Stochastic Implementation of the Disparity Energy Model for Depth Perception. J. Signal Process. Syst. Kaushik Boga, François Leduc-Primeau, Naoya Onizawa, Kazumichi Matsumiya, Takahiro Hanyu, Warren J. Gross
2018	J	`jnl`	An Accuracy/Energy-Flexible Configurable Gabor-Filter Chip Based on Stochastic Computation With Dynamic Voltage-Frequency-Length Scaling. IEEE J. Emerg. Sel. Topics Circuits Syst. Naoya Onizawa, Daisaku Katagiri, Kazumichi Matsumiya, Warren J. Gross, Takahiro Hanyu
2018	J	`jnl`	Design of MTJ-Based nonvolatile logic gates for quantized neural networks. Microelectron. J. Masanori Natsui, Tomoki Chiba, Takahiro Hanyu
2018	—	`conf`	Design of a Low-Power MTJ-Based True Random Number Generator Using a Multi-voltage/Current Converter. ISMVL Shogo Mukaida, Naoya Onizawa, Takahiro Hanyu
2018	A	`conf`	Design of an MTJ-Based Nonvolatile LUT Circuit with a Data-Update Minimized Shift Operation for an Ultra-Low-Power FPGA: (Abstract Only). FPGA Daisuke Suzuki, Takahiro Hanyu
2018	C	`conf`	High-Precision Stochastic State-Space Digital Filters Based on Minimum Roundoff Noise Structure. ISCAS Shunsuke Koshita, Naoya Onizawa, Masahide Abe, Takahiro Hanyu, Masayuki Kawamata
2018	J	`jnl`	MTJ-based asynchronous circuits for Re-initialization free computing against power failures. Microelectron. J. Naoya Onizawa, Masashi Imai, Tomohiro Yoneda, Takahiro Hanyu
2018	J	`jnl`	Networked Power-Gated MRAMs for Memory-Based Computing. IEEE Trans. Very Large Scale Integr. Syst. Jean-Philippe Diguet, Naoya Onizawa, Mostafa Rizk, Martha Johanna Sepúlveda, Amer Baghdadi, Takahiro Hanyu
2018	—	`conf`	Study of Stochastic Invertible Multiplier Designs. ICECS Kaito Nishino, Sean C. Smithson, Naoya Onizawa, Brett H. Meyer, Warren J. Gross, Hitoshi Yamagata, Hiroyuki Fujita, Takahiro Hanyu
2018	—	`conf`	Systematic Intrusion Detection Technique for an In-vehicle Network Based on Time-Series Feature Extraction. ISMVL Hiroki Suda, Masanori Natsui, Takahiro Hanyu
2017	—	`conf`	Accuracy/energy-flexible stochastic configurable 2D Gabor filter with instant-on capability. ESSCIRC Naoya Onizawa, Kazumichi Matsumiya, Warren J. Gross, Takahiro Hanyu
2017	J	`jnl`	Area/Energy-Efficient Gammatone Filters Based on Stochastic Computation. IEEE Trans. Very Large Scale Integr. Syst. Naoya Onizawa, Shunsuke Koshita, Shuichi Sakamoto, Masahide Abe, Masayuki Kawamata, Takahiro Hanyu
2017	—	`conf`	Design of stochastic asymmetric compensation filters for auditory signal processing. GlobalSIP Naoya Onizawa, Shunsuke Koshita, Shuichi Sakamoto, Masayuki Kawamata, Takahiro Hanyu
2017	J	`jnl`	Energy-Efficient and Highly-Reliable Nonvolatile FPGA Using Self-Terminated Power-Gating Scheme. IEICE Trans. Inf. Syst. Daisuke Suzuki, Takahiro Hanyu
2017	—	`conf`	Evaluation of Stochastic Cascaded IIR Filters. ISMVL Naoya Onizawa, Shunsuke Koshita, Shuichi Sakamoto, Masayuki Kawamata, Takahiro Hanyu
2017	J	`jnl`	Foreword. IEICE Trans. Inf. Syst. Takahiro Hanyu
2017	J	`jnl`	High-Accuracy and Area-Efficient Stochastic FIR Digital Filters Based on Hybrid Computation. IEICE Trans. Inf. Syst. Shunsuke Koshita, Naoya Onizawa, Masahide Abe, Takahiro Hanyu, Masayuki Kawamata
2017	—	`conf`	MTJ-based Asynchronous Circuits for Re-initialization Free Computing against Power Failures. ASYNC Naoya Onizawa, Masashi Imai, Takahiro Hanyu, Tomohiro Yoneda
2017	—	`conf`	NoC-MRAM architecture for memory-based computing: Database-search case study. NEWCAS Mostafa Rizk, Jean-Philippe Diguet, Naoya Onizawa, Amer Baghdadi, Martha Johanna Sepúlveda, Y. Akgul, Vincent Gripon, Takahiro Hanyu
2017	J	`jnl`	Sudden Power-Outage Resilient In-Processor Checkpointing for Energy-Harvesting Nonvolatile Processors. IEEE Trans. Emerg. Top. Comput. Naoya Onizawa, Akira Mochizuki, Akira Tamakoshi, Takahiro Hanyu
2017	A	`conf`	Three-terminal MTJ-based nonvolatile logic circuits with self-terminated writing mechanism for ultra-low-power VLSI processor. DATE Takahiro Hanyu, Daisuke Suzuki, Naoya Onizawa, Masanori Natsui
2017	J	`jnl`	VLSI Implementation of Deep Neural Network Using Integral Stochastic Computing. IEEE Trans. Very Large Scale Integr. Syst. Arash Ardakani, François Leduc-Primeau, Naoya Onizawa, Takahiro Hanyu, Warren J. Gross
2016	B	`conf`	A low-power MTJ-based nonvolatile FPGA using self-terminated logic-in-memory structure. FPL Daisuke Suzuki, Takahiro Hanyu
2016	—	`conf`	A study of a top-down error correction technique using Recurrent-Neural-Network-based learning. NEWCAS Masanori Natsui, Naoto Sugaya, Takahiro Hanyu
2016	J	`jnl`	An Overview of Nonvolatile Emerging Memories - Spintronics for Working Memories. IEEE J. Emerg. Sel. Topics Circuits Syst. Tetsuo Endoh, Hiroki Koike, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno
2016	—	`conf`	Context-Based Error Correction Scheme Using Recurrent Neural Network for Resilient and Efficient Intra-Chip Data Transmission. ISMVL Naoto Sugaya, Masanori Natsui, Takahiro Hanyu
2016	—	`conf`	Energy-Efficient and Highly-Reliable Nonvolatile FPGA Using Self-Terminated Power-Gating Scheme. ISMVL Daisuke Suzuki, Takahiro Hanyu
2016	J	`jnl`	Evaluation of Soft-Delay-Error Effects in Content-Addressable Memory. J. Multiple Valued Log. Soft Comput. Naoya Onizawa, Noboru Sakimura, Ryusuke Nebashi, Tadahiko Sugibayashi, Takahiro Hanyu
2016	Misc	`conf`	Gammatone filter based on stochastic computation. ICASSP Naoya Onizawa, Shunsuke Koshita, Shuichi Sakamoto, Masahide Abe, Masayuki Kawamata, Takahiro Hanyu
2016	J	`jnl`	Hardware Implementation of Associative Memories Based on Multiple-Valued Sparse Clustered Networks. IEEE J. Emerg. Sel. Topics Circuits Syst. Naoya Onizawa, Hooman Jarollahi, Takahiro Hanyu, Warren J. Gross
2016	—	`conf`	Realization of FIR Digital Filters Based on Stochastic/Binary Hybrid Computation. ISMVL Shunsuke Koshita, Naoya Onizawa, Masahide Abe, Takahiro Hanyu, Masayuki Kawamata
2016	—	`conf`	Redundant STT-MTJ-based nonvolatile flip-flops for low write-error-rate operations. NEWCAS Naoya Onizawa, Takahiro Hanyu
2016	J	`jnl`	Standby-Power-Free Integrated Circuits Using MTJ-Based VLSI Computing. Proc. IEEE Takahiro Hanyu, Tetsuo Endoh, Daisuke Suzuki, Hiroki Koike, Yitao Ma, Naoya Onizawa, Masanori Natsui, Shoji Ikeda, Hideo Ohno
2016	C	`conf`	Stochastic behavior-considered VLSI CAD environment for MTJ/MOS-hybrid microprocessor design. ISCAS Masanori Natsui, Akira Tamakoshi, Akira Mochizuki, Hiroki Koike, Hideo Ohno, Tetsuo Endoh, Takahiro Hanyu
2016	—	`conf`	VLSI implementation of deep neural networks using integral stochastic computing. ISTC Arash Ardakani, François Leduc-Primeau, Naoya Onizawa, Takahiro Hanyu, Warren J. Gross
2015	—	`conf`	A sudden power-outage resilient nonvolatile microprocessor for immediate system recovery. NANOARCH Naoya Onizawa, Akira Mochizuki, Akira Tamakoshi, Takahiro Hanyu
2015	C	`conf`	Design of a computational nonvolatile RAM for a greedy energy-efficient VLSI processor. IECON Akira Mochizuki, Naoto Yube, Takahiro Hanyu
2015	—	`conf`	Design of an MTJ-based nonvolatile lookup table circuit using an energy-efficient single-ended logic-in-memory structure. MWSCAS Daisuke Suzuki, Takahiro Hanyu
2015	—	`conf`	Design of an STT-MTJ based true random number generator using digitally controlled probability-locked loop. NEWCAS Satoshi Oosawa, Takayuki Konishi, Naoya Onizawa, Takahiro Hanyu
2015	—	`conf`	Early-Stage Operation-Skipping Scheme for Low-Power Stochastic Image Processors. ISMVL Daisaku Katagiri, Naoya Onizawa, Takahiro Hanyu
2015	—	`conf`	Fabrication of a 3000-6-input-LUTs embedded and block-level power-gated nonvolatile FPGA chip using p-MTJ-based logic-in-memory structure. VLSIC Daisuke Suzuki, Masanori Natsui, Akira Mochizuki, Sadahiko Miura, Hiroaki Honjo, Hideo Sato, Shunsuke Fukami, Shoji Ikeda, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu
2015	—	`conf`	Frequency-flexible stochastic Gabor filter. DSP Naoya Onizawa, Daisaku Katagiri, Kazumichi Matsumiya, Warren J. Gross, Takahiro Hanyu
2015	J	`jnl`	Gabor Filter Based on Stochastic Computation. IEEE Signal Process. Lett. Naoya Onizawa, Daisaku Katagiri, Kazumichi Matsumiya, Warren J. Gross, Takahiro Hanyu
2015	J	`jnl`	Nonvolatile Logic-in-Memory LSI Using Cycle-Based Power Gating and its Application to Motion-Vector Prediction. IEEE J. Solid State Circuits Masanori Natsui, Daisuke Suzuki, Noboru Sakimura, Ryusuke Nebashi, Yukihide Tsuji, Ayuka Morioka, Tadahiko Sugibayashi, Sadahiko Miura, Hiroaki Honjo, Keizo Kinoshita, Shoji Ikeda, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu
2015	—	`conf`	Scaled IIR filter based on stochastic computation. MWSCAS Naoya Onizawa, Shunsuke Koshita, Takahiro Hanyu
2015	A	`conf`	Spintronics-based nonvolatile logic-in-memory architecture towards an ultra-low-power and highly reliable VLSI computing paradigm. DATE Takahiro Hanyu, Daisuke Suzuki, Naoya Onizawa, Shoun Matsunaga, Masanori Natsui, Akira Mochizuki
2015	—	`conf`	Stochastic implementation of the disparity energy model for depth perception. SiPS Kaushik Boga, Naoya Onizawa, François Leduc-Primeau, Kazumichi Matsumiya, Takahiro Hanyu, Warren J. Gross
2015	J	`jnl`	VLSI Implementation of Deep Neural Network Using Integral Stochastic Computing. CoRR Arash Ardakani, François Leduc-Primeau, Naoya Onizawa, Takahiro Hanyu, Warren J. Gross
2015	—	`conf`	Write-Operation Frequency Reduction for Nonvoratile Logic LSI with a Short Break-Even Time. ISMVL Takeaki Akutsu, Masanori Natsui, Takahiro Hanyu
2014	—	`conf`	10.5 A 90nm 20MHz fully nonvolatile microcontroller for standby-power-critical applications. ISSCC Noboru Sakimura, Yukihide Tsuji, Ryusuke Nebashi, Hiroaki Honjo, Ayuka Morioka, Kunihiko Ishihara, Keizo Kinoshita, Shunsuke Fukami, Sadahiko Miura, Naoki Kasai, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu, Tadahiko Sugibayashi
2014	—	`conf`	A Compact Soft-Error Tolerant Asynchronous TCAM Based on a Transistor/Magnetic-Tunnel-Junction Hybrid Dual-Rail Word Structure. ASYNC Naoya Onizawa, Shoun Matsunaga, Takahiro Hanyu
2014	J	`jnl`	A Nonvolatile Associative Memory-Based Context-Driven Search Engine Using 90 nm CMOS/MTJ-Hybrid Logic-in-Memory Architecture. IEEE J. Emerg. Sel. Topics Circuits Syst. Hooman Jarollahi, Naoya Onizawa, Vincent Gripon, Noboru Sakimura, Tadahiko Sugibayashi, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu, Warren J. Gross
2014	J	`jnl`	A compact low-power nonvolatile flip-flop using domain-wall-motion-device-based single-ended structure. IEICE Electron. Express Daisuke Suzuki, Noboru Sakimura, Masanori Natsui, Akira Mochizuki, Tadahiko Sugibayashi, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu
2014	C	`conf`	A delay circuit with 4-terminal magnetic-random-access-memory device for power-efficient time- domain signal processing. ISCAS Ryusuke Nebashi, Noboru Sakimura, Hiroaki Honjo, Ayuka Morioka, Yukihide Tsuji, Kunihiko Ishihara, Keiichi Tokutome, Sadahiko Miura, Shunsuke Fukami, Keizo Kinoshita, Takahiro Hanyu, Tetsuo Endoh, Naoki Kasai, Hideo Ohno, Tadahiko Sugibayashi
2014	—	`conf`	Algorithm and architecture for a multiple-field context-driven search engine using fully-parallel clustered associative memories. SiPS Hooman Jarollahi, Naoya Onizawa, Vincent Gripon, Takahiro Hanyu, Warren J. Gross
2014	—	`conf`	An NoC-based evaluation platform for safety-critical automotive applications. APCCAS Tomohiro Yoneda, Masashi Imai, Hiroshi Saito, Takahiro Hanyu, Kenji Kise, Yuichi Nakamura
2014	—	`conf`	Analog-to-stochastic converter using magnetic-tunnel junction devices. NANOARCH Naoya Onizawa, Daisaku Katagiri, Warren J. Gross, Takahiro Hanyu
2014	—	`conf`	Associative Memories Based on Multiple-Valued Sparse Clustered Networks. ISMVL Hooman Jarollahi, Naoya Onizawa, Takahiro Hanyu, Warren J. Gross
2014	J	`jnl`	Associative Memories Based on Multiple-Valued Sparse Clustered Networks. CoRR Hooman Jarollahi, Naoya Onizawa, Takahiro Hanyu, Warren J. Gross
2014	J	`jnl`	Asynchronous Stochastic Decoding of LDPC Codes: Algorithm and Simulation Model. IEICE Trans. Inf. Syst. Naoya Onizawa, Warren J. Gross, Takahiro Hanyu, Vincent C. Gaudet
2014	J	`jnl`	Clockless Stochastic Decoding of Low-Density Parity-Check Codes: Architecture and Simulation Model. J. Signal Process. Syst. Naoya Onizawa, Warren J. Gross, Takahiro Hanyu, Vincent C. Gaudet
2014	J	`jnl`	Complementary 5T-4MTJ nonvolatile TCAM cell circuit with phase-selective parallel writing scheme. IEICE Electron. Express Shoun Matsunaga, Akira Mochizuki, Noboru Sakimura, Ryusuke Nebashi, Tadahiko Sugibayashi, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu
2014	—	`conf`	Design of a Quaternary Single-Ended Current-Mode Circuit for an Energy-Efficient Inter-chip Asynchronous Communication Link. ISMVL Akira Mochizuki, Hirokatsu Shirahama, Takahiro Hanyu
2014	—	`conf`	Design of a soft-error tolerant 9-transistor/6-magnetic-tunnel-junction hybrid cell based nonvolatile TCAM. NEWCAS Naoya Onizawa, Shoun Matsunaga, Takahiro Hanyu
2014	J	`jnl`	Design of an Energy-Efficient Ternary Current-Mode Intra-Chip Communication Link for an Asynchronous Network-on-Chip. IEICE Trans. Inf. Syst. Akira Mochizuki, Hirokatsu Shirahama, Yuma Watanabe, Takahiro Hanyu
2014	J	`jnl`	Design of an energy-efficient 2T-2MTJ nonvolatile TCAM based on a parallel-serial-combined search scheme. IEICE Electron. Express Shoun Matsunaga, Akira Mochizuki, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu
2014	C	`conf`	Energy-aware current-mode inter-chip link for a dependable GALS NoC platform. ISCAS Hirokatsu Shirahama, Akira Mochizuki, Yuma Watanabe, Takahiro Hanyu
2014	—	`conf`	Fabrication of a MTJ-based multilevel resistor towards process-variaton-resilient logic LSI. NEWCAS Masanori Natsui, Takahiro Hanyu
2014	J	`jnl`	High-Throughput Compact Delay-Insensitive Asynchronous NoC Router. IEEE Trans. Computers Naoya Onizawa, Atsushi Matsumoto, Tomoyoshi Funazaki, Takahiro Hanyu
2014	J	`jnl`	High-Throughput Low-Energy Self-Timed CAM Based on Reordered Overlapped Search Mechanism. IEEE Trans. Circuits Syst. I Regul. Pap. Naoya Onizawa, Shoun Matsunaga, Vincent C. Gaudet, Warren J. Gross, Takahiro Hanyu
2014	J	`jnl`	High-Throughput Partially Parallel Inter-Chip Link Architecture for Asynchronous Multi-Chip NoCs. IEICE Trans. Inf. Syst. Naoya Onizawa, Akira Mochizuki, Hirokatsu Shirahama, Masashi Imai, Tomohiro Yoneda, Takahiro Hanyu
2014	—	`conf`	Highly reliable single-ended current-mode circuit for an inter-chip asynchronous communication link. APCCAS Akira Mochizuki, Hirokatsu Shirahama, Naoya Onizawa, Takahiro Hanyu
2014	—	`conf`	Soft-Delay-Error Evaluation in Content-Addressable Memory. ISMVL Naoya Onizawa, Shoun Matsunaga, Noboru Sakimura, Ryusuke Nebashi, Tadahiko Sugibayashi, Takahiro Hanyu
2014	J	`jnl`	Soft-error tolerant transistor/magnetic-tunnel-junction hybrid non-volatile C-element. IEICE Electron. Express Naoya Onizawa, Takahiro Hanyu
2014	—	`conf`	Variation-Effect Analysis of MTJ-Based Multiple-Valued Programmable Resistors. ISMVL Masanori Natsui, Takahiro Hanyu
2013	J	`jnl`	A 1 Mb Nonvolatile Embedded Memory Using 4T2MTJ Cell With 32 b Fine-Grained Power Gating Scheme. IEEE J. Solid State Circuits Takashi Ohsawa, Hiroki Koike, Sadahiko Miura, Hiroaki Honjo, Keizo Kinoshita, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh
2013	—	`conf`	A Low-Energy Variation-Tolerant Asynchronous TCAM for Network Intrusion Detection Systems. ASYNC Naoya Onizawa, Warren J. Gross, Takahiro Hanyu
2013	—	`conf`	Accurate and High-Speed Asynchronous Network-on-Chip Simulation Using Physical Wire-Delay Information. ISMVL Takahiro Hanyu, Yuma Watanabe, Atsushi Matsumoto
2013	C	`conf`	Challenge of MTJ/MOS-hybrid logic-in-memory architecture for nonvolatile VLSI processor. ISCAS Takahiro Hanyu
2013	—	`conf`	Design and Evaluation of a Differential Switching Gate for Low-Voltage Applications. ISMVL Masanori Natsui, Kiyohiro Kashiuchi, Takahiro Hanyu
2013	J	`jnl`	Design of Process-Variation-Resilient Analog Basic Components Using Magnetic-Tunnel-Junction Devices. J. Multiple Valued Log. Soft Comput. Masanori Natsui, Takahiro Hanyu
2013	J	`jnl`	Fabrication of a magnetic tunnel junction-based 240-tile nonvolatile field-programmable gate array chip skipping wasted write operations for greedy power-reduced logic applications. IEICE Electron. Express Daisuke Suzuki, Masanori Natsui, Akira Mochizuki, Sadahiko Miura, Hiroaki Honjo, Keizo Kinoshita, Hideo Sato, Shoji Ikeda, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu
2013	J	`jnl`	High-throughput CAM based on a synchronous overlapped search scheme. IEICE Electron. Express Naoya Onizawa, Shoun Matsunaga, Vincent C. Gaudet, Warren J. Gross, Takahiro Hanyu
2013	—	`conf`	Lowering Error Floors in Stochastic Decoding of LDPC Codes Based on Wire-Delay Dependent Asynchronous Updating. ISMVL Naoya Onizawa, Warren J. Gross, Takahiro Hanyu, Vincent C. Gaudet
2013	C	`conf`	MTJ/MOS-hybrid logic-circuit design flow for nonvolatile logic-in-memory LSI. ISCAS Masanori Natsui, Takahiro Hanyu, Noboru Sakimura, Tadahiko Sugibayashi
2013	—	`conf`	Nonvolatile logic-in-memory array processor in 90nm MTJ/MOS achieving 75% leakage reduction using cycle-based power gating. ISSCC Masanori Natsui, Daisuke Suzuki, Noboru Sakimura, Ryusuke Nebashi, Yukihide Tsuji, Ayuka Morioka, Tadahiko Sugibayashi, Sadahiko Miura, Hiroaki Honjo, Keizo Kinoshita, Shoji Ikeda, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu
2013	J	`jnl`	Open-Fault Resilient Multiple-Valued Codes for Reliable Asynchronous Global Communication Links. IEICE Trans. Inf. Syst. Naoya Onizawa, Atsushi Matsumoto, Takahiro Hanyu
2012	—	`conf`	1Mb 4T-2MTJ nonvolatile STT-RAM for embedded memories using 32b fine-grained power gating technique with 1.0ns/200ps wake-up/power-off times. VLSIC Takashi Ohsawa, Hiroki Koike, Sadahiko Miura, Hiroaki Honjo, Keiichi Tokutome, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh
2012	—	`conf`	A 3.14 um VLSIC Shoun Matsunaga, Sadahiko Miura, Hiroaki Honjou, Keizo Kinoshita, Shoji Ikeda, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu
2012	—	`conf`	Area-efficient LUT circuit design based on asymmetry of MTJ's current switching for a nonvolatile FPGA. MWSCAS Daisuke Suzuki, Masanori Natsui, Takahiro Hanyu
2012	—	`conf`	Asynchronous Stochastic Decoding of Low-Density Parity-Check Codes. ISMVL Naoya Onizawa, Vincent C. Gaudet, Takahiro Hanyu, Warren J. Gross
2012	—	`conf`	Building Blocks to Use in Innovative Non-volatile FPGA Architecture Based on MTJs. ISVLSI Luca Montesi, Zeljko Zilic, Takahiro Hanyu, Daisuke Suzuki
2012	—	`conf`	Clockless Stochastic Decoding of Low-Density Parity-Check Codes. SiPS Naoya Onizawa, Warren J. Gross, Takahiro Hanyu, Vincent C. Gaudet
2012	—	`conf`	Fine-grained power-gating scheme of a nonvolatile logic-in-memory circuit for low-power motion-vector extraction. NEWCAS Magdalena Sihotang, Shoun Matsunaga, Takahiro Hanyu
2012	—	`conf`	High-Throughput Low-Energy Content-Addressable Memory Based on Self-Timed Overlapped Search Mechanism. ASYNC Naoya Onizawa, Shoun Matsunaga, Vincent C. Gaudet, Takahiro Hanyu
2012	C	`conf`	High-speed simulator including accurate MTJ models for spintronics integrated circuit design. ISCAS Noboru Sakimura, Ryusuke Nebashi, Yukihide Tsuji, Hiroaki Honjo, Tadahiko Sugibayashi, Hiroki Koike, Takashi Ohsawa, Shunsuke Fukami, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh
2012	—	`conf`	Implementation of a perpendicular MTJ-based read-disturb-tolerant 2T-2R nonvolatile TCAM based on a reversed current reading scheme. ASP-DAC Shoun Matsunaga, Masanori Natsui, Shoji Ikeda, Katsuya Miura, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu
2012	J	`jnl`	Long-Range Asynchronous On-Chip Link Based on Multiple-Valued Single-Track Signaling. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Naoya Onizawa, Atsushi Matsumoto, Takahiro Hanyu
2012	J	`jnl`	Low-Energy Pipelined Multiple-Valued Current-Mode Circuit Based on Current-Level Control Technique. J. Multiple Valued Log. Soft Comput. Masanori Natsui, Takashi Arimitsu, Takahiro Hanyu
2012	C	`conf`	Multi-chip NoCs for Automotive Applications. PRDC Tomohiro Yoneda, Masashi Imai, Naoya Onizawa, Atsushi Matsumoto, Takahiro Hanyu
2012	—	`conf`	Process-Variation-Resilient OTA Using MTJ-based Multi-level Resistance Control. ISMVL Masanori Natsui, Takaaki Nagashima, Takahiro Hanyu
2012	—	`conf`	Quaternary 1T-2MTJ Cell Circuit for a High-Density and a High-Throughput Nonvolatile Bit-Serial CAM. ISMVL Shoun Matsunaga, Takahiro Hanyu
2012	—	`conf`	Scalable serial-configuration scheme for MTJ/MOS-hybrid variation-resilient VLSI system. NEWCAS Masanori Natsui, Takahiro Hanyu
2012	—	`conf`	Systematic Coding Schemes for Low-Power Multiple-Valued Current-Mode Asynchronous Communication Links. ISMVL Atsushi Matsumoto, Naoya Onizawa, Takahiro Hanyu
2012	C	`conf`	Variation-resilient current-mode logic circuit design using MTJ devices. ISCAS YoungKeun Kim, Masanori Natsui, Takahiro Hanyu
2011	C	`conf`	Adjacent-State monitoring based fine-grained power-gating scheme for a low-power asynchronous pipelined system. ISCAS Takao Kawano, Naoya Onizawa, Atsushi Matsumoto, Takahiro Hanyu
2011	—	`conf`	Complementary Multiple-Valued Encoding Scheme for Interconnect-Fault-Resilient Bidirectional Asynchronous Links. ISMVL Atsushi Matsumoto, Naoya Onizawa, Takahiro Hanyu
2011	—	`conf`	Design of a Low-Energy Nonvolatile Fully-Parallel Ternary CAM Using a Two-Level Segmented Match-Line Scheme. ISMVL Shoun Matsunaga, Akira Katsumata, Masanori Natsui, Takahiro Hanyu
2011	J	`jnl`	Design of an 8-nsec 72-bit-Parallel-Search Content-Addressable Memory Using a Phase-Change Device. IEICE Trans. Electron. Satoru Hanzawa, Takahiro Hanyu
2011	—	`conf`	Instant power-on nonvolatile FPGA based on MTJ/MOS-hybrid circuitry. ACM Great Lakes Symposium on VLSI Takahiro Hanyu
2011	A	`conf`	Interconnect-fault-resilient delay-insensitive asynchronous communication link based on current-flow monitoring. DATE Naoya Onizawa, Atsushi Matsumoto, Takahiro Hanyu
2011	J	`jnl`	Low-Energy Asynchronous Interleaver for Clockless Fully Parallel LDPC Decoding. IEEE Trans. Circuits Syst. I Regul. Pap. Naoya Onizawa, Vincent C. Gaudet, Takahiro Hanyu
2010	—	`conf`	Accurate Asynchronous Network-on-Chip Simulation Based on a Delay-Aware Model. ISVLSI Naoya Onizawa, Tomoyoshi Funazaki, Atsushi Matsumoto, Takahiro Hanyu
2010	—	`conf`	Accurate Asynchronous Network-on-Chip Simulation Based on a Delay-Aware Model. ISVLSI (Selected papers) Naoya Onizawa, Tomoyoshi Funazaki, Atsushi Matsumoto, Takahiro Hanyu
2010	J	`jnl`	Design of High-Throughput Fully Parallel LDPC Decoders Based on Wire Partitioning. IEEE Trans. Very Large Scale Integr. Syst. Naoya Onizawa, Takahiro Hanyu, Vincent C. Gaudet
2010	J	`jnl`	Energy-Aware Multiple-Valued Current-Mode Sequential Circuits Using a Completion-Detection Scheme. IEICE Trans. Inf. Syst. Hirokatsu Shirahama, Takashi Matsuura, Masanori Natsui, Takahiro Hanyu
2010	C	`conf`	High-throughput protocol converter based on an independent encoding/decoding scheme for asynchronous Network-on-Chip. ISCAS Naoya Onizawa, Takahiro Hanyu
2010	J	`jnl`	Highly Reliable Multiple-Valued One-Phase Signalling for an Asynchronous On-Chip Communication Link. IEICE Trans. Inf. Syst. Naoya Onizawa, Takahiro Hanyu
2010	—	`conf`	Low-Energy Pipelined Multiple-Valued Current-Mode Circuit with 8-Level Static Current-Source Control. ISMVL Masanori Natsui, Takashi Arimitsu, Takahiro Hanyu
2010	—	`conf`	One-Color Two-Phase Asynchronous Communication Links Based on Multiple-Valued Simultaneous Control. ISMVL Atsushi Matsumoto, Naoya Onizawa, Takahiro Hanyu
2010	Misc	`conf`	Special session 8B: New topic MOS/MTJ-hybrid circuit with nonvolatile logic-in-memory architecture and its impact. VTS Takahiro Hanyu
2010	J	`jnl`	Study of the DC Performance of Fabricated Magnetic Tunnel Junction Integrated on Back-End Metal Line of CMOS Circuits. IEICE Trans. Electron. Fumitaka Iga, Masashi Kamiyanagi, Shoji Ikeda, Katsuya Miura, Jun Hayakawa, Haruhiro Hasegawa, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh
2010	J	`jnl`	Transient Characteristic of Fabricated Magnetic Tunnel Junction (MTJ) Programmed with CMOS Circuit. IEICE Trans. Electron. Masashi Kamiyanagi, Fumitaka Iga, Shoji Ikeda, Katsuya Miura, Jun Hayakawa, Haruhiro Hasegawa, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh
2009	J	`jnl`	High-Throughput Bit-Serial LDPC Decoder LSI Based on Multiple-Valued Asynchronous Interleaving. IEICE Trans. Electron. Naoya Onizawa, Takahiro Hanyu, Vincent C. Gaudet
2009	C	`conf`	High-performance Asynchronous Intra-chip Communication Link based on a Multiple-valued Current-mode Single-track Scheme. ISCAS Yo Ohtake, Naoya Onizawa, Takahiro Hanyu
2009	A	`conf`	MTJ-based nonvolatile logic-in-memory circuit, future prospects and issues. DATE Shoun Matsunaga, Jun Hayakawa, Shoji Ikeda, Katsuya Miura, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu
2009	—	`conf`	Robust Multiple-Valued Current-Mode Circuit Components Based on Adaptive Reference-Voltage Control. ISMVL Naoya Onizawa, Takahiro Hanyu
2009	—	`conf`	Timing-Variation-Aware Multiple-Valued Current-Mode Circuit for a Low-Power Pipelined System. ISMVL Takashi Matsuura, Hirokatsu Shirahama, Masanori Natsui, Takahiro Hanyu
2008	—	`conf`	Design of High-Performance Quaternary Adders Based on Output-Generator Sharing. ISMVL Hirokatsu Shirahama, Takahiro Hanyu
2008	—	`conf`	High-Speed Timing Verification Scheme Using Delay Tables for a Large-Scaled Multiple-Valued Current-Mode Circuit. ISMVL Tasuku Nagai, Naoya Onizawa, Takahiro Hanyu
2008	J	`jnl`	Highly Reliable Multiple-Valued Current-Mode Comparator Based on Active-Load Dual-Rail Operation. IEICE Trans. Electron. Masatomo Miura, Takahiro Hanyu
2008	J	`jnl`	Power-Aware Asynchronous Peer-to-Peer Duplex Communication System Based on Multiple-Valued One-Phase Signaling. IEICE Trans. Electron. Kazuyasu Mizusawa, Naoya Onizawa, Takahiro Hanyu
2008	—	`conf`	Vth-Variation Compensation of Multiple-Valued Current-Mode Circuit Using TMR Devices. ISMVL Akihiro Hirosaki, Masatomo Miura, Atsushi Matsumoto, Takahiro Hanyu
2007	—	`conf`	Asynchronous Peer-to-Peer Simplex/Duplex-Compatible Communication System Using a One-Phase Signaling Scheme. ISMVL Tomohiro Takahashi, Kazuyasu Mizusawa, Takahiro Hanyu
2007	J	`jnl`	Design and Evaluation of a 54 x 54-bit Multiplier Based on Differential-Pair Circuitry. IEICE Trans. Electron. Akira Mochizuki, Hirokatsu Shirahama, Takahiro Hanyu
2007	—	`conf`	Design of a Processing Element Based on Quaternary Differential Logic for a Multi-Core SIMD Processor. ISMVL Hirokatsu Shirahama, Akira Mochizuki, Takahiro Hanyu, Masami Nakajima, Kazutami Arimoto
2007	—	`conf`	High-Performance Multiple-Valued Comparator Based on Active-Load Dual-Rail Differential Logic for Crosstalk-Noise Reduction. ISMVL Akira Mochizuki, Masatomo Miura, Takahiro Hanyu
2007	—	`conf`	Implementation of a Standby-Power-Free CAM Based on Complementary Ferroelectric-Capacitor Logic. ASP-DAC Shoun Matsunaga, Takahiro Hanyu, Hiromitsu Kimura, Takashi Nakamura, Hidemi Takasu
2006	J	`jnl`	Design and Evaluation of a NULL-Convention Circuit Based on Dual-Rail Current-Mode Differential Logic. IEICE Trans. Electron. Naoya Onizawa, Takahiro Hanyu
2006	J	`jnl`	Design of a Low-Power Quaternary Flip-Flop Based on Dynamic Differential Logic. IEICE Trans. Electron. Akira Mochizuki, Hirokatsu Shirahama, Takahiro Hanyu
2006	—	`conf`	Design of a Microprocessor Datapath Using Four-Valued Differential-Pair Circuits. ISMVL Akira Mochizuki, Takeshi Kitamura, Hirokatsu Shirahama, Takahiro Hanyu
2006	—	`conf`	Highly reliable Multiple-Valued Circuit Based on Dual-Rail Differential Logic. ISMVL Akira Mochizuki, Takahiro Hanyu
2006	J	`jnl`	Implementation of a High-Speed Asynchronous Data-Transfer Chip Based on Multiple-Valued Current-Signal Multiplexing. IEICE Trans. Electron. Tomohiro Takahashi, Takahiro Hanyu
2006	J	`jnl`	Special Section on Novel Device Architectures and System Integration Technologies. IEICE Trans. Electron. Takahiro Hanyu
2005	J	`jnl`	Control Signal Multiplexing Based Asynchronous Data Transfer Scheme Using Multiple-Valued Bidirectional Current-Mode Circuits. J. Multiple Valued Log. Soft Comput. Tomohiro Takahashi, Takahiro Hanyu
2005	J	`jnl`	Design of a Low-Power Multiple-Valued Integrated Circuit Based on Dynamic Source-Coupled Logic. J. Multiple Valued Log. Soft Comput. Akira Mochizuki, Takahiro Hanyu, Michitaka Kameyama
2005	J	`jnl`	Logic-in-Memory VLSI circuit for Fully Parallel Nearest Pattern Matching Based on Floating-Gate-MOS Pass-Transistor Logic. J. Multiple Valued Log. Soft Comput. Takahiro Hanyu, Shunichi Kaeriyama, Michitaka Kameyama
2005	—	`conf`	Multiple-Valued Duplex Asynchronous Data Transfer Scheme for Interleaving in LDPC Decoders. ISMVL Naoya Onizawa, Akira Mochizuki, Takahiro Hanyu
2005	J	`jnl`	Multiple-Valued Logic as a New Computing Paradigm - A Brief Survey of Higuchi's Researchon Multiple-Valued Logic. J. Multiple Valued Log. Soft Comput. Michitaka Kameyama, Takahiro Hanyu, Takafumi Aoki
2005	J	`jnl`	TMR-Based Logic-in-Memory Circuit for Low-Power VLSI. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Akira Mochizuki, Hiromitsu Kimura, Mitsuru Ibuki, Takahiro Hanyu
2004	—	`conf`	A Study of Multiple-Valued Magnetoresistive RAM (MRAM) Using Binary MTJ Devices. ISMVL Hiromitsu Kimura, Kostas Pagiamtzis, Ali Sheikholeslami, Takahiro Hanyu
2004	J	`jnl`	Complementary ferroelectric-capacitor logic for low-power logic-in-memory VLSI. IEEE J. Solid State Circuits Hiromitsu Kimura, Takahiro Hanyu, Michitaka Kameyama, Yoshikazu Fujimori, Takashi Nakamura, Hidemi Takasu
2004	—	`conf`	Intra-Chip Address-Presetting Data-Transfer Scheme Using Four-Valued Encoding. ISMVL Akira Mochizuki, Takashi Takeuchi, Takahiro Hanyu
2004	—	`conf`	Multiple-Valued Multiple-Rail Encoding Scheme for Low-Power Asynchronous Communication. ISMVL Tomohiro Takahashi, Takahiro Hanyu
2003	—	`conf`	Bidirectional Data Transfer Based Asynchronous VLSI System Using Multiple-Valued Current Mode Logic. ISMVL Takahiro Hanyu, Tomohiro Takahashi, Michitaka Kameyama
2003	—	`conf`	Multiple-Valued Dynamic Source-Coupled Logic. ISMVL Takahiro Hanyu, Akira Mochizuki, Michitaka Kameyama
2003	J	`jnl`	Multiple-Valued Logic-in-Memory VLSI Using MFSFETs and its Applications. J. Multiple Valued Log. Soft Comput. Hiromitsu Kimura, Takahiro Hanyu, Michitaka Kameyama
2003	J	`jnl`	Optimal Design of a Dual-Rail Multiple-Valued Current-Mode Integrated Circuit Based on Voltage Swing Minimization. J. Multiple Valued Log. Soft Comput. Tsukasa Ike, Takahiro Hanyu, Michitaka Kameyama
2002	—	`conf`	Fully Source-Coupled Logic Based Multiple-Valued VLSI. ISMVL Tsukasa Ike, Takahiro Hanyu, Michitaka Kameyama
2002	—	`conf`	Multiple-Valued Logic-in-Memory VLSI Based on Ferroelectric Capacitor Storage and Charge Addition. ISMVL Hiromitsu Kimura, Takahiro Hanyu, Michitaka Kameyama
2001	—	`conf`	Challenge of a Multiple-Valued Technology in Recent Deep-Submicron VLSI. ISMVL Takahiro Hanyu
2001	—	`conf`	Dual-Rail Multiple-Valued Current-Mode VLSI with Biasing Current Sources. ISMVL Tsukasa Ike, Takahiro Hanyu, Michitaka Kameyama
2001	—	`conf`	Multiple-Valued Mask-Programmable Logic Array Using One-Transistor Universal-Literal Circuits. ISMVL Takahiro Hanyu, Michitaka Kameyama, Katsuhiko Shimabukuro, Chotei Zukeran
2000	—	`conf`	Arithmetic-Oriented Multiple-Valued Logic-in-Memory VLSI Based on Current-Mode Logic. ISMVL Shunichi Kaeriyama, Takahiro Hanyu, Michitaka Kameyama
2000	—	`conf`	DRAM-Cell-Based Multiple-Valued Logic-in-Memory VLSI with Charge Addition and Charge Storage. ISMVL Takahiro Hanyu, Hiromitsu Kimura, Michitaka Kameyama
2000	C	`conf`	Integration of asynchronous and self-checking multiple-valued current-mode circuits based on dual-rail differential logic. PRDC Takahiro Hanyu, Tsukasa Ike, Michitaka Kameyama
2000	—	`conf`	Low-Power Dual-Rail Multiple-Valued Current-Mode Logic Circuit Using Multiple Input-Signal Levels. ISMVL Takahiro Hanyu, Tsukasa Ike, Michitaka Kameyama
1999	—	`conf`	Multiple-Valued Content-Addressable Memory Using Metal-Ferroelectric-Semiconductor FETs. ISMVL Takahiro Hanyu, Hiromitsu Kimura, Michitaka Kameyama
1999	—	`conf`	Self-Checking Multiple-Valued Circuit Based on Dual-Rail Current-Mode Differential Logic. ISMVL Takahiro Hanyu, Tsukasa Ike, Michitaka Kameyama
1998	—	`conf`	Asynchronous Multiple-Valued VLSI System Based on Dual-Rail Current-Mode Differential Logic. ISMVL Takahiro Hanyu, Takahiro Saito, Michitaka Kameyama
1998	J	`jnl`	Design and evaluation of a digit-parallel multiple-valued content-addressable memory. Syst. Comput. Jpn. Takahiro Hanyu, Kaname Teranishi, Michitaka Kameyama
1998	—	`conf`	Multiple-Valued Floating-Gate-MOS Pass Logic and its Application to Logic-in-Memory VLSI. ISMVL Takahiro Hanyu, Kaname Teranishi, Michitaka Kameyama
1998	J	`jnl`	Optimal design of a current-mode deep-submicron multiple-valued integrated circuit and application. Syst. Comput. Jpn. Takahiro Saito, Takahiro Hanyu, Michitaka Kameyama
1997	—	`conf`	Low-power multiple-valued current-mode integrated circuit with current-source control and its application. ASP-DAC Takahiro Hanyu, Satoshi Kazama, Michitaka Kameyama
1997	—	`conf`	One-Transistor-Cell 4-Valued Universal-Literal CAM for Cellular Logic Image Processing. ISMVL Takahiro Hanyu, Manabu Arakaki, Michitaka Kameyama
1996	—	`conf`	A Multiple-Valued Ferroelectric Content-Addressable Memory. ISMVL Ali Sheikholeslami, P. Glenn Gulak, Takahiro Hanyu
1996	J	`jnl`	Design of a one-transistor-cell multiple-valued CAM. IEEE J. Solid State Circuits Takahiro Hanyu, N. Kanagawa, Michitaka Kameyama
1996	J	`jnl`	Design of a one-transistor-cell multiple-valued CAM. IEEE J. Solid State Circuits Takahiro Hanyu, Naoki Kanagawa, Michitaka Kameyama
1996	—	`conf`	Quaternary Universal-Literal CAM for Cellular Logic Image Processing. ISMVL Takahiro Hanyu, Manabu Arakaki, Michitaka Kameyama
1995	J	`jnl`	A 200 MHz pipelined multiplier using 1.5 V-supply multiple-valued MOS current-mode circuits with dual-rail source-coupled logic. IEEE J. Solid State Circuits Takahiro Hanyu, Michitaka Kameyama
1995	—	`conf`	Multiple-Valued Arithmetic Integrated Circuits Based on 1.5V-Supply Dual-Rail Source-Coupled Logic. ISMVL Takahiro Hanyu, Akira Mochizuki, Michitaka Kameyama
1995	—	`conf`	Quantum Device Model-Based Super Pass Gate for Multiple-Valued Digital Systems. ISMVL Xiaowei Deng, Takahiro Hanyu, Michitaka Kameyama
1995	J	`jnl`	Quantum-Device-Oriented Multiple-Valued Logic System Based on a Super Pass Gate. IEICE Trans. Inf. Syst. Xiaowei Deng, Takahiro Hanyu, Michitaka Kameyama
1994	—	`conf`	Multiple-Valued Current-Mode MOS Integrated Circuits Based on Dual-Rail Source-Coupled Logic. ISMVL Takahiro Hanyu, Akira Mochizuki, Michitaka Kameyama
1993	—	`conf`	A Multiple-Valued Content-Addressable Memory Using Logic-Value Conversion and Threshold Functions. ISMVL Satoshi Aragaki, Takahiro Hanyu, Tatsuo Higuchi
1992	—	`conf`	Design of a Multiple-Valued Rule-Programmable Matching VLSI Chip for Real-Time Rule-Based Systems. ISMVL Takahiro Hanyu, Kouichi Takeda, Tatsuo Higuchi
1991	—	`conf`	A Floating-Gate-MOS-Based Multiple-Valued Associative Memory. ISMVL Takahiro Hanyu, Tatsuo Higuchi
1991	—	`conf`	A Multiple-Valued Logic Artay VLSI Based on Two-Transistor Delta Literal Circuit and Its Application to Real-Time Reasoning Systems. ISMVL Takahiro Hanyu, Yasushi Kojima, Tatsuo Higuchi
1990	—	`conf`	Design of a High-Density Multiple-Valued Content-Addressable Memory Based on Floating-Gate MOS Devices. ISMVL Takahiro Hanyu, Tatsuo Higuchi
1989	J	`jnl`	Design of a Multiple-Valued Associative Memory. Syst. Comput. Jpn. Takahiro Hanyu, Tatsuo Higuchi
1989	J	`jnl`	High-density quaternary logic array chip for knowledge information processing systems. IEEE J. Solid State Circuits Takahiro Hanyu, Tatsuo Higuchi
1987	J	`jnl`	Design and implementation of an nmos image processor based on quaternary logic. Syst. Comput. Jpn. Takahiro Hanyu, Michitaka Kameyama, Tatsuo Higuchi