Tak-Kei Lam

11 papers A* 1A 3Misc 1Journal 2Unranked 4
YearRankTypeTitle / Venue / Authors
2016 — conf
Coupling reverse engineering and SAT to tackle NP-complete arithmetic circuitry verification in ∼O(# of gates).
ASP-DAC
Yi Diao, Xing Wei, Tak-Kei Lam, Yu-Liang Wu
2015 A conf
A coupling area reduction technique applying ODC shifting.
DATE
Yi Diao, Tak-Kei Lam, Xing Wei, Yu-Liang Wu
2015 A conf
A universal macro block mapping scheme for arithmetic circuits.
DATE
Xing Wei, Yi Diao, Tak-Kei Lam, Yu-Liang Wu
2014 Misc conf
Delete and Correct (DaC): An Atomic Logic Operation for Removing Any Unwanted Wire.
VLSID
Xing Wei, Tak-Kei Lam, Xiaoqing Yang, Wai-Chung Tang, Yi Diao, Yu-Liang Wu
2014 — conf
On macro-fault: a new fault model, its implications on fault tolerance and manufacturing yield.
ACM Great Lakes Symposium on VLSI
Tak-Kei Lam, Xing Wei, Wen-Ben Jone, Yi Diao, Yu-Liang Wu
2012 A conf
Almost every wire is removable: A modeling and solution for removing any circuit wire.
DATE
Xiaoqing Yang, Tak-Kei Lam, Wai-Chung Tang, Yu-Liang Wu
2012 J jnl
ECR: A Powerful and Low-Complexity Error Cancellation Rewiring Scheme.
ACM Trans. Design Autom. Electr. Syst.
Tak-Kei Lam, Wai-Chung Tang, Xiaoqing Yang, Yu-Liang Wu
2011 J jnl
On Structural Analysis and Efficiency for Graph-Based Rewiring Techniques.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Fu-Shing Chim, Tak-Kei Lam, Yu-Liang Wu, Hongbing Fan
2011 — conf
On applying erroneous clock gating conditions to further cut down power.
ASP-DAC
Tak-Kei Lam, Xiaoqing Yang, Wai-Chung Tang, Yu-Liang Wu
2010 A* conf
ECR: a low complexity generalized error cancellation rewiring scheme.
DAC
Xiaoqing Yang, Tak-Kei Lam, Yu-Liang Wu
2010 — conf
Logic synthesis for low power using clock gating and rewiring.
ACM Great Lakes Symposium on VLSI
Tak-Kei Lam, Steve Yang, Wai-Chung Tang, Yu-Liang Wu