Taiquan Wei - RankMe

13 papers A* 5Journal 6Unranked 2

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Designing Spatial Architectures for Sparse Attention: STAR Accelerator via Cross-Stage Tiling. IEEE Trans. Computers Huizheng Wang, Taiquan Wei, Hongbin Wang, Zichuan Wang, Xinru Tang, Zhiheng Yue, Shaojun Wei, Yang Hu, Shouyi Yin
2026	A*	`conf`	MoEntwine: Unleashing the Potential of Wafer-Scale Chips for Large-Scale Expert Parallel Inference. HPCA Xinru Tang, Jingxiang Hou, Dingcheng Jiang, Taiquan Wei, Jiaxin Liu, Jinyi Deng, Huizheng Wang, Qize Yang, Haoran Shang, Chao Li, Yang Hu, Shouyi Yin
2026	A*	`conf`	TEMP: A Memory Efficient Physical-Aware Tensor Partition-Mapping Framework on Wafer-Scale Chips. HPCA Huizheng Wang, Taiquan Wei, Zichuan Wang, Dingcheng Jiang, Qize Yang, Jiaxin Liu, Jingxiang Hou, Chao Li, Jinyi Deng, Yang Hu, Shouyi Yin
2026	A*	`conf`	WATOS: Efficient LLM Training Strategies and Architecture Co-Exploration for Wafer-Scale Chip. HPCA Huizheng Wang, Zichuan Wang, Hongbin Wang, Jingxiang Hou, Taiquan Wei, Chao Li, Yang Hu, Shouyi Yin
2025	J	`jnl`	BETA: A Bit-Grained Transformer Attention Accelerator With Efficient Early Termination. IEEE Trans. Circuits Syst. II Express Briefs Huizheng Wang, Hongbin Wang, Zhiheng Yue, Jingyao Liu, Taiquan Wei, Shaojun Wei, Yang Hu, Shouyi Yin
2025	J	`jnl`	Designing Spatial Architectures for Sparse Attention: STAR Accelerator via Cross-Stage Tiling. CoRR Huizheng Wang, Taiquan Wei, Hongbin Wang, Zichuan Wang, Xinru Tang, Zhiheng Yue, Shaojun Wei, Yang Hu, Shouyi Yin
2025	A*	`conf`	MCBP: A Memory-Compute Efficient LLM Inference Accelerator Leveraging Bit-Slice-enabled Sparsity and Repetitiveness. MICRO Huizheng Wang, Zichuan Wang, Zhiheng Yue, Yousheng Long, Taiquan Wei, Jianxun Yang, Yang Wang, Chao Li, Shaojun Wei, Yang Hu, Shouyi Yin
2025	J	`jnl`	MCBP: A Memory-Compute Efficient LLM Inference Accelerator Leveraging Bit-Slice-enabled Sparsity and Repetitiveness. CoRR Huizheng Wang, Zichuan Wang, Zhiheng Yue, Yousheng Long, Taiquan Wei, Jianxun Yang, Yang Wang, Chao Li, Shaojun Wei, Yang Hu, Shouyi Yin
2025	J	`jnl`	MoEntwine: Unleashing the Potential of Wafer-scale Chips for Large-scale Expert Parallel Inference. CoRR Xinru Tang, Jingxiang Hou, Dingcheng Jiang, Taiquan Wei, Jiaxin Liu, Jinyi Deng, Huizheng Wang, Qize Yang, Haoran Shang, Chao Li, Yang Hu, Shouyi Yin
2025	A*	`conf`	PD Constraint-aware Physical/Logical Topology Co-Design for Network on Wafer. ISCA Qize Yang, Taiquan Wei, Sihan Guan, Chengran Li, Haoran Shang, Jinyi Deng, Huizheng Wang, Chao Li, Lei Wang, Yan Zhang, Shouyi Yin, Yang Hu
2025	—	`conf`	Segmentation-Aware Optimization of Collective for Waferscale Chips. APPT Qize Yang, Jiaxin Liu, Taiquan Wei, Yuxin Jin, Shouyi Yin, Yang Hu
2025	—	`conf`	Spatial-Aware Orchestration of LLM Attention on Waferscale Chips. APPT Taiquan Wei, Huizheng Wang, Zichuan Wang, Shouyi Yin, Yang Hu
2025	J	`jnl`	TEMP: A Memory Efficient Physical-aware Tensor Partition-Mapping Framework on Wafer-scale Chips. CoRR Huizheng Wang, Taiquan Wei, Zichuan Wang, Dingcheng Jiang, Qize Yang, Jiaxin Liu, Jingxiang Hou, Chao Li, Jinyi Deng, Yang Hu, Shouyi Yin