Tailong Xu

16 papers Journal 10Unranked 6
YearRankTypeTitle / Venue / Authors
2025 J jnl
Analysis and Design of a Type-II Reference-Sampling PLL Using Gain-Boosting Phase Detector With Sampling Capacitor Reduction.
IEEE Trans. Circuits Syst. II Express Briefs
Tailong Xu, Haoran Li, Xi Meng, Xiangxun Zhan, Yatao Peng, Jun Yin, Shiheng Yang, Chao Fan, Zhixiang Huang, Rui Paulo Martins, Pui-In Mak
2025 J jnl
Design and Analysis of a Type-II Sampling PLL With Automatic Frequency and Phase Calibrations Achieving 0.62-μs Locking Time.
IEEE Trans. Circuits Syst. I Regul. Pap.
Jian Yang, Tailong Xu, Xi Meng, Zhenghao Li, Jun Yin, Rui Paulo Martins, Pui-In Mak, Quan Pan
2024 — conf
10.9 A 23.2-to-26GHz Sub-Sampling PLL Achieving 48.3fsrms Jitter, -253.5dB FoMJ, and 0.55μs Locking Time Based on a Function-Reused VCO-Buffer and a Type-I FLL with Rapid Phase Alignment.
ISSCC
Haoran Li, Tailong Xu, Xi Meng, Jun Yin, Rui Paulo Martins, Pui-In Mak
2024 J jnl
A 16-MHz Crystal Oscillator With 17.5- μ s Start-Up Time Under 10
IEEE J. Solid State Circuits
Zixuan Wang, Xin Wang, Ka-Meng Lei, Wenjing Zhang, Yunjin Yin, Tailong Xu, Zhikuang Cai, Yufeng Guo, Pui-In Mak
2024 J jnl
A 23.2-to-26-GHz Low-Jitter Fast-Locking Sub-Sampling PLL Based on a Function-Reused VCO-Buffer and a Type-I FLL With Rapid Phase Alignment.
IEEE J. Solid State Circuits
Haoran Li, Tailong Xu, Xi Meng, Jun Yin, Rui Paulo Martins, Pui-In Mak
2024 — conf
A 6.0-to-6.9GHz 99fsrms-Jitter Type-II Sampling PLL with Automatic Frequency and Phase Calibration Method Achieving 0.62μs Locking Time in 28nm CMOS.
CICC
Jian Yang, Tailong Xu, Xi Meng, Zhenghao Li, Jun Yin, Pui-In Mak, Rui Paulo Martins, Quan Pan
2023 — conf
A 16MHz X0 with 17.5μs Startup Time Under 10
ISSCC
Zhikuang Cai, Xin Wang, Zixuan Wang, Yunjin Yin, Wenjing Zhang, Tailong Xu, Yufeng Guo
2023 J jnl
On the DC-Settling Process of the Pierce Crystal Oscillator in Start-Up.
IEEE Trans. Circuits Syst. II Express Briefs
Zehao Zhang, Shiheng Yang, Yueduo Liu, Zihao Zhu, Jiahui Lin, Rongxin Bao, Tailong Xu, Zhizhan Yang, Mingkang Zhang, Jiaxin Liu, Xiong Zhou, Jun Yin, Pui-In Mak, Qiang Li
2022 J jnl
A 6-to-7.5-GHz 54-fs
IEEE Trans. Circuits Syst. I Regul. Pap.
Tailong Xu, Shenke Zhong, Jun Yin, Pui-In Mak, Rui Paulo Martins
2021 J jnl
A 600-μm² Ring-VCO-Based Hybrid PLL Using a 30-μW Charge-Sharing Integrator in 28-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs
Shiheng Yang, Jun Yin, Tailong Xu, Taimo Yi, Pui-In Mak, Qiang Li, Rui Paulo Martins
2020 J jnl
Blockchain Enabled Tracking of Physician Burnout and Stressors During the COVID-19 Pandemic.
Frontiers Blockchain
Vikram Dhillon, Tailong Xu, Chirag Parikh
2017 — conf
A harmonic-free cell-based all-digital delay-locked loop for die-to-die clock synchronization of 3-D IC.
ASICON
Tailong Xu, Feng Xue, Zhikuang Cai, Xinning Liu, Shuo Meng
2016 J jnl
Design and implementation of elastic buffer for Universal Serial Bus 3.0.
IEICE Electron. Express
Hong Chang, Te Peng, Daoming Ke, Tailong Xu, Jian Meng
2013 J jnl
A wide-range and ultra fast-locking all-digital SAR DLL without harmonic-locking.
IEICE Electron. Express
Zhikuang Cai, Tailong Xu, Haiyan Sun, Longxing Shi
2013 — conf
Dynamic thermal management for multi-core microprocessors considering transient thermal effects.
ASP-DAC
Zao Liu, Tailong Xu, Sheldon X.-D. Tan, Hai Wang
2012 — conf
Transient analysis of large linear dynamic networks on hybrid GPU-multicore platforms.
NEWCAS
Xuexin Liu, Sheldon X.-D. Tan, Zao Liu, Hai Wang, Tailong Xu