Taigon Song - RankMe

45 papers A* 4A 6C 2Journal 18Unranked 15

Year	Rank	Type	Title / Venue / Authors
2026	A*	`conf`	NPUWattch: ML-Based Power, Area, and Timing Modeling for Neural Accelerators. HPCA Sehyeon Kim, Minkwan Kim, Chanho Park, Hanmok Park, Seonghoon Kim, Taigon Song, William J. Song
2025	J	`jnl`	An RTL-Based General Synthesis Methodology for Device-Independent Ternary Logic Circuits. IEEE Access Hanmok Park, Seonghoon Kim, Sunmean Kim, Taigon Song
2025	J	`jnl`	Ternary Toward Binary: Circuit-Level Implementation of Ternary Logic Using Depletion-Mode and Conventional MOSFETs. IEEE Access Hyundong Lee, Seonghoon Kim, Jongbeom Kim, Jaehoon Jeong, Jeonggyu Yang, Taigon Song
2025	J	`jnl`	WACA-UNet: Weakness-Aware Channel Attention for Static IR Drop Prediction in Integrated Circuit Design. CoRR Youngmin Seo, Yunhyeong Kwon, Younghun Park, HwiRyong Kim, Seungho Eum, Jinha Kim, Taigon Song, Juho Kim, Unsang Park
2024	J	`jnl`	Design Technology Co-Optimization and Time-Efficient Verification for Enhanced Pin Accessibility in the Post-3-nm Node. IEEE Access Jaehoon Jeong, Yunjeong Shin, Hyundong Lee, JongHyun Ko, Jongbeom Kim, Taigon Song
2024	C	`conf`	FS2K: A Forksheet FET Technology Library and a Study of VLSI Prediction for 2nm and Beyond. ISCAS Yunjeong Shin, Daehyeok Park, Dohun Koh, Dongryul Heo, Jieun Park, Hyundong Lee, Jongbeom Kim, Hyunsoo Lee, Taigon Song
2024	A	`conf`	Reinforcement Learning-Based Optimization of Back-Side Power Delivery Networks in VLSI Design for IR -Drop Reduction. DATE Seungmin Woo, Hyunsoo Lee, Yunjeong Shin, Minseok Han, Yunjeong Go, Jongbeom Kim, Hyundong Lee, Hyunwoo Kim, Taigon Song
2024	J	`jnl`	Robust Hardware Trojan Detection Method by Unsupervised Learning of Electromagnetic Signals. IEEE Trans. Very Large Scale Integr. Syst. Daehyeon Lee, Junghee Lee, Younggiu Jung, Janghyuk Kauh, Taigon Song
2023	—	`conf`	A Compact Q-Learning-Based Standard Cell Layout Compiler for 3nm GAAFET and Beyond. ISOCC MinSeung Shin, Jongbeom Kim, Yunjeong Shin, Taigon Song
2023	—	`conf`	Cache Register Sharing Structure for Channel-level Near-memory Processing in NAND Flash Memory. ISQED Hyunwoo Kim, Hyundong Lee, Jongbeom Kim, Yunjeong Go, Seungwon Baek, Jaehong Song, Junhyeon Kim, Minyoung Jung, Hyodong Kim, Seongju Kim, Taigon Song
2023	J	`jnl`	Complementary FET (CFET) Standard Cell Design for Low Parasitics and Its Impact on VLSI Prediction at 3-nm Process. IEEE Trans. Very Large Scale Integr. Syst. Eun-Bin Park, Taigon Song
2023	J	`jnl`	Exploration of Ternary Logic Using T-CMOS for Circuit-Level Design. IEEE Trans. Circuits Syst. I Regul. Pap. JongHyun Ko, Jongbeom Kim, TaeGam Jeong, Jaehoon Jeong, Taigon Song
2023	—	`conf`	HFGCN: High-speed and Fully-optimized GCN Accelerator. ISQED Minseok Han, Jiwan Kim, DongGeon Kim, Hyunuk Jeong, Gilho Jung, Myeongwon Oh, Hyundong Lee, Yunjeong Go, Hyunwoo Kim, Jongbeom Kim, Taigon Song
2023	—	`conf`	High-throughput PIM (Processing in-Memory) for DRAM using Bank-level Pipelined Architecture. ISOCC Hyunsoo Lee, Hyundong Lee, MinSeung Shin, Gyuri Shin, Sumin Jeon, Taigon Song
2023	J	`jnl`	NS3K: A 3-nm Nanosheet FET Standard Cell Library Development and its Impact. IEEE Trans. Very Large Scale Integr. Syst. Taehak Kim, Jaehoon Jeong, Seungmin Woo, Jeonggyu Yang, Hyunwoo Kim, Ahyeon Nam, Changdong Lee, Jinmin Seo, Minji Kim, Siwon Ryu, Yoonju Oh, Taigon Song
2023	J	`jnl`	T IEEE Trans. Circuits Syst. I Regul. Pap. Jongbeom Kim, Hyundong Lee, JongHyun Ko, Bongjun Kim, Taigon Song
2022	—	`conf`	A Convenient Implementation of the Ternary Logic: Using Anti-Ambipolar Transistors and PMOS Based on Printed Carbon Nanotubes. ISMVL Jongbeom Kim, Yeji Kim, Hyundong Lee, Jihyeong Yun, Hyeseung Jang, Huijeen Jin, Juhee Park, Bongjun Kim, Taigon Song
2022	—	`conf`	A Novel Processing Unit and Architecture for Process-In Memory (PIM) in NAND Flash Memory. ISOCC Hyunwoo Kim, Seungwon Baek, Jaehong Song, Taigon Song
2022	A	`conf`	A Study on Optimizing Pin Accessibility of Standard Cells in the Post-3 nm Node. ISLPED Jaehoon Jeong, JongHyun Ko, Taigon Song
2022	J	`jnl`	Circuit-Level Exploration of Ternary Logic Using Memristors and MOSFETs. IEEE Trans. Circuits Syst. I Regul. Pap. Jeonggyu Yang, Hyundong Lee, Jaehoon Jeong, Taehak Kim, Sin-Hyung Lee, Taigon Song
2022	—	`conf`	Ternary Competitive to Binary: A Novel Implementation of Ternary Logic Using Depletion-mode and Conventional MOSFETs. ISMVL Hyundong Lee, Hyeseung Jang, Jihyeong Yun, Huijeen Jin, Jongbeom Kim, Yeji Kim, Taigon Song
2021	—	`conf`	A Practical Implementation of the Ternary Logic Using Memristors and MOSFETs. ISMVL Jeonggyu Yang, Hyundong Lee, Jaehoon Jeong, Taehak Kim, Sin-Hyung Lee, Taigon Song
2021	—	`conf`	An Optimal Design Methodology of Ternary Logic in Iso-device Ternary CMOS. ISMVL JongHyun Ko, Kwanwoo Park, Suhyeong Yong, TaeGam Jeong, Taehak Kim, Taigon Song
2021	—	`conf`	An Optimized Standard Cell Design Methodology Targeting Low Parasitics and Small Area for Complementary FETs (CFETs). ISOCC Eun-Bin Park, Taigon Song
2021	C	`conf`	NS3K: A 3nm Nanosheet FET Library for VLSI Prediction in Advanced Nodes. ISCAS Taehak Kim, Jaehoon Jeong, Seungmin Woo, Jeonggyu Yang, Hyunwoo Kim, Ahyeon Nam, Changdong Lee, Jinmin Seo, Minji Kim, Siwon Ryu, Yoonju Oh, Taigon Song
2020	—	`conf`	A Prediction Scheme in Spiking Neural Network (SNN) Hardware for Ultra-low Power Consumption. ISOCC Jeonggyu Yang, Taigon Song
2020	J	`jnl`	Many-Tier Vertical GAAFET (V-FET) for Ultra-Miniaturized Standard Cell Designs Beyond 5 nm. IEEE Access Taigon Song
2017	J	`jnl`	Design Methodologies for Low-Power 3-D ICs With Advanced Tier Partitioning. IEEE Trans. Very Large Scale Integr. Syst. Moongon Jung, Taigon Song, Yarui Peng, Sung Kyu Lim
2017	A	`conf`	Transistor-level monolithic 3D standard cell layout optimization for full-chip static power integrity. ISLPED Bon Woong Ku, Taigon Song, Arthur Nieuwoudt, Sung Kyu Lim
2016	J	`jnl`	Full-Chip Signal Integrity Analysis and Optimization of 3-D ICs. IEEE Trans. Very Large Scale Integr. Syst. Taigon Song, Chang Liu, Yarui Peng, Sung Kyu Lim
2016	J	`jnl`	More Power Reduction With 3-Tier Logic-on-Logic 3-D ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Taigon Song, Shreepad Panth, Yoo-Jin Chae, Sung Kyu Lim
2015	J	`jnl`	Design and Analysis of 3D-MAPS (3D Massively Parallel Processor with Stacked Memory). IEEE Trans. Computers Daehyun Kim, Krit Athikulwongse, Michael B. Healy, Mohammad M. Hossain, Moongon Jung, Ilya Khorosh, Gokul Kumar, Young-Joon Lee, Dean L. Lewis, Tzu-Wei Lin, Chang Liu, Shreepad Panth, Mohit Pathak, Minzhen Ren, Guanhao Shen, Taigon Song, Dong Hyuk Woo, Xin Zhao, Joungho Kim, Ho Choi, Gabriel H. Loh, Hsien-Hsin S. Lee, Sung Kyu Lim
2015	J	`jnl`	Die-to-Die Parasitic Extraction Targeting Face-to-Face Bonded 3D ICs. J. Inform. and Commun. Convergence Engineering Taigon Song, Sung Kyu Lim
2015	J	`jnl`	Full-Chip Power/Performance Benefits of Carbon Nanotube-Based Circuits. J. Inform. and Commun. Convergence Engineering Taigon Song, Sung Kyu Lim
2015	A	`conf`	Full-chip Inter-die Parasitic Extraction in Face-to-Face-Bonded 3D ICs. ICCAD Yarui Peng, Taigon Song, Dusan Petranovic, Sung Kyu Lim
2015	A	`conf`	Three-Tier 3D ICs for More Power Reduction: Strategies in CAD, Design, and Bonding Selection. ICCAD Taigon Song, Shreepad Panth, Yoo-Jin Chae, Sung Kyu Lim
2014	A*	`conf`	On Enhancing Power Benefits in 3D ICs: Block Folding and Bonding Styles Perspective. DAC Moongon Jung, Taigon Song, Yang Wan, Yarui Peng, Sung Kyu Lim
2014	J	`jnl`	Silicon Effect-Aware Full-Chip Extraction and Mitigation of TSV-to-TSV Coupling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yarui Peng, Taigon Song, Dusan Petranovic, Sung Kyu Lim
2013	A*	`conf`	Full-chip multiple TSV-to-TSV coupling extraction and optimization in 3D ICs. DAC Taigon Song, Chang Liu, Yarui Peng, Sung Kyu Lim
2013	—	`conf`	How to reduce power in 3D IC designs: A case study with OpenSPARC T2 core. CICC Moongon Jung, Taigon Song, Yang Wan, Young-Joon Lee, Debabrata Mohapatra, Hong Wang, Greg Taylor, Devang Jariwala, Vijay Pitchumani, Patrick Morrow, Clair Webb, Paul Fischer, Sung Kyu Lim
2013	A	`conf`	On accurate full-chip extraction and optimization of TSV-to-TSV coupling elements in 3D ICs. ICCAD Yarui Peng, Taigon Song, Dusan Petranovic, Sung Kyu Lim
2012	—	`conf`	3D-MAPS: 3D Massively parallel processor with stacked memory. ISSCC Dae Hyun Kim, Krit Athikulwongse, Michael B. Healy, Mohammad M. Hossain, Moongon Jung, Ilya Khorosh, Gokul Kumar, Young-Joon Lee, Dean L. Lewis, Tzu-Wei Lin, Chang Liu, Shreepad Panth, Mohit Pathak, Minzhen Ren, Guanhao Shen, Taigon Song, Dong Hyuk Woo, Xin Zhao, Joungho Kim, Ho Choi, Gabriel H. Loh, Hsien-Hsin S. Lee, Sung Kyu Lim
2011	—	`conf`	Analysis of TSV-to-TSV coupling with high-impedance termination in 3D ICs. ISQED Taigon Song, Chang Liu, Dae Hyun Kim, Sung Kyu Lim, Jonghyun Cho, Joohee Kim, Junso Pak, Seungyoung Ahn, Joungho Kim, Kihyun Yoon
2011	A*	`conf`	Full-chip TSV-to-TSV coupling analysis and optimization in 3D IC. DAC Chang Liu, Taigon Song, Jonghyun Cho, Joohee Kim, Joungho Kim, Sung Kyu Lim
2011	—	`conf`	Signal integrity analysis and optimization for 3D ICs. ISQED Chang Liu, Taigon Song, Sung Kyu Lim