Tai-Cheng Lee

73 papers A 1C 4Journal 31Unranked 37
YearRankTypeTitle / Venue / Authors
2025 J jnl
A Calibration-Free 12-Bit 1.5-GS/s Pipelined ADC With Merged Sub-ADC Quantization Technique.
IEEE Trans. Circuits Syst. II Express Briefs
Chun-Tse Su, Chao-Yen Hsu, Tai-Cheng Lee
2025 J jnl
A Calibration-Free 9.3-ENOB 1-GS/s Pipelined ADC With PVT-Insensitive Nested Ring Amplifiers.
IEEE Trans. Circuits Syst. II Express Briefs
Chao-Yen Hsu, Tai-Cheng Lee
2025 C conf
A Pipelined-SAR ADC with a Compensation-Free Two-Stage Amplifier.
ISCAS
Chun-Tse Su, Chao-Yen Hsu, Shih-Jie Huang, Tai-Cheng Lee
2024 J jnl
A 511-μW 89-dB-SNDR Asynchronous SAR-ISDM ADC With Noise Shaping Dynamic Amplifier and Time-Domain Noise-Slicing Technique.
IEEE J. Solid State Circuits
Hao-Hsuan Chang, Ci-Ren Chen, Tai-Cheng Lee
2024 J jnl
A Sub-Baud-Rate Wireline Receiver With One-Tap DFE.
IEEE J. Solid State Circuits
Yu-Hong Yang, Tai-Cheng Lee
2024 — conf
An 800-MS/s 10b Pipelined ADC with Floating Ring Amplifiers.
ISOCC
Chao-Yen Hsu, Mu-Heng Pi, Tai-Cheng Lee
2024 J jnl
An 800-MS/s 8.2-ENOB TDC-Assisted Pipelined-SAR ADC With Parallel Conversion.
IEEE Trans. Circuits Syst. II Express Briefs
Shao-Yu Wang, Tai-Cheng Lee
2023 J jnl
A 0.9-V 50-MS/s 67.3-dB-SNDR SAR-ISDM ADC With an Oscillator-Based Integrator.
IEEE Trans. Circuits Syst. II Express Briefs
Yen-Chun Chan, Che-Wei Chang, Tai-Cheng Lee
2023 J jnl
A 6.0-11.0 Gb/s Reference-Less Sub-Baud-Rate Linear CDR With Wide-Range Frequency Acquisition Technique.
IEEE Trans. Circuits Syst. II Express Briefs
Yu-Hong Yang, Mou Tzou, Tai-Cheng Lee
2022 — conf
A Reinforcement Learning Agent for Obstacle-Avoiding Rectilinear Steiner Tree Construction.
ISPD
Po-Yan Chen, Bing-Ting Ke, Tai-Cheng Lee, I-Ching Tsai, Tai-Wei Kung, Li-Yi Lin, En-Cheng Liu, Yun-Chih Chang, Yih-Lang Li, Mango C.-T. Chao
2022 J jnl
A Single-Channel 1-GS/s 7.48-ENOB Parallel Conversion Pipelined SAR ADC With a Varactor-Based Residue Amplifier.
IEEE Trans. Circuits Syst. II Express Briefs
Hao-Hsuan Chang, Tung-Cheng Lin, Tai-Cheng Lee
2022 C conf
A Type-3 FMCW Radar Synthesizer with Wide Frequency Modulation Bandwidth.
ISCAS
Cheng-Tang Chen, Yu-Hong Yang, Tai-Cheng Lee
2022 — conf
An Asynchronous Zero-Crossing-Based Incremental Delta-Sigma Converter.
VLSI-DAT
Yen-Po Lai, Hao-Hsuan Chang, Tai-Cheng Lee
2022 — conf
Path-Based Pre-Routing Timing Prediction for Modern Very Large-Scale Integration Designs.
ISQED
Li-Wei Chen, Yao-Nien Sui, Tai-Cheng Lee, Yih-Lang Li, Mango C.-T. Chao, I-Ching Tsai, Tai-Wei Kung, En-Cheng Liu, Yun-Chih Chang
2020 A conf
/TPlace: Machine Learning-Based Delay-Aware Transistor Placement for Standard Cell Synthesis.
ICCAD
Tai-Cheng Lee, Cheng-Yen Yang, Yih-Lang Li
2020 — conf
25.6 A 5.25GHz Subsampling PLL with a VCO-Phase-Noise Suppression Technique.
ISSCC
Hsiu-Hsien Ting, Tai-Cheng Lee
2020 C conf
A 5 GHz Outer-Loop Phase Noise Filter with Delay-Sampling Technique.
ISCAS
Kun-Ruei Li, Wei-Sung Chang, Tai-Cheng Lee
2020 — conf
Analysis and Design of a Self-Charged Crystal Oscillator with Pulse Regulating Feedback Loop.
VLSI-DAT
Hsiang-Chun Cheng, Yu-Hong Yang, Tai-Cheng Lee
2019 — conf
A SAR-Assisted Continuous-Time Incremental ΣΔ ADC With First-Order Noise Coupling.
ASICON
Yu-Lun Hsieh, Tai-Cheng Lee
2019 J jnl
Incremental Timing-Driven Placement With Approximated Signoff Wire Delay and Regression-Based Cell Delay.
IEEE Trans. Very Large Scale Integr. Syst.
Tai-Cheng Lee, Yih-Lang Li
2018 J jnl
A 10-bit 2.6-GS/s Time-Interleaved SAR ADC With a Digital-Mixing Timing-Skew Calibration Technique.
IEEE J. Solid State Circuits
Chin-Yu Lin, Yen-Hsin Wei, Tai-Cheng Lee
2018 — conf
F2: FinFETs & FDSOI - A mixed signal circuit designer's perspective.
ISSCC
Venkatesh Srinivasan, Stephane Le Tuai, Tai-Cheng Lee
2017 — conf
A 10-Gb/s equalizer with digital adaptation.
ISOCC
Jui-Cheng Hsiao, Dai-En Jhou, Tai-Cheng Lee
2017 — conf
An energy-efficient self-charged crystal oscillator with a quadrature-phase shifter technique.
A-SSCC
Wei-Sung Chang, Dai-En Jhou, Yu-Hong Yang, Tai-Cheng Lee
2017 — conf
Few-mode 850-nm VCSEL chip with direct 16-QAM OFDM encoding at 80-Gbit/s for 100-m OM4 MMF link.
OFC
Hsuan-Yun Kao, Cheng-Ting Tsai, Chun-Yen Pong, Shan-Fong Liang, Zu-Kai Weng, Yu-Chieh Chi, Hao-Chung Kuo, Jian Jang Huang, Tai-Cheng Lee, Tien-Tsorng Shih, Jau-Ji Jou, Wood-Hi Cheng, Chao-Hsin Wu, Gong-Ru Lin
2017 — conf
Session 28 overview: Hybrid ADCs.
ISSCC
Tai-Cheng Lee, Bob Verbruggen, Un-Ku Moon
2016 — conf
27.7 A 10b 2.6GS/s time-interleaved SAR ADC with background timing-skew calibration.
ISSCC
Chin-Yu Lin, Yen-Hsin Wei, Tai-Cheng Lee
2016 J jnl
A 12-bit 210-MS/s 2-Times Interleaved Pipelined-SAR ADC With a Passive Residue Transfer Technique.
IEEE Trans. Circuits Syst. I Regul. Pap.
Chin-Yu Lin, Tai-Cheng Lee
2016 J jnl
A 200-MS/s Phase-Detector-Based Comparator With 400-μV
IEEE Trans. Circuits Syst. II Express Briefs
Chin-Yu Lin, Chien-Heng Wong, Chia-Hau Hsu, Yen-Hsin Wei, Tai-Cheng Lee
2016 J jnl
A 5 GHz Fractional-N ADC-Based Digital Phase-Locked Loops With -243.8 dB FOM.
IEEE Trans. Circuits Syst. I Regul. Pap.
Wei-Sung Chang, Tai-Cheng Lee
2016 J jnl
A Compact Multi-Input Power Conversion System with High Time-Efficiency Inductor-Sharing Technique for Thermoelectric Energy Harvesting Applications.
J. Circuits Syst. Comput.
Chia-Lun Chang, Tai-Cheng Lee
2016 — conf
A technique for in-band phase noise reduction in fractional-N frequency synthesizers.
A-SSCC
Chun-Ping Wang, Tai-Cheng Lee
2016 — conf
Session 15 overview: Oversampling data converters.
ISSCC
Venkatesh Srinivasan, Tai-Cheng Lee
2015 — conf
A 84.7-DR wide BW incremental ADC using CT structure.
VLSI-DAT
Ting-Yang Wang, Tai-Cheng Lee
2015 — conf
A single-channel 10-b 400-MS/s 8.7-mW pipeline ADC in a 90-nm technology.
A-SSCC
Chen-Kai Hsu, Tai-Cheng Lee
2014 J jnl
2.4-GHz High-Efficiency Adaptive Power.
IEEE Trans. Very Large Scale Integr. Syst.
Cheng-Jyun Li, Tai-Cheng Lee
2014 — conf
21.2 A 2.3GHz fractional-N dividerless phase-locked loop with -112dBc/Hz in-band phase noise.
ISSCC
Po-Chun Huang, Wei-Sung Chang, Tai-Cheng Lee
2014 — conf
A 12-bit 210-MS/s 5.3-mW pipelined-SAR ADC with a passive residue transfer technique.
VLSIC
Chin-Yu Lin, Tai-Cheng Lee
2014 C conf
A 20-MHz BW 75-dB SFDR shifted-averaging VCO-based ΔΣ modulator.
ISCAS
Yu-Hsuan Kang, Chin-Yu Lin, Tai-Cheng Lee
2014 — conf
A 3X-oversampling hybrid clock and data recovery circuit with programmable bandwidth.
VLSI-DAT
Jia-An Jheng, Wei-Sung Chang, Tai-Cheng Lee
2014 — conf
A 6-Gb/s adaptive-loop-bandwidth clock and data recovery (CDR) circuit.
A-SSCC
Li-Hung Chiueh, Tai-Cheng Lee
2014 J jnl
A Fractional-N Divider-Less Phase-Locked Loop With a Subsampling Phase Detector.
IEEE J. Solid State Circuits
Wei-Sung Chang, Po-Chun Huang, Tai-Cheng Lee
2014 — conf
A compact multi-input thermoelectric energy harvesting system with 58.5% power conversion efficiency and 32.4-mW output power capability.
ISIC
Chia-Lun Chang, Tai-Cheng Lee
2013 J jnl
A 6-GHz Self-Oscillating Spread-Spectrum Clock Generator.
IEEE Trans. Circuits Syst. I Regul. Pap.
Chien-Heng Wong, Tai-Cheng Lee
2013 — conf
Analysis of the leakage effect in a pipelined ADC with nanoscale CMOS technologies.
VLSI-DAT
Chin-Yu Lin, Yen-Chuan Huang, Tai-Cheng Lee
2013 — conf
Jitter error cancellation technique in digital domain for ADC.
VLSI-DAT
Chin-Yu Lin, Tai-Cheng Lee
2012 — conf
A 10-bit 200-MS/s reconfigurable pipelined A/D converter.
VLSI-DAT
Chia-Chi Ho, Tai-Cheng Lee
2011 J jnl
A 10-bit 100-MS/s 4.5-mW Pipelined ADC With a Time-Sharing Technique.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yen-Chuan Huang, Tai-Cheng Lee
2011 J jnl
The Design and Analysis of Dual-Delay-Path Ring Oscillators.
IEEE Trans. Circuits Syst. I Regul. Pap.
Zuow-Zun Chen, Tai-Cheng Lee
2011 J jnl
The Study of a Dual-Mode Ring Oscillator.
IEEE Trans. Circuits Syst. II Express Briefs
Zuow-Zun Chen, Tai-Cheng Lee
2010 J jnl
A 0.02-mm
IEEE J. Solid State Circuits
Yen-Chuan Huang, Tai-Cheng Lee
2010 — conf
A 10b 100MS/s 4.5mW pipelined ADC with a time sharing technique.
ISSCC
Yen-Chuan Huang, Tai-Cheng Lee
2010 — conf
An all-digital de-skew clock generator for arbitrary wide range delay.
APCCAS
Kevin Fong, Yu-Cheng Hung, Zuow-Zun Chen, Tai-Cheng Lee
2010 — conf
An offset phase-locked loop spread spectrum clock generator for SATA III.
CICC
Chin-Yu Lin, Chun-Yu Chiang, Tai-Cheng Lee
2010 J jnl
Nonlinear R-2R Transistor-Only DAC.
IEEE Trans. Circuits Syst. I Regul. Pap.
Tai-Cheng Lee, Cheng-Hsiao Lin
2009 J jnl
A Split-Based Digital Background Calibration Technique in Pipelined ADCs.
IEEE Trans. Circuits Syst. II Express Briefs
Li-Han Hung, Tai-Cheng Lee
2009 J jnl
An 8-GHz to 10-GHz Distributed DLL for Multiphase Clock Generation.
IEEE J. Solid State Circuits
Keng-Jan Hsiao, Tai-Cheng Lee
2008 — conf
A Low-Jitter 8-to-10GHz Distributed DLL for Multiple-Phase Clock Generation.
ISSCC
Keng-Jan Hsiao, Tai-Cheng Lee
2008 J jnl
The Design and Analysis of a Fully Integrated Multiplying DLL With Adaptive Current Tuning.
IEEE J. Solid State Circuits
Keng-Jan Hsiao, Tai-Cheng Lee
2007 J jnl
A 6-bit 800-MS/s Pipelined A/D Converter With Open-Loop Amplifiers.
IEEE J. Solid State Circuits
Ding-Lan Shen, Tai-Cheng Lee
2007 — conf
A Delay-Line-Based GFSK Demodulator for Low-IF Receivers.
ISSCC
Hong-Sing Kao, Ming-Jen Yang, Tai-Cheng Lee
2006 — conf
A Spur Suppression Technique for Phase-Locked Frequency Synthesizers.
ISSCC
Tai-Cheng Lee, Wei-Liang Lee
2006 J jnl
A mixed-signal GFSK demodulator for Bluetooth.
IEEE Trans. Circuits Syst. II Express Briefs
Tai-Cheng Lee, Chin-Chi Chen
2006 J jnl
The design and analysis of a DLL-based frequency synthesizer for UWB application.
IEEE J. Solid State Circuits
Tai-Cheng Lee, Keng-Jan Hsiao
2006 J jnl
The design and analysis of a Miller-divider-based clock generator for MBOA-UWB application.
IEEE J. Solid State Circuits
Tai-Cheng Lee, Yen-Chuan Huang
2005 — conf
A linear-approximation technique for digitally-calibrated pipelined A/D converters.
ISCAS (2)
Ding-Lan Shen, Tai-Cheng Lee
2005 — conf
An optimization technique for RF buffers with active inductors.
ISCAS (4)
Tai-Cheng Lee, Yen-Chuan Huang
2004 — conf
A 10 Gbase-LX4 receiver front end transimpedance amplifier and limiting amplifier.
ISCAS (4)
Hung-Chieh Tsai, Jyh-Yih Yeh, Wei-Hsuan Tu, Tai-Cheng Lee, Chorng-Kuang Wang
2003 J jnl
A stabilization technique for phase-locked frequency synthesizers.
IEEE J. Solid State Circuits
Tai-Cheng Lee, Behzad Razavi
2002 — conf
CMOS 2.4-GHz receiver front end with area-efficient inductors and digitally calibrated 90° delay network.
ISCAS (3)
Chih-Chun Tang, Chia-Hsin Wu, Kun-Hsien Li, Tai-Cheng Lee, Shen-Iuan Liu
2001 — conf
A 125-MHz CMOS mixed-signal equalizer for Gigabit Ethernet on copper wire.
CICC
Tai-Cheng Lee, Behzad Razavi
2001 J jnl
A 125-MHz mixed-signal echo canceller for Gigabit Ethernet on copper wire.
IEEE J. Solid State Circuits
Tai-Cheng Lee, Behzad Razavi
2000 — conf
A 4-tap 125-MHz mixed-signal echo canceller for Gigabit Ethernet on copper wire.
CICC
Tai-Cheng Lee, Behzad Razavi