Tai-Chen Chen - RankMe

20 papers A* 2A 3C 1Journal 4Unranked 10

Year	Rank	Type	Title / Venue / Authors
2024	A	`conf`	Modern Fixed-Outline Floorplanning with Rectilinear Soft Modules. ICCAD Yu-Yang Chen, Yi-Chen Lin, Tzu-Han Hsu, Iris Hui-Ru Jiang, Tung-Chieh Chen, Tai-Chen Chen, Hua-Yu Chang
2022	J	`jnl`	Flexible Multiple-Objective Reinforcement Learning for Chip Placement. CoRR Fu-Chieh Chang, Yu-Wei Tseng, Ya-Wen Yu, Ssu-Rui Lee, Alexandru Cioba, I-Lun Tseng, Da-Shan Shiu, Jhih-Wei Hsu, Cheng-Yuan Wang, Chien-Yi Yang, Ren-Chu Wang, Yao-Wen Chang, Tai-Chen Chen, Tung-Chieh Chen
2022	A*	`conf`	Flexible chip placement via reinforcement learning: late breaking results. DAC Fu-Chieh Chang, Yu-Wei Tseng, Ya-Wen Yu, Ssu-Rui Lee, Alexandru Cioba, I-Lun Tseng, Da-Shan Shiu, Jhih-Wei Hsu, Cheng-Yuan Wang, Chien-Yi Yang, Ren-Chu Wang, Yao-Wen Chang, Tai-Chen Chen, Tung-Chieh Chen
2020	—	`conf`	Automatic Floorplanning for AI SoCs. VLSI-DAT Tai-Chen Chen, Pei-Yu Lee, Tung-Chieh Chen
2014	A	`conf`	Design-for-debug routing for FIB probing. DATE Chia-Yi Lee, Tai-Hung Li, Tai-Chen Chen
2014	A	`conf`	The overview of 2014 CAD contest at ICCAD. ICCAD Iris Hui-Ru Jiang, Natarajan Viswanathan, Tai-Chen Chen, Jin-Fu Li
2013	—	`conf`	Electromigration- and obstacle-avoiding routing tree construction. VLSI-DAT Yun-Chih Tsai, Tai-Hung Li, Tai-Chen Chen, Chung-Wei Yeh
2013	—	`conf`	LASER: layout-aware analog synthesis environment on laker. ACM Great Lakes Symposium on VLSI Yu-Ching Liao, Yen-Lung Chen, Xian-Ting Cai, Chien-Nan Jimmy Liu, Tai-Chen Chen
2012	—	`conf`	Escape routing of differential pairs considering length matching. ASP-DAC Tai-Hung Li, Wan-Chun Chen, Xian-Ting Cai, Tai-Chen Chen
2012	—	`conf`	Micro-bump assignment for 3D ICs using order relation. ASP-DAC Ta-Yu Kuan, Yi-Chun Chang, Tai-Chen Chen
2012	—	`conf`	Native-conflict-avoiding track routing for double patterning technology. SoCC Bi-Ting Lai, Tai-Hung Li, Tai-Chen Chen
2011	—	`conf`	ILP-based inter-die routing for 3D ICs. ASP-DAC Chia-Jen Chang, Pao-Jen Huang, Tai-Chen Chen, Chien-Nan Jimmy Liu
2010	J	`jnl`	Predictive Formulae for OPC With Applications to Lithography-Friendly Routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Tai-Chen Chen, Guang-Wan Liao, Yao-Wen Chang
2008	A*	`conf`	Predictive formulae for OPC with applications to lithography-friendly routing. DAC Tai-Chen Chen, Guang-Wan Liao, Yao-Wen Chang
2007	J	`jnl`	Multilevel Full-Chip Gridless Routing With Applications to Optical-Proximity Correction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Tai-Chen Chen, Yao-Wen Chang
2007	—	`conf`	Recent Research and Emerging Challenges in Physical Design for Manufacturability/Reliability. ASP-DAC Chung-Wei Lin, Ming-Chao Tsai, Kuang-Yao Lee, Tai-Chen Chen, Ting-Chi Wang, Yao-Wen Chang
2006	—	`conf`	A novel framework for multilevel full-chip gridless routing. ASP-DAC Tai-Chen Chen, Yao-Wen Chang, Shyh-Chang Lin
2005	—	`conf`	Multilevel full-chip gridless routing considering optical proximity correction. ASP-DAC Tai-Chen Chen, Yao-Wen Chang
2004	J	`jnl`	Timing modeling and optimization under the transmission line model. IEEE Trans. Very Large Scale Integr. Syst. Tai-Chen Chen, Song-Ra Pan, Yao-Wen Chang
2001	C	`conf`	Performance Optimization By Wire and Buffer Sizing Under The Transmission Line Model. ICCD Tai-Chen Chen, Song-Ra Pan, Yao-Wen Chang