Taha Soliman

25 papers A* 2B 2C 2Journal 6Unranked 12
YearRankTypeTitle / Venue / Authors
2025 J jnl
A Lightweight PUF-Based Weights Obfuscation Technique for Secure In-Memory AI Inference.
IEEE Trans. Circuits Syst. I Regul. Pap.
Luca Parrini, Anirban Kar, Benjamin Hettwer, Taha Soliman, Yogesh Singh Chauhan, Hussam Amrouch, Norbert Wehn
2025 A* conf
Neoscope: How Resilient Is My SoC to Workload Churn?
ISCA
Joseph Rogers, Lieven Eeckhout, Taha Soliman, Magnus Jahre
2025 B conf
Optimization of DNNs Using a Hardware Aware Two Stage NAS for Automotive Embedded Targets.
ICCP
Andrei Viman, Mihai Negru, Martin Rapp, Taha Soliman
2024 A* conf
AIO: An Abstraction for Performance Analysis Across Diverse Accelerator Architectures.
ISCA
Joseph Rogers, Taha Soliman, Magnus Jahre
2024 — conf
Accelerating Automated Driving and ADAS Using HW/SW Codesign.
SOCC
Shubham Rai, Cecilia De la Parra, Martin Rapp, Jan Micha Borrmann, Nina Bretz, Stefan Metzlaff, Taha Soliman, Christoph Schorn
2024 — conf
CoNAX: Towards Comprehensive Co-Design Neural Architecture Search Using HW Abstractions.
ASAP
Yannick Braatz, Taha Soliman, Shubham Rai, Dennis Sebastian Rieber, Oliver Bringmann
2024 B conf
Error Detection and Correction Codes for Safe In-Memory Computations.
ETS
Luca Parrini, Taha Soliman, Benjamin Hettwer, Jan Micha Borrmann, Simranjeet Singh, Ankit Bende, Vikas Rana, Farhad Merchant, Norbert Wehn
2024 J jnl
Error Detection and Correction Codes for Safe In-Memory Computations.
CoRR
Luca Parrini, Taha Soliman, Benjamin Hettwer, Jan Micha Borrmann, Simranjeet Singh, Ankit Bende, Vikas Rana, Farhad Merchant, Norbert Wehn
2023 J jnl
Demonstration of Differential Mode Ferroelectric Field-Effect Transistor Array-Based in-Memory Computing Macro for Realizing Multiprecision Mixed-Signal Artificial Intelligence Accelerator.
Adv. Intell. Syst.
Vivek Parmar, Franz Müller, Jing-Hua Hsuen, Sandeep Kaur Kingra, Nellie Laleni, Yannick Raffel, Maximilian Lederer, Alptekin Vardar, Konrad Seidel, Taha Soliman, Tobias Kirchner, Tarek Ali, Stefan Dünkel, Sven Beyer, Tian-Li Wu, Sourav De, Manan Suri, Thomas Kämpfe
2023 — conf
SimPyler: A Compiler-Based Simulation Framework for Machine Learning Accelerators.
ASAP
Yannick Braatz, Dennis Sebastian Rieber, Taha Soliman, Oliver Bringmann
2023 — conf
Simulation-driven Latency Estimations for Multi-core Machine Learning Accelerators.
AICAS
Yannick Braatz, Dennis Sebastian Rieber, Taha Soliman, Oliver Bringmann
2023 — conf
Torwards Variability Immune Scalable FeFET-based Macros for IMC DNN Accelerators.
ICECS
Nellie Laleni, Taha Soliman, Cecilia De la Parra, Franz Müller, Tobias Kirchner, Andre Guntoro, Thomas Kämpfe, Norbert Wehn, T. Jang
2022 J jnl
A Weighted Current Summation Based Mixed Signal DRAM-PIM Architecture for Deep Neural Network Inference.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Chirag Sudarshan, Taha Soliman, Jan Lappas, Christian Weis, Mohammad Hassani Sadi, Matthias Jung, Andre Guntoro, Norbert Wehn
2022 — conf
Efficient Hardware Approximation for Bit-Decomposition Based Deep Neural Network Accelerators.
SOCC
Taha Soliman, Amro Eldebiky, Cecilia De la Parra, Andre Guntoro, Norbert Wehn
2022 J jnl
FELIX: A Ferroelectric FET Based Low Power Mixed-Signal In-Memory Architecture for DNN Acceleration.
ACM Trans. Embed. Comput. Syst.
Taha Soliman, Nellie Laleni, Tobias Kirchner, Franz Müller, Ashish Shrivastava, Thomas Kämpfe, Andre Guntoro, Norbert Wehn
2022 C conf
FeFET versus DRAM based PIM Architectures: A Comparative Study.
VLSI-SoC
Chirag Sudarshan, Taha Soliman, Thomas Kämpfe, Christian Weis, Norbert Wehn
2022 J jnl
Increasing Throughput of In-Memory DNN Accelerators by Flexible Layerwise DNN Approximation.
IEEE Micro
Cecilia De la Parra, Taha Soliman, Andre Guntoro, Akash Kumar, Norbert Wehn
2022 — —
Ultra-low power approximate processing-in-memory acceleration for deep neural networks = Approximative Prozessierung viellagiger neuronaler Netze in Speichermatrizen für Systeme mit ultra-geringer Leistungsaufnahme.
Taha Soliman
2021 — conf
A Novel DRAM-Based Process-in-Memory Architecture and its Implementation for CNNs.
ASP-DAC
Chirag Sudarshan, Taha Soliman, Cecilia De la Parra, Christian Weis, Leonardo Ecco, Matthias Jung, Norbert Wehn, Andre Guntoro
2021 — conf
Adaptable Approximation Based on Bit Decomposition for Deep Neural Network Accelerators.
AICAS
Taha Soliman, Cecilia De la Parra, Andre Guntoro, Norbert Wehn
2021 C conf
Exploiting Resiliency for Kernel-Wise CNN Approximation Enabled by Adaptive Hardware Design.
ISCAS
Cecilia De la Parra, Ahmed El-Yamany, Taha Soliman, Akash Kumar, Norbert Wehn, Andre Guntoro
2020 — conf
A Ferroelectric FET Based In-memory Architecture for Multi-Precision Neural Networks.
SoCC
Taha Soliman, Ricardo Olivo, Tobias Kirchner, Maximilian Lederer, Thomas Kämpfe, Andre Guntoro, Norbert Wehn
2020 — conf
Efficient FeFET Crossbar Accelerator for Binary Neural Networks.
ASAP
Taha Soliman, Ricardo Olivo, Tobias Kirchner, Cecilia De la Parra, Maximilian Lederer, Thomas Kämpfe, Andre Guntoro, Norbert Wehn
2020 — conf
Enhancing the Utilization of Dot-Product Engines in Deep Learning Accelerators.
IPDPS Workshops
Taha Soliman, Armin Runge, Leonardo Ecco
2019 — conf
Fast validation of DRAM protocols with timed petri nets.
MEMSYS
Matthias Jung, Kira Kraft, Taha Soliman, Chirag Sudarshan, Christian Weis, Norbert Wehn