Taewhan Kim - RankMe

177 papers A* 16A 32B 1C 7Misc 1Journal 66Unranked 53

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	ML-driven Design Technology Co-Optimization Framework for Advanced Technology Nodes. ASP-DAC Hyunbae Seo, Handong Cho, Sehyeon Chung, Kyu-Myung Choi, Taewhan Kim
2025	A	`conf`	Adaptive Pin Pattern Modification on Standard Cells Towards ECO Routing. ICCAD Jaehoon Ahn, Sehyeon Chung, Taewhan Kim
2025	J	`jnl`	Design and Utilization of Multiskewed Multibit Flip-Flop Cells for Timing Optimization: Design and Technology Co-Optimization Approach. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Suwan Kim, Taewhan Kim
2025	—	`conf`	Invited: Physical Design Challenges for Design Technology Co-optimization. ISPD Taewhan Kim
2025	—	`conf`	PPA-Aware Tier Partitioning for 3D IC Placement with ILP Formulation. ASP-DAC Eunsol Jeong, Taewhan Kim, Heechun Park
2025	A	`conf`	Synthesis of Standard Cells of Minimum Delay. ICCAD Sehyeon Chung, Hyunbae Seo, Taewhan Kim
2025	C	`conf`	Timing-Driven Multi-Bit Flip-Flop Allocation Utilizing Design-Technology Co-Optimization Techniques. ICCD Yeongyeong Shin, Sehyeon Chung, Taewhan Kim
2024	A	`conf`	BOXGB: Design Parameter Optimization with Systematic Integration of Bayesian Optimization and XGBoost. DATE Chanhee Jeon, Doyeon Won, Jaewan Yang, Kyu-Myung Choi, Taewhan Kim
2024	A*	`conf`	Binding Multi-bit Flip-flop Cells through Design and Technology Co-optimization. DAC Jooyeon Jeong, Taewhan Kim
2024	J	`jnl`	CSyn-fp: Standard Cell Synthesis of Advanced Nodes With Simultaneous Transistor Folding and Placement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Kyeonghyeon Baek, Taewhan Kim
2024	J	`jnl`	DTOC-P: Deep-Learning-Driven Timing Optimization Using Commercial EDA Tool With Practicality Enhancement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jaehoon Ahn, Kyungjoon Chang, Kyumyung Choi, Taewhan Kim, Heechun Park
2024	—	`conf`	Design and Allocation of Multi-bit Flip-flop Cells Amenable to Placement Legalization in Physical Design. SOCC Yeongyeong Shin, Taewhan Kim
2024	J	`jnl`	Enhancing Design Qualities Utilizing Multibit Flip-Flops: A Design and Technology Co-Optimization Driven Approach. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Soomin Kim, Taewhan Kim
2024	—	`conf`	Improving Timing Quality Through Net Topology Optimization in Global Routing. SOCC Jayoung Yang, Taewhan Kim
2024	—	`conf`	Methodology of Resolving Design Rule Checking Violations Coupled with Fully Compatible Prediction Model. ISPD Suwan Kim, Hyunbum Park, Kyeonghyeon Baek, Kyumyung Choi, Taewhan Kim
2024	C	`conf`	Net Topology Exploration and Tuning for Mitigating Congestion in Global Routing. ISCAS Hwapyong Kim, Taewhan Kim
2024	A	`conf`	Optimal Layout Synthesis of Multi-Row Standard Cells for Advanced Technology Nodes. ICCAD Sehyeon Chung, Hyunbae Seo, Handong Cho, Kyumyung Choi, Taewhan Kim
2024	A*	`conf`	Optimal Transistor Folding and Placement for Synthesizing Standard Cells of Complementary FET Technology. DAC Suwan Kim, Taewhan Kim
2024	J	`jnl`	Pin Accessibility and Routing Congestion Aware DRC Hotspot Prediction for Designs in Advanced Technology Nodes With Consolidated Practical Applicability and Sustainability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hyunbum Park, Kyeonghyeon Baek, Suwan Kim, Kyumyung Choi, Taewhan Kim
2024	J	`jnl`	Placement legalization for heterogeneous cells of non-integer multiple-heights. Integr. Jooyeon Jeong, Taewhan Kim
2024	J	`jnl`	Pre-route timing prediction and optimization with graph neural network models. Integr. Kyungjoon Chang, Taewhan Kim
2024	J	`jnl`	Recap of the 29th Edition of the Asia and South Pacific Design Automation Conference (ASPDAC 2024). IEEE Des. Test Taewhan Kim
2024	—	`conf`	Recent Research in Design and Technology Co-Optimization with Multi-Bit Flip-Flops. MWSCAS Taewhan Kim
2024	A	`conf`	Standard Cell Layout Generator Amenable to Design Technology Co-Optimization in Advanced Process Nodes. DATE Handong Cho, Hyunbae Seo, Sehyeon Chung, Kyu-Myung Choi, Taewhan Kim
2023	—	`conf`	Allocation of Multi-bit Flip-Flops Targeting Low-Power Chips. ISOCC Jinmyoung Kim, Taewhan Kim
2023	—	`conf`	Challenges on Design and Technology Co-Optimization: Design Automation Perspective. MWSCAS Taewhan Kim
2023	A	`conf`	DTOC: integrating Deep-learning driven Timing Optimization into the state-of-the-art Commercial EDA tool. DATE Kyungjoon Chang, Jaehoon Ahn, Heechun Park, Kyu-Myung Choi, Taewhan Kim
2023	—	`conf`	Debanking Techniques on Multi-bit Flip-flops for Reinforcing Useful Clock Skew Scheduling. SOCC Jaewan Yang, Taewhan Kim
2023	A	`conf`	Design and Technology Co-Optimization for Useful Skew Scheduling on Multi-Bit Flip-Flops. ICCAD Suwan Kim, Taewhan Kim
2023	J	`jnl`	Eliminating Minimum Implant Area Violations With Design Quality Preservation. IEEE Trans. Very Large Scale Integr. Syst. Eunsol Jeong, Taewhan Kim, Heechun Park
2023	—	`conf`	Fast Refinement on Placement Legalization for Designs with Mixed-Height Cells. ISOCC Kihwan Jeon, Taewhan Kim
2023	C	`conf`	Machine Learning Based Flip-Flop Grouping for Toggling Driven Clock Gating. ISCAS Sora Park, Taewhan Kim
2023	A	`conf`	Machine Learning Driven Synthesis of Clock Gating. ISLPED Doyeon Won, Soomin Kim, Taewhan Kim
2023	—	`conf`	Maximizing Power Saving Through State-Driven Clock Gating. ISOCC Chaehyun Kim, Taewhan Kim
2023	—	`conf`	Optimizing Timing for Multi-bit Flip-Flop Intensive Designs Compatible with Commercial EDA Flow. ISOCC Ilseon Ha, Taewhan Kim
2023	—	`conf`	Placement Legalization Amenable to Mixed-cell-height Standard Cells Integrating into State-of-the-art Commercial EDA Tool. ACM Great Lakes Symposium on VLSI Hwapyong Kim, Taewhan Kim
2023	A	`conf`	Synthesis and Utilization of Standard Cells Amenable to Gear Ratio of Gate-Metal Pitches for Improving Pin Accessibility. DATE Jooyeon Jeong, Sehyeon Chung, Kyeongrok Jo, Taewhan Kim
2022	A	`conf`	A Systematic Removal of Minimum Implant Area Violations under Timing Constraint. DATE Eunsol Jeong, Heechun Park, Taewhan Kim
2022	—	`conf`	Analysis of Impacting Multi-stack Standard Cells on Chip Implementation. ISOCC Kyungjoon Chang, Taewhan Kim
2022	J	`jnl`	Deeper Weight Pruning Without Accuracy Loss in Deep Neural Networks: Signed-Digit Representation-Based Approach. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Byungmin Ahn, Taewhan Kim
2022	A	`conf`	Design and Technology Co-Optimization Utilizing Multi-Bit Flip-Flop Cells. ICCAD Soomin Kim, Taewhan Kim
2022	J	`jnl`	ECO routing based on network flow method. Integr. Sehyeon Chung, Taewhan Kim
2022	J	`jnl`	Hardware Performance Monitoring Methodology at Near-Threshold Computing and Advanced Technology Nodes: From Design to Postsilicon. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jeongwoo Heo, Kwangok Jeong, Jungyun Choi, Taewhan Kim, Kyumyung Choi
2022	A	`conf`	Improving Performance and Power by Co-Optimizing Middle-of-Line Routing, Pin Pattern Generation, and Contact over Active Gates in Standard Cell Layout Synthesis. ISLPED Sehyeon Chung, Jooyeon Jeong, Taewhan Kim
2022	C	`conf`	Improving Pin Accessibility of Standard Cells Through Fin Depopulation. ISCAS Doyeon Won, Taewhan Kim
2022	C	`conf`	Optimizing Timing in Placement Through I/O Signal Flipping on Multi-bit Flip-flops. ISCAS Soomin Kim, Taewhan Kim
2022	A	`conf`	Pin Accessibility and Routing Congestion Aware DRC Hotspot Prediction Using Graph Neural Network and U-Net. ICCAD Kyeonghyeon Baek, Hyunbum Park, Suwan Kim, Kyumyung Choi, Taewhan Kim
2022	A	`conf`	Pin Accessibility-driven Placement Optimization with Accurate and Comprehensive Prediction Model. DATE Suwan Kim, Taewhan Kim
2022	C	`conf`	Selective Clock Gating Based on Comprehensive Power Saving Analysis. ISCAS Sora Park, Taewhan Kim
2022	J	`jnl`	Speeding-up neuromorphic computation for neural networks: Structure optimization approach. Integr. Heechun Park, Taewhan Kim
2022	A	`conf`	Tightly Linking 3D Via Allocation Towards Routing Optimization for Monolithic 3D ICs. ISLPED Suwan Kim, Sehyeon Chung, Taewhan Kim, Heechun Park
2021	J	`jnl`	Allocation of Always-On State Retention Storage for Power Gated Circuits - Steady-State- Driven Approach. IEEE Trans. Very Large Scale Integr. Syst. Taehwan Kim, Heechun Park, Taewhan Kim
2021	J	`jnl`	Allocation of Multibit Retention Flip-Flops for Power Gated Circuits: Algorithm-Design Unified Approach. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Gyoung-Hwan Hyun, Taewhan Kim
2021	—	`conf`	Analyses of Power Staple Inserting Methodologies for Mitigating IR-Drops. ISOCC Jaejoon Yoon, Sehyeon Chung, Taewhan Kim
2021	—	`conf`	Boosting Pin Accessibility Through Cell Layout Topology Diversification. ASP-DAC Suwan Kim, Kyeongrok Jo, Taewhan Kim
2021	—	`conf`	Challenges on DTCO Methodology Towards Deep Submicron Interconnect Technology. ISOCC Heechun Park, Kyungjoon Chang, Jooyeon Jeong, Jaehoon Ahn, Ki-Seok Chung, Taewhan Kim
2021	J	`jnl`	Common Kernels and Convolutions in Binary- and Ternary-Weight Neural Networks. J. Circuits Syst. Comput. Byungmin Ahn, Taewhan Kim
2021	—	`conf`	Minimally Allocating Always-on State Retention Storage for Supporting Power Gating Circuits. ISQED Soomin Kim, Taewhan Kim
2021	—	`conf`	Minimum Implant Area-Aware Threshold Voltage Refinement in Pre-Placement. MWSCAS Eunsol Jeong, Heechun Park, Jooyeon Jeong, Taewhan Kim
2021	C	`conf`	Optimal Transistor Placement Combined with Global In-cell Routing in Standard Cell Layout Synthesis. ICCD Kyeongrok Jo, Taewhan Kim
2021	—	`conf`	Practical Approach to Cell Replacement for Resolving Pin Inaccessibility. MWSCAS Suwan Kim, Taewhan Kim
2021	J	`jnl`	Reusable Delay Path Synthesis for Lightening Asynchronous Pipeline Controller. IEEE Trans. Very Large Scale Integr. Syst. Jeongwoo Heo, Taewhan Kim
2021	A	`conf`	Simultaneous Transistor Folding and Placement in Standard Cell Layout Synthesis. ICCAD Kyeonghyeon Baek, Taewhan Kim
2021	A	`conf`	Speeding up MUX-FSM based Stochastic Computing for On-device Neural Networks. DATE Jongsung Kang, Taewhan Kim
2021	—	`conf`	Utilizing Middle-of-Line Resource in Filler Cells for Fixing Routing Failures. MWSCAS Jooyeon Jeong, Taewhan Kim
2020	—	`conf`	Lightening Asynchronous Pipeline Controller Through Resynthesis and Optimization. ASP-DAC Jeongwoo Heo, Taewhan Kim
2020	J	`jnl`	SRAM on-chip monitoring methodology for high yield and energy efficient memory operation at near threshold voltage. Integr. Taehwan Kim, Kwangok Jeong, Jungyun Choi, Taewhan Kim, Kyu-Myung Choi
2020	A	`conf`	Steady state driven power gating for lightening always-on state retention storage. ISLPED Taehwan Kim, Gyoung-Hwan Hyun, Taewhan Kim
2020	—	`conf`	Synthesis of Hardware Performance Monitoring and Prediction Flow Adapting to Near-Threshold Computing and Advanced Process Nodes. ASP-DAC Jeongwoo Heo, Kwangok Jeong, Taewhan Kim, Kyu-Myung Choi
2019	J	`jnl`	Design Rule Evaluation Framework Using Automatic Cell Layout Generator for Design Technology Co-Optimization. IEEE Trans. Very Large Scale Integr. Syst. Kyeongrok Jo, Seyong Ahn, Jungho Do, Taejoong Song, Taewhan Kim, Kyu-Myung Choi
2019	J	`jnl`	Hybrid asynchronous circuit generation amenable to conventional EDA flow. Integr. Heechun Park, Taewhan Kim
2019	—	`conf`	SRAM On-Chip Monitoring Methodology for Energy Efficient Memory Operation at Near Threshold Voltage. ISVLSI Taehwan Kim, Kwangok Jeong, Taewhan Kim, Kyu-Myung Choi
2018	—	`conf`	Cohesive techniques for cell layout optimization supporting 2D metal-1 routing completion. ASP-DAC Kyeongrok Jo, Seyong Ahn, Taewhan Kim, Kyu-Myung Choi
2018	A	`conf`	Design and algorithm for clock gating and flip-flop co-optimization. ICCAD Giyoung Yang, Taewhan Kim
2018	A	`conf`	Structure optimizations of neuromorphic computing architectures for deep neural network. DATE Heechun Park, Taewhan Kim
2017	J	`jnl`	Adjustable Delay Buffer Allocation under Useful Clock Skew Scheduling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Juyeon Kim, Taewhan Kim
2017	J	`jnl`	Clock buffer polarity assignment under useful skew constraints. Integr. Deokjin Joo, Taewhan Kim
2016	A	`conf`	Allocation of multi-bit flip-flops in logic synthesis for power optimization. ICCAD Dongyoun Yi, Taewhan Kim
2016	—	`conf`	Clock buffer polarity assignment utilizing useful clock skews for power noise reduction. ASP-DAC Deokjin Joo, Taewhan Kim
2016	J	`jnl`	Design Methodology for Synthesizing Resonant Clock Networks in the Presence of Dynamic Voltage/Frequency Scaling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Seyong Ahn, Minseok Kang, Marios C. Papaefthymiou, Taewhan Kim
2016	J	`jnl`	Optimal utilization of adjustable delay clock buffers for timing correction in designs with multiple power modes. Integr. Juyeon Kim, Deokjin Joo, Taewhan Kim
2016	—	`conf`	Synthesizing Asynchronous Circuits toward Practical Use. ISVLSI Heechun Park, Taewhan Kim
2016	—	`conf`	Timing Analysis and Optimization Based on Flexible Flip-Flop Timing Model. ISVLSI Jeongwoo Heo, Taewhan Kim
2015	—	`conf`	Clock skew optimization for maximizing time margin by utilizing flexible flip-flop timing. ISQED Hyungjung Seo, Jeongwoo Heo, Taewhan Kim
2015	A	`conf`	Synthesis for Power-Aware Clock Spines. ICCAD Hyungjung Seo, Juyeon Kim, Minseok Kang, Taewhan Kim
2015	J	`jnl`	Synthesis of TSV Fault-Tolerant 3-D Clock Trees. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Heechun Park, Taewhan Kim
2015	—	`conf`	Synthesis of resonant clock networks supporting dynamic voltage / frequency scaling. ASP-DAC Seyong Ahn, Minseok Kang, Marios C. Papaefthymiou, Taewhan Kim
2014	J	`jnl`	A Fine-Grained Clock Buffer Polarity Assignment for High-Speed and Low-Power Digital Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Deokjin Joo, Taewhan Kim
2014	J	`jnl`	Edge layer embedding algorithm for mitigating on-package variation in 3D clock tree synthesis. Integr. Sangdo Park, Taewhan Kim
2014	J	`jnl`	Integrated Resource Allocation and Binding in Clock Mesh Synthesis. ACM Trans. Design Autom. Electr. Syst. Minseok Kang, Taewhan Kim
2014	A	`conf`	Mixed allocation of adjustable delay buffers combined with buffer sizing in clock tree synthesis of multiple power mode designs. DATE Kitae Park, Geunho Kim, Taewhan Kim
2014	—	`conf`	Post-silicon tuning aware wafer matching algorithm for 3d integration of ICs. MWSCAS Sangdo Park, Taewhan Kim
2013	J	`jnl`	An Optimal Allocation Algorithm of Adjustable Delay Buffers and Practical Extensions for Clock Skew Optimization in Multiple Power Mode Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Kyoung-Hwan Lim, Deokjin Joo, Taewhan Kim
2013	A*	`conf`	An optimal algorithm of adjustable delay buffer insertion for solving clock skew variation problem. DAC Juyeon Kim, Deokjin Joo, Taewhan Kim
2013	A	`conf`	Comprehensive technique for designing and synthesizing TSV fault-tolerant 3D clock trees. ICCAD Heechun Park, Taewhan Kim
2013	J	`jnl`	Resource Allocation and Design Techniques of Prebond Testable 3-D Clock Tree. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Tak-Yung Kim, Taewhan Kim
2013	—	`conf`	Tutorial: Methodology for designing reliable clock networks. SoCC Taewhan Kim
2012	J	`jnl`	Design Methodologies for Reliable Clock Networks. J. Comput. Sci. Eng. Deokjin Joo, Minseok Kang, Taewhan Kim
2012	—	`conf`	Die matching algorithm for enhancing parametric yield of 3D ICs. ISOCC Sangdo Park, Taewhan Kim
2012	—	`ch.`	Power Saving by Task-Level Dynamic Voltage Scaling. Handbook of Energy-Aware and Green Computing Taewhan Kim
2012	J	`jnl`	Synthesis of Adaptable Hybrid Adders for Area Optimization under Timing Constraint. ACM Trans. Design Autom. Electr. Syst. Yonghwan Kim, Sanghoon Kwak, Taewhan Kim
2011	—	`conf`	An energy-optimal algorithm for temperature-aware idle time distribution considering mode transition overhead. ISOCC Sangdo Park, Taewhan Kim
2011	J	`jnl`	Buffer Sizing and Polarity Assignment in Clock Tree Synthesis for Power/Ground Noise Minimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hochang Jang, Deokjin Joo, Taewhan Kim
2011	J	`jnl`	Clock Tree synthesis for TSV-based 3D IC designs. ACM Trans. Design Autom. Electr. Syst. Tak-Yung Kim, Taewhan Kim
2011	—	`conf`	Clock design techniques considering circuit reliability. ISOCC Yonghwan Kim, Minseok Kang, Kyoung-Hwan Lim, Sangdo Park, Deokjin Joo, Taewhan Kim
2011	A*	`conf`	WaveMin: a fine-grained clock buffer polarity assignment combined with buffer sizing. DAC Deokjin Joo, Taewhan Kim
2010	—	`conf`	Bounded skew clock routing for 3D stacked IC designs: Enabling trade-offs between power and clock skew. Green Computing Conference Tak-Yung Kim, Taewhan Kim
2010	—	`conf`	Clock tree embedding for 3D ICs. ASP-DAC Tak-Yung Kim, Taewhan Kim
2010	A*	`conf`	Clock tree synthesis with pre-bond testability for 3D stacked IC designs. DAC Tak-Yung Kim, Taewhan Kim
2010	J	`jnl`	Task-Level Dynamic Voltage Scaling for Embedded System Design: Recent Theoretical Results. J. Comput. Sci. Eng. Taewhan Kim
2009	A*	`conf`	Simultaneous clock buffer sizing and polarity assignment for power/ground noise minimization. DAC Hochang Jang, Taewhan Kim
2009	J	`jnl`	Thermal sensor allocation and placement for reconfigurable systems. ACM Trans. Design Autom. Electr. Syst. ByungHyun Lee, Ki-Seok Chung, Bontae Koo, Nak-Woong Eum, Taewhan Kim
2009	J	`jnl`	Thermal-Aware High-Level Synthesis Based on Network Flow Method. J. Circuits Syst. Comput. Pilok Lim, Ki-Seok Chung, Taewhan Kim
2007	J	`jnl`	Integration of Code Scheduling, Memory Allocation, and Array Binding for Memory-Access Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Taewhan Kim, Jungeun Kim
2006	J	`jnl`	A HW/SW Partitioner for Multi-Mode Multi-Task Embedded Applications. J. VLSI Signal Process. Young-Jun Kim, Taewhan Kim
2006	A	`conf`	A systematic IP and bus subsystem modeling for platform-based system design. DATE Junhyung Um, Woo-Cheol Kwon, Sungpack Hong, Young-Taek Kim, Kyu-Myung Choi, Jeong-Taek Kong, Soo-Kwan Eo, Taewhan Kim
2006	B	`conf`	Application-Driven Low-Power Techniques Using Dynamic Voltage Scaling. RTCSA Taewhan Kim
2006	—	`conf`	HW/SW partitioning techniques for multi-mode multi-task embedded applications. ACM Great Lakes Symposium on VLSI Young-Jun Kim, Taewhan Kim
2006	J	`jnl`	Memory Access Driven Storage Assignment for Variables in Embedded System Design. J. Circuits Syst. Comput. Yoonseo Choi, Taewhan Kim
2006	J	`jnl`	Resource Sharing Combined with Layout Effects in High-Level Synthesis. J. VLSI Signal Process. Junhyung Um, Taewhan Kim
2006	Misc	`conf`	Thermal-aware high-level synthesis based on network flow method. CODES+ISSS Pilok Lim, Taewhan Kim
2005	A*	`conf`	Memory access optimization through combined code scheduling, memory allocation, and array binding in embedded system design. DAC Jungeun Kim, Taewhan Kim
2005	J	`jnl`	Memory layout techniques for variables utilizing efficient DRAM access modes in embedded system design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yoonseo Choi, Taewhan Kim, Hwansoo Han
2004	—	`conf`	An integrated approach to timing-driven synthesis and placement of arithmetic circuits. ASP-DAC Keoncheol Shin, Taewhan Kim
2004	J	`jnl`	CeRA: A Router for Symmetrical FPGAs Based on Exact Routing Density Evaluation. IEEE Trans. Computers Nak-Woong Eum, Taewhan Kim, Chong-Min Kyung
2004	J	`jnl`	Coupling-aware high-level interconnect synthesis [IC layout]. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chun-Gi Lyuh, Taewhan Kim, Ki-Wook Kim
2004	—	`conf`	Leakage power minimization for the synthesis of parallel multiplier circuits. ACM Great Lakes Symposium on VLSI Keoncheol Shin, Taewhan Kim
2004	—	`conf`	Memory access driven storage assignment for variables in embedded system design. ASP-DAC Yoonseo Choi, Taewhan Kim
2004	A*	`conf`	Memory access scheduling and binding considering energy minimization in multi-bank memory systems. DAC Chun-Gi Lyuh, Taewhan Kim
2004	A*	`conf`	Profile-based optimal intra-task voltage scheduling for hard real-time applications. DAC Jaewon Seo, Taewhan Kim, Ki-Seok Chung
2004	—	`conf`	Resource-constrained low-power bus encoding with crosstalk delay elimination. ASP-DAC Meeyoung Cha, Chun-Gi Lyuh, Taewhan Kim
2004	J	`jnl`	Tight integration of timing-driven synthesis and placement of parallel multiplier circuits. IEEE Trans. Very Large Scale Integr. Syst. Keoncheol Shin, Taewhan Kim
2003	J	`jnl`	Address assignment in DSP code generation - an integrated approach. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yoonseo Choi, Taewhan Kim
2003	—	`conf`	An efficient inverse multiplier/divider architecture for cryptography systems. ISCAS (5) Junhyung Um, Sangwoo Lee, Youngsoo Park, Sungik Jun, Taewhan Kim
2003	A	`conf`	Code Placement with Selective Cache Activity Minimization for Embedded Real-time Software Design. ICCAD Junhyung Um, Taewhan Kim
2003	J	`jnl`	Coupling delay optimization by temporal decorrelation using dual threshold voltage technique. IEEE Trans. Very Large Scale Integr. Syst. Ki-Wook Kim, Seong-Ook Jung, Taewhan Kim, Prashant Saxena, C. L. Liu, S.-M. S. Kang
2003	J	`jnl`	High-level synthesis for low power based on network flow method. IEEE Trans. Very Large Scale Integr. Syst. Chun-Gi Lyuh, Taewhan Kim
2003	A*	`conf`	Memory layout techniques for variables utilizing efficient DRAM access modes in embedded system design. DAC Yoonseo Choi, Taewhan Kim
2003	J	`jnl`	Minimum delay optimization for domino circuits - a coupling-aware approach. ACM Trans. Design Autom. Electr. Syst. Ki-Wook Kim, Seong-Ook Jung, Taewhan Kim, Sung-Mo Kang
2003	J	`jnl`	Synthesis of arithmetic circuits considering layout effects. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Junhyung Um, Taewhan Kim
2002	J	`jnl`	A Complete Model for Glitch Analysis in Logic Circuits. J. Circuits Syst. Comput. Ki-Seok Chung, Taewhan Kim, C. L. Liu
2002	A*	`conf`	Address assignment combined with scheduling in DSP code generation. DAC Yoonseo Choi, Taewhan Kim
2002	—	`conf`	Address code optimization using code scheduling for digital signal processors. ISCAS (5) Yoonseo Choi, Taewhan Kim
2002	—	`conf`	An efficient low-power binding algorithm in high-level synthesis. ISCAS (4) Yoonseo Choi, Taewhan Kim
2002	J	`jnl`	Binding Algorithm for Power Optimization Based on Network Flow Method. J. Circuits Syst. Comput. Yoonseo Choi, Taewhan Kim
2002	A	`conf`	Coupling-aware high-level interconnect synthesis for low power. ICCAD Chun-Gi Lyuh, Taewhan Kim, Ki-Wook Kim
2002	J	`jnl`	Domino logic synthesis based on implication graph. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ki-Wook Kim, Taewhan Kim, C. L. Liu, Sung-Mo Kang
2002	—	`conf`	Enhanced bus invert encodings for low-power. ISCAS (5) Unni Narayanan, Ki-Seok Chung, Taewhan Kim
2002	A*	`conf`	Layout-aware synthesis of arithmetic circuits. DAC Junhyung Um, Taewhan Kim
2002	A	`conf`	Layout-driven resource sharing in high-level synthesis. ICCAD Junhyung Um, Jae-Hoon Kim, Taewhan Kim
2002	J	`jnl`	Logic transformation for low-power synthesis. ACM Trans. Design Autom. Electr. Syst. Ki-Wook Kim, Taewhan Kim, TingTing Hwang, Sung-Mo Kang, C. L. Liu
2002	J	`jnl`	Synthesis and Optimization of Combinational Interface Circuits. J. VLSI Signal Process. Ki-Seok Chung, Rajesh K. Gupta, Taewhan Kim, C. L. Liu
2001	A	`conf`	A Router for Symmetrical FPGAs Based on Exact Routing Density Evaluation. ICCAD Nak-Woong Eum, Taewhan Kim, Chong-Min Kyung
2001	A*	`conf`	A Static Estimation Technique of Power Sensitivity in Logic Circuits. DAC Taewhan Kim, Ki-Seok Chung, Chien-Liang Liu
2001	—	`conf`	Accurate exploration of timing and area trade-offs in arithmetic optimization using carry-save-adders. ASP-DAC Youngtae Kim, Taewhan Kim
2001	A	`conf`	An Integrated Data Path Optimization for Low Power Based on Network Flow Method. ICCAD Chun-Gi Lyuh, Taewhan Kim, Chien-Liang Liu
2001	J	`jnl`	An Optimal Allocation of Carry-Save-Adders in Arithmetic Circuits. IEEE Trans. Computers Junhyung Um, Taewhan Kim
2001	—	`conf`	An accurate evaluation of routing density for symmetrical FPGAs. ACM Great Lakes Symposium on VLSI Nak-Woong Eum, Taewhan Kim, Chong-Min Kyung
2001	J	`jnl`	G-vector: A New Model for Glitch Analysis in Logic Circuits. J. VLSI Signal Process. Ki-Seok Chung, Taewhan Kim, C. L. Liu
2000	A*	`conf`	A fine-grained arithmetic optimization technique for high-performance/low-power data path synthesis. DAC Junhyung Um, Taewhan Kim, C. L. Liu
2000	J	`jnl`	A practical approach to the synthesis of arithmetic circuits usingcarry-save-adders. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Taewhan Kim, Junhyung Um
2000	—	`conf`	A timing-driven synthesis of arithmetic circuits using carry-save-adders (short paper). ASP-DAC Taewhan Kim, Junhyung Um
2000	J	`jnl`	An Accurate Exploration of Timing and Area Trade-Offs in Arithmetic Optimization Using Carry-Save-Adders. J. Circuits Syst. Comput. Youngtae Kim, Taewhan Kim
2000	J	`jnl`	An Integrated Approach to Data Path Synthesis for Behavioral-level Power Optimization. VLSI Design Chaeryung Park, Taewhan Kim, C. L. Liu
2000	—	`conf`	Behavioral-level partitioning for low power design in control-dominated application. ACM Great Lakes Symposium on VLSI Ki-Seok Chung, Taewhan Kim, Chien-Liang Liu
2000	J	`jnl`	Decomposition of Bus-Invert Coding for Low-Power I/O. J. Circuits Syst. Comput. Sungpack Hong, Taewhan Kim, Unni Narayanan, Ki-Seok Chung
1999	A	`conf`	Optimal allocation of carry-save-adders in arithmetic optimization. ICCAD Junhyung Um, Taewhan Kim, C. L. Liu
1998	A*	`conf`	Arithmetic Optimization Using Carry-Save-Adders. DAC Taewhan Kim, William Jao, Steven W. K. Tjiang
1998	J	`jnl`	Circuit optimization using carry-save-adder cells. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Taewhan Kim, William Jao, Steven W. K. Tjiang
1998	J	`jnl`	Register Allocation - A Hierarchical Reduction Approach. J. VLSI Signal Process. Chaeryung Park, Taewhan Kim, C. L. Liu
1996	J	`jnl`	An integrated algorithm for incremental data path synthesis. J. VLSI Signal Process. Taewhan Kim, C. L. Liu
1995	J	`jnl`	A new approach to the multiport memory allocation problem in data path synthesis. Integr. Taewhan Kim, C. L. Liu
1994	—	`conf`	A Stepwise Refinement Data Path Synthesis Procedure for Easy Testability. EDAC-ETC-EUROASIC Taewhan Kim, Ki-Seok Chung, Chien-Liang Liu
1994	J	`jnl`	A scheduling algorithm for conditional resource sharing-a hierarchical reduction approach. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Taewhan Kim, Noritake Yonezawa, Jane W.-S. Liu, C. L. Liu
1993	—	`conf`	Register allocation for data flow graphs with conditional branches and loops. EURO-DAC Chaeryung Park, Taewhan Kim, C. L. Liu
1993	A*	`conf`	Utilization of Multiport Memories in Data Path Synthesis. DAC Taewhan Kim, C. L. Liu
1991	A	`conf`	A Scheduling Algorithm for Conditional Resource Sharing. ICCAD Taewhan Kim, Jane W.-S. Liu, C. L. Liu