Taewhan Kim - RankMe

92 papers A* 8A 14B 1C 3Misc 2Journal 37Unranked 27

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	A 20-Gb/s/pin 0.42-pJ/b Single-Ended Receiver With Ping-Pong Self-Referencing Technique. IEEE Trans. Circuits Syst. II Express Briefs Seongcheol Kim, Changmin Sim, Seungwoo Park, Junseob So, Hwaseok Shin, Taewhan Kim, Seon-Been Lee, Chulwoo Kim
2026	—	`conf`	Enhancing Pin Accessibility Through Pin Pattern Migration and Optimization Across Cell Boundaries. ASP-DAC Hyunbae Seo, Sehyeon Chung, Taewhan Kim
2026	—	`conf`	Synthesis of CFET Standard Cells Utilizing Backside Interconnects Towards Improving Pin Accessibility. ASP-DAC Hyunbum Park, Taewhan Kim
2026	J	`jnl`	Utilization of standard cells with hybrid-threshold-voltage for timing and power optimization. Integr. Sehyeon Chung, Taewhan Kim
2025	—	`conf`	2nm GAA Cell Architecture Exploration Driven by Automated Standard Cell Layout Generator for Design-Technology Co-Optimization. SOCC Inhyeok Hwang, Ahreum Kim, Byungsu Kim, Seonil Choi, Handong Cho, Hyunbae Seo, Taewhan Kim
2025	A*	`conf`	CheckManual: A New Challenge and Benchmark for Manual-based Appliance Manipulation. CVPR Yuxing Long, Jiyao Zhang, Mingjie Pan, Tianshu Wu, Taewhan Kim, Hao Dong
2025	J	`jnl`	CheckManual: A New Challenge and Benchmark for Manual-based Appliance Manipulation. CoRR Yuxing Long, Jiyao Zhang, Mingjie Pan, Tianshu Wu, Taewhan Kim, Hao Dong
2025	A*	`conf`	Design and Technology Co-optimization Utilizing Flip-FET (FFET) Standard Cells. DAC Jaehoon Ahn, Taewhan Kim
2025	—	`conf`	EDA Tool Parameter Optimization Through Fast and Reliable Machine-Learning based Rank Prediction Model. MLCAD Doyeon Won, Taewhan Kim
2025	A*	`conf`	Late Breaking Results: Utilization of Hybrid Threshold-Voltage Flip-flops for Power Recovery. DAC Sehyeon Chung, Hyun-chul Hwang, Byung Su Kim, Jaeha Lee, Kunhyuk Kang, Taewhan Kim
2025	—	`conf`	Machine Learning Driven Early Clustering for Multi-bit Flip-Flop Allocation. MLCAD Jooyeon Jeong, Taewhan Kim
2025	—	`conf`	Machine-Learning Driven Cell Library Compaction. MLCAD Handong Cho, Taewhan Kim
2025	A	`conf`	ManipGPT: Is Affordance Segmentation by Large Vision Models Enough for Articulated Object Manipulation? IROS Taewhan Kim, Hojin Bae, Zeming Li, Xiaoqi Li, Iaroslav Ponomarenko, Ruihai Wu, Hao Dong
2025	J	`jnl`	Motif 2 12.7B technical report. CoRR Junghwan Lim, Sungmin Lee, Dongseok Kim, Tae-Hyun Kim, Eunhwan Park, Jeesoo Lee, Jeongdoo Lee, Junhyeok Lee, Wai Ting Cheung, Dahye Choi, Jaeheui Her, Jaeyeon Huh, Hanbin Jung, Changjin Kang, Beomgyu Kim, Minjae Kim, Taewhan Kim, Youngrok Kim, Hyukjin Kweon, Haesol Lee, Kungyu Lee, Dongpin Oh, Yeongjae Park, Bokki Ryu, Dongjoo Weon
2025	J	`jnl`	Motif-2-12.7B-Reasoning: A Practitioner's Guide to RL Training Recipes. CoRR Junghwan Lim, Sungmin Lee, Dongseok Kim, Taehyun Kim, Eunhwan Park, Jeesoo Lee, Jeongdoo Lee, Junhyeok Lee, Wai Ting Cheung, Dahye Choi, Minsu Ha, Jaeheui Her, Jaeyeon Huh, Hanbin Jung, Changjin Kang, Beomgyu Kim, Minjae Kim, Taewhan Kim, Youngrok Kim, Hyukjin Kweon, Haesol Lee, Kungyu Lee, Dongpin Oh, Yeongjae Park, Bokki Ryu, Dongjoo Weon
2025	—	`conf`	Optimizing Placement Legalization Utilizing Multiple Shapes of Standard Cells. SOCC Seoyoung Bang, Taewhan Kim
2025	A	`conf`	Simultaneous Optimization of Placement Legalization and Multi-bit Flip-flop Allocation in Physical Design Automation. ISLPED Seoyoung Bang, Taewhan Kim
2025	J	`jnl`	SynC: Synthetic Image Caption Dataset Refinement with One-to-many Mapping for Zero-shot Image Captioning. CoRR Si-Woo Kim, MinJu Jeon, Ye-Chan Kim, Soeun Lee, Taewhan Kim, Dong-Jin Kim
2025	C	`conf`	Threshold Voltage Tuning Technique for Leakage Power Recovery. ICCD Jaejoon Yoon, Taewhan Kim
2024	A*	`conf`	IFCap: Image-like Retrieval and Frequency-based Entity Filtering for Zero-shot Captioning. EMNLP Soeun Lee, Si-Woo Kim, Taewhan Kim, Dong-Jin Kim
2024	J	`jnl`	IFCap: Image-like Retrieval and Frequency-based Entity Filtering for Zero-shot Captioning. CoRR Soeun Lee, Si-Woo Kim, Taewhan Kim, Dong-Jin Kim
2024	J	`jnl`	ManipGPT: Is Affordance Segmentation by Large Vision Models Enough for Articulated Object Manipulation? CoRR Taewhan Kim, Hojin Bae, Zeming Li, Xiaoqi Li, Iaroslav Ponomarenko, Ruihai Wu, Hao Dong
2024	J	`jnl`	RAD: A Dataset and Benchmark for Real-Life Anomaly Detection with Robotic Observations. CoRR Kaichen Zhou, Yang Cao, Taewhan Kim, Hao Zhao, Hao Dong, Kai Ming Ting, Ye Zhu
2024	J	`jnl`	ViPCap: Retrieval Text-Based Visual Prompts for Lightweight Image Captioning. CoRR Taewhan Kim, Soeun Lee, Si-Woo Kim, Dong-Jin Kim
2022	J	`jnl`	Improving Speed of MUX-FSM-based Stochastic Computing for On-device Neural Networks. J. Comput. Sci. Eng. Jongsung Kang, Taewhan Kim
2022	—	`conf`	Neural Network Model for Detour Net Prediction. SLIP Jaehoon Ahn, Taewhan Kim
2021	J	`jnl`	Synthesis of representative critical path circuits considering BEOL variations for deep sub-micron circuits. Integr. Changho Han, Taewhan Kim
2020	A	`conf`	Deeper Weight Pruning without Accuracy Loss in Deep Neural Networks. DATE Byungmin Ahn, Taewhan Kim
2020	J	`jnl`	PV-MAC: Multiply-and-accumulate unit structure exploiting precision variability in on-device convolutional neural networks. Integr. Jongsung Kang, Taewhan Kim
2020	J	`jnl`	Sparsity Reduction Technique Using Grouping Method for Matrix Factorization in Differentially Private Recommendation Systems. IEICE Trans. Inf. Syst. Taewhan Kim, Kangsoo Jung, Seog Park
2019	A	`conf`	Allocation of State Retention Registers Boosting Practical Applicability to Power Gated Circuits. ICCAD Gyoung-Hwan Hyun, Taewhan Kim
2019	A	`conf`	Flip-flop State Driven Clock Gating: Concept, Design, and Methodology. ICCAD Gyoung-Hwan Hyun, Taewhan Kim
2018	—	`conf`	Clock buffer and flip-flop co-optimization for reducing peak current noise. ISQED Joohan Kim, Taewhan Kim
2018	—	`conf`	Energy-optimal dynamic voltage scaling in multicore platforms with reconfigurable power distribution network. ISQED Juyeon Kim, Taewhan Kim
2018	—	`conf`	Memory Access Driven Memory Layout and Block Replacement Techniques for Compressed Deep Neural Networks. SoCC Byungmin Ahn, Taewhan Kim
2018	J	`jnl`	Synthesis and exploration of clock spines. IET Comput. Digit. Tech. Youngchan Kim, Taewhan Kim
2017	—	`conf`	Algorithm for synthesis and exploration of clock spines. ASP-DAC Youngchan Kim, Taewhan Kim
2017	J	`jnl`	Boundary optimization of buffered clock trees for low power. Integr. Joohan Kim, Taewhan Kim
2017	J	`jnl`	Loosely coupled multi-bit flip-flop allocation for power reduction. Integr. Hyoungseok Moon, Taewhan Kim
2017	A	`conf`	Switch cell optimization of power-gated modern system-on-chips. ICCAD Dongyoun Yi, Taewhan Kim
2016	—	`conf`	Design and allocation of loosely coupled multi-bit flip-flops for power reduction in post-placement optimization. ASP-DAC Hyoungseok Moon, Taewhan Kim
2016	J	`jnl`	Grey-level context-driven histogram equalisation. IET Image Process. Hyoungjun Jeon, Taewhan Kim
2015	J	`jnl`	Context-driven hybrid image inpainting. IET Image Process. Lu Cai, Taewhan Kim
2015	—	`conf`	Useful clock skew scheduling using adjustable delay buffers in multi-power mode designs. ASP-DAC Juyeon Kim, Taewhan Kim
2014	J	`jnl`	Algorithms for TSV resource sharing and optimization in designing 3D stacked ICs. Integr. Byunghyun Lee, Taewhan Kim
2014	—	`conf`	Fast algorithm of low power image reformation for OLED display. ICDIP Myung Woo Lee, Taewhan Kim
2014	—	`conf`	Post-silicon tunable clock buffer allocation based on fast chip yield computation. ISQED Hyungjung Seo, Taewhan Kim
2013	—	`conf`	High-level TSV resource sharing and optimization for TSV based 3D IC designs. SoCC Byunghyun Lee, Taewhan Kim
2013	J	`jnl`	Statistical Viability Analysis for Detecting False Paths Under Delay Variation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jongyoon Jung, Taewhan Kim
2012	—	`conf`	Algorithm for synthesizing design context-aware fast carry-skip adders. ASP-DAC Kiyoung Kim, Taewhan Kim
2012	J	`jnl`	Algorithms for Combined Inter- and Intra-Task Dynamic Voltage Scaling. Comput. J. Hyungjung Seo, Jaewon Seo, Taewhan Kim
2012	J	`jnl`	Variation-Aware False Path Analysis Based on Statistical Dynamic Timing Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jongyoon Jung, Taewhan Kim
2011	—	`conf`	A fine-grained technique of NBTI-aware voltage scaling and body biasing for standard cell based designs. ASP-DAC Yongho Lee, Taewhan Kim
2011	—	`conf`	A fine-grained timing driven synthesis of arithmetic circuits. ISOCC Joohan Kim, Taewhan Kim
2011	—	`conf`	An optimal algorithm for allocation, placement, and delay assignment of adjustable delay buffers for clock skew minimization in multi-voltage mode designs. ASP-DAC Kyoung-Hwan Lim, Taewhan Kim
2011	J	`jnl`	Comprehensive Analysis and Control of Design Parameters for Power Gated Circuits. IEEE Trans. Very Large Scale Integr. Syst. Yongho Lee, Deog-Kyoon Jeong, Taewhan Kim
2011	J	`jnl`	Scheduling and Resource Binding Algorithm Considering Timing Variation. IEEE Trans. Very Large Scale Integr. Syst. Jongyoon Jung, Taewhan Kim
2010	—	`conf`	Clock buffer polarity assignment considering the effect of delay variations. ISQED Minseok Kang, Taewhan Kim
2010	J	`jnl`	HLS-l: A High-Level Synthesis Framework for Latch-Based Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Seungwhun Paik, Insup Shin, Taewhan Kim, Youngsoo Shin
2010	A	`conf`	Optimal algorithm for profile-based power gating: A compiler technique for reducing leakage on execution units in microprocessors. ICCAD Danbee Park, Jungseob Lee, Nam Sung Kim, Taewhan Kim
2010	J	`jnl`	Resource Sharing Problem of Timing Variation-Aware Task Scheduling and Binding in MPSoC. Comput. J. HaNeul Chon, Taewhan Kim
2010	—	`conf`	Technique for controlling power-mode transition noise in distributed sleep transistor network. ASP-DAC Yongho Lee, Taewhan Kim
2009	J	`jnl`	Autonomous temperature control technique in VLSI circuits through logic replication. IET Comput. Digit. Tech. Benjamin Carrión Schäfer, Taewhan Kim
2009	J	`jnl`	Interconnect and communication synthesis for distributed register-file microarchitecture. IET Comput. Digit. Tech. Kyoung-Hwan Lim, Yonghwan Kim, Taewhan Kim
2009	C	`conf`	Timing variation-aware high-level synthesis considering accurate yield computation. ICCD Jongyoon Jung, Taewhan Kim
2009	—	`conf`	Timing variation-aware task scheduling and binding for MPSoC. ASP-DAC HaNeul Chon, Taewhan Kim
2008	A	`conf`	Clock buffer polarity assignment combined with clock tree generation for power/ground noise minimization. ICCAD Yesin Ryu, Taewhan Kim
2008	J	`jnl`	Hotspots Elimination and Temperature Flattening in VLSI Circuits. IEEE Trans. Very Large Scale Integr. Syst. Benjamin Carrión Schäfer, Taewhan Kim
2008	J	`jnl`	Introduction to embedded systems week 2006 special issue. ACM Trans. Embed. Comput. Syst. Soonhoi Ha, Kiyoung Choi, Taewhan Kim, Krisztián Flautner, Sang Lyul Min, Wang Yi
2008	—	`conf`	Optimal allocation and placement of thermal sensors for reconfigurable systems and its practical extension. ASP-DAC Byunghyun Lee, Taewhan Kim
2008	A	`conf`	Power-gating-aware high-level synthesis. ISLPED Eunjoo Choi, Changsik Shin, Taewhan Kim, Youngsoo Shin
2008	A	`conf`	Simultaneous control of power/ground current, wakeup time and transistor overhead in power gated circuits. ICCAD Yongho Lee, Deog-Kyoon Jeong, Taewhan Kim
2008	—	`conf`	Timing variation-aware high level synthesis: Current results and research challenges. APCCAS Jongyoon Jung, Taewhan Kim
2007	C	`conf`	Address Code Optimization Exploiting Code Scheduling in DSP Applications. ISCAS Zhenmin Li, Taewhan Kim
2007	J	`jnl`	DC-DC Converter-Aware Power Management for Low-Power Embedded Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yongseok Choi, Naehyuck Chang, Taewhan Kim
2007	A*	`conf`	Interconnect and Communication Synthesis for Distributed Register-File Microarchitecture. DAC Kyoung-Hwan Lim, Yonghwan Kim, Taewhan Kim
2007	Misc	`ed.`	Proceedings of the 2007 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2007, Salzburg, Austria, September 30 - October 3, 2007 CASES Taewhan Kim, Pascal Sainrat, Steven S. Lumetta, Nacho Navarro
2007	B	`conf`	Temperature-Aware Compilation for VLIWProcessors. RTCSA Benjamin Carrión Schäfer, Yongho Lee, Taewhan Kim
2007	A	`conf`	Timing variation-aware high-level synthesis. ICCAD Jongyoon Jung, Taewhan Kim
2006	J	`jnl`	Optimal intratask dynamic voltage-scaling technique and its practical extensions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jaewon Seo, Taewhan Kim, Joonwon Lee
2006	Misc	`ed.`	Proceedings of the 2006 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2006, Seoul, Korea, October 22-25, 2006 CASES Seongsoo Hong, Wayne H. Wolf, Krisztián Flautner, Taewhan Kim
2006	J	`jnl`	Technique for Transition Energy-Aware Dynamic Voltage Assignment. IEEE Trans. Circuits Syst. II Express Briefs Jong-U. Shin, Taewhan Kim
2005	A*	`conf`	DC-DC converter-aware power management for battery-operated embedded systems. DAC Yongseok Choi, Naehyuck Chang, Taewhan Kim
2005	A	`conf`	Optimal integration of inter-task and intra-task dynamic voltage scaling techniques for hard real-time applications. ICCAD Jaewon Seo, Taewhan Kim, Nikil D. Dutt
2005	J	`jnl`	Optimal voltage allocation techniques for dynamically variable voltage processors. ACM Trans. Embed. Comput. Syst. Woo-Cheol Kwon, Taewhan Kim
2003	J	`jnl`	Bus Optimization for Low Power in High-Level Synthesis. J. Circuits Syst. Comput. Sungpack Hong, Taewhan Kim
2003	J	`jnl`	Memory allocation and mapping in high-level synthesis - an integrated approach. IEEE Trans. Very Large Scale Integr. Syst. Jaewon Seo, Taewhan Kim, Preeti Ranjan Panda
2003	A*	`conf`	Optimal voltage allocation techniques for dynamically variable voltage processors. DAC Woo-Cheol Kwon, Taewhan Kim
2002	A*	`conf`	An integrated algorithm for memory allocation and assignment in high-level synthesis. DAC Jaewon Seo, Taewhan Kim, Preeti Ranjan Panda
2002	—	`conf`	Memory exploration utilizing scheduling effects in high-level synthesis. ISCAS (4) Jaewon Seo, Taewhan Kim
2000	A	`conf`	A Methodology for Verifying Memory Access Protocols in Behavioral Synthesis. ICCAD Gernot Koch, Taewhan Kim, Reiner Genevriere
2000	A	`conf`	Bus Optimization for Low-Power Data Path Synthesis Based on Network Flow Method. ICCAD Sungpack Hong, Taewhan Kim