Taesik Na - RankMe

40 papers A* 4A 7B 4Journal 19Unranked 5

Year	Rank	Type	Title / Venue / Authors
2024	A*	`conf`	Mitigating Pooling Bias in E-commerce Search via False Negative Estimation. KDD Xiaochen Wang, Xiao Xiao, Ruhan Zhang, Xuan Zhang, Taesik Na, Tejaswi Tenneti, Haixun Wang, Fenglong Ma
2023	J	`jnl`	Mitigating Pooling Bias in E-commerce Search via False Negative Estimation. CoRR Xiaochen Wang, Xiao Xiao, Ruhan Zhang, Xuan Zhang, Taesik Na, Tejaswi Tenneti, Haixun Wang, Fenglong Ma
2023	J	`jnl`	Rethinking E-Commerce Search. CoRR Haixun Wang, Taesik Na
2023	J	`jnl`	Rethinking E-Commerce Search. SIGIR Forum Haixun Wang, Taesik Na
2022	J	`jnl`	An Embedding-Based Grocery Search Model at Instacart. CoRR Yuqing Xie, Taesik Na, Xiao Xiao, Saurav Manchanda, Young Rao, Zhihong Xu, Guanghua Shu, Esther Vasiete, Tejaswi Tenneti, Haixun Wang
2021	J	`jnl`	A Universal Modular Hybrid LDO With Fast Load Transient Response and Programmable PSRR in 14-nm CMOS Featuring Dynamic Clamp Strength Tuning. IEEE J. Solid State Circuits Xiaosen Liu, Harish K. Krishnamurthy, Taesik Na, Sheldon Weng, Khondker Zakir Ahmed, Christopher Schaef, Krishnan Ravichandran, James W. Tschanz, Vivek De
2020	J	`jnl`	Cross-Layer Noise Analysis in Smart Digital Pixel Sensors With Integrated Deep Neural Network. IEEE J. Emerg. Sel. Topics Circuits Syst. Minah Lee, Mandovi Mukherjee, Edward Lee, Priyabrata Saha, Mohammad Faisal Amir, Taesik Na, Saibal Mukhopadhyay
2020	—	`conf`	Effect of Process Variations in Digital Pixel Circuits on the Accuracy of DNN based Smart Sensor. AICAS Minah Lee, Mandovi Mukherjee, Priyabrata Saha, Mohammad Faisal Amir, Taesik Na, Saibal Mukhopadhyay
2020	A*	`conf`	Pushing the Limits of Narrow Precision Inferencing at Cloud Scale with Microsoft Floating Point. NeurIPS Bita Darvish Rouhani, Daniel Lo, Ritchie Zhao, Ming Liu, Jeremy Fowers, Kalin Ovtcharov, Anna Vinogradsky, Sarah Massengill, Lita Yang, Ray Bittner, Alessandro Forin, Haishan Zhu, Taesik Na, Prerak Patel, Shuai Che, Lok Chand Koppaka, Xia Song, Subhojit Som, Kaustav Das, Saurabh Tiwary, Steven K. Reinhardt, Sitaram Lanka, Eric S. Chung, Doug Burger
2020	A*	`conf`	WarningNet: A Deep Learning Platform for Early Warning of Task Failures under Input Perturbation for Reliable Autonomous Platforms. DAC Minah Lee, Burhan Ahmad Mudassar, Taesik Na, Saibal Mukhopadhyay
2019	A	`conf`	A Camera with Brain - Embedding Machine Learning in 3D Sensors. DATE Burhan Ahmad Mudassar, Priyabrata Saha, Yun Long, Mohammad Faisal Amir, Evan Gebhardt, Taesik Na, Jong Hwan Ko, Marilyn Wolf, Saibal Mukhopadhyay
2019	—	`conf`	A Modular Hybrid LDO with Fast Load-Transient Response and Programmable PSRR in 14nm CMOS Featuring Dynamic Clamp Tuning and Time-Constant Compensation. ISSCC Xiaosen Liu, Harish K. Krishnamurthy, Taesik Na, Sheldon Weng, Khondker Zakir Ahmed, Krishnan Ravichandran, James W. Tschanz, Vivek De
2019	A	`conf`	A Spatiotemporal Pre-processing Network for Activity Recognition under Rain. BMVC Minah Lee, Burhan Ahmad Mudassar, Taesik Na, Saibal Mukhopadhyay
2019	J	`jnl`	CAMEL: An Adaptive Camera With Embedded Machine Learning-Based Sensor Parameter Control. IEEE J. Emerg. Sel. Topics Circuits Syst. Burhan Ahmad Mudassar, Priyabrata Saha, Yun Long, Mohammad Faisal Amir, Evan Gebhardt, Taesik Na, Jong Hwan Ko, Marilyn Wolf, Saibal Mukhopadhyay
2019	J	`jnl`	Design and Analysis of a Neural Network Inference Engine Based on Adaptive Weight Compression. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jong Hwan Ko, Duckhwan Kim, Taesik Na, Saibal Mukhopadhyay
2019	B	`conf`	Mixture of Pre-processing Experts Model for Noise Robust Deep Learning on Resource Constrained Platforms. IJCNN Taesik Na, Minah Lee, Burhan Ahmad Mudassar, Priyabrata Saha, Jong Hwan Ko, Saibal Mukhopadhyay
2019	J	`jnl`	Mixture of Pre-processing Experts Model for Noise Robust Deep Learning on Resource Constrained Platforms. CoRR Taesik Na, Minah Lee, Burhan Ahmad Mudassar, Priyabrata Saha, Jong Hwan Ko, Saibal Mukhopadhyay
2018	A	`conf`	A ferroelectric FET based power-efficient architecture for data-intensive computing. ICCAD Yun Long, Taesik Na, Prakshi Rastogi, Karthik Rao, Asif Islam Khan, Sudhakar Yalamanchili, Saibal Mukhopadhyay
2018	J	`jnl`	An Energy-Quality Scalable Wireless Image Sensor Node for Object-Based Video Surveillance. IEEE J. Emerg. Sel. Topics Circuits Syst. Jong Hwan Ko, Taesik Na, Saibal Mukhopadhyay
2018	—	`conf`	Cascade Adversarial Machine Learning Regularized with a Unified Embedding. ICLR (Poster) Taesik Na, Jong Hwan Ko, Saibal Mukhopadhyay
2018	J	`jnl`	DeepTrain: A Programmable Embedded Platform for Training Deep Neural Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Duckhwan Kim, Taesik Na, Sudhakar Yalamanchili, Saibal Mukhopadhyay
2018	B	`conf`	Edge-Host Partitioning of Deep Neural Networks with Feature Space Encoding for Resource-Constrained Internet-of-Things Platforms. AVSS Jong Hwan Ko, Taesik Na, Mohammad Faisal Amir, Saibal Mukhopadhyay
2018	J	`jnl`	Edge-Host Partitioning of Deep Neural Networks with Feature Space Encoding for Resource-Constrained Internet-of-Things Platforms. CoRR Jong Hwan Ko, Taesik Na, Mohammad Faisal Amir, Saibal Mukhopadhyay
2018	—	`—`	Energy efficient, secure and noise robust deep learning for the internet of things. Taesik Na
2018	J	`jnl`	ReRAM-Based Processing-in-Memory Architecture for Recurrent Neural Network Acceleration. IEEE Trans. Very Large Scale Integr. Syst. Yun Long, Taesik Na, Saibal Mukhopadhyay
2017	J	`jnl`	A Single-Chip Image Sensor Node With Energy Harvesting From a CMOS Pixel Array. IEEE Trans. Circuits Syst. I Regul. Pap. Jong Hwan Ko, Mohammad Faisal Amir, Khondker Zakir Ahmed, Taesik Na, Saibal Mukhopadhyay
2017	A	`conf`	Adaptive weight compression for memory-efficient neural networks. DATE Jong Hwan Ko, Duckhwan Kim, Taesik Na, Jaeha Kung, Saibal Mukhopadhyay
2017	J	`jnl`	Cascade Adversarial Machine Learning Regularized with a Unified Embedding. CoRR Taesik Na, Jong Hwan Ko, Saibal Mukhopadhyay
2017	J	`jnl`	Clock Data Compensation Aware Digital Circuits Design for Voltage Margin Reduction. IEEE Trans. Circuits Syst. I Regul. Pap. Taesik Na, Jong Hwan Ko, Saibal Mukhopadhyay
2017	A	`conf`	Clock data compensation aware clock tree synthesis in digital circuits with adaptive clock generation. DATE Taesik Na, Jong Hwan Ko, Saibal Mukhopadhyay
2017	A*	`conf`	Design of an Energy-Efficient Accelerator for Training of Convolutional Neural Networks using Frequency-Domain Computation. DAC Jong Hwan Ko, Burhan Ahmad Mudassar, Taesik Na, Saibal Mukhopadhyay
2017	—	`conf`	Energy-efficient neural image processing for Internet-of-Things edge devices. MWSCAS Jong Hwan Ko, Yun Long, Mohammad Faisal Amir, Duckhwan Kim, Jaeha Kung, Taesik Na, Amit Ranjan Trivedi, Saibal Mukhopadhyay
2017	J	`jnl`	NeuroTrainer: An Intelligent Memory Module for Deep Learning Training. CoRR Duckhwan Kim, Taesik Na, Sudhakar Yalamanchili, Saibal Mukhopadhyay
2017	B	`conf`	On-chip training of recurrent neural networks with limited numerical precision. IJCNN Taesik Na, Jong Hwan Ko, Jaeha Kung, Saibal Mukhopadhyay
2016	B	`conf`	An energy-efficient wireless video sensor node with a region-of-interest based multi-parameter rate controller for moving object surveillance. AVSS Jong Hwan Ko, Taesik Na, Saibal Mukhopadhyay
2016	A	`conf`	Behavioral modeling of timing slack variation in digital circuits due to power supply noise. DATE Taesik Na, Saibal Mukhopadhyay
2016	A	`conf`	Speeding up Convolutional Neural Network Training with Dynamic Precision Scaling and Flexible Multiplier-Accumulator. ISLPED Taesik Na, Saibal Mukhopadhyay
2013	J	`jnl`	A 1.2 V 30 nm 3.2 Gb/s/pin 4 Gb DDR4 SDRAM With Dual-Error Detection and PVT-Tolerant Data-Fetch Scheme. IEEE J. Solid State Circuits Kyomin Sohn, Taesik Na, Indal Song, Yong Shim, Wonil Bae, Sanghee Kang, Dongsu Lee, Hangyun Jung, Seok-Hun Hyun, Hanki Jeoung, Ki Won Lee, Jun-Seok Park, Jongeun Lee, ByungHyun Lee, Inwoo Jun, Juseop Park, Junghwan Park, Hundai Choi, Sanghee Kim, Haeyoung Chung, Young Choi, Dae-Hee Jung, Byungchul Kim, Jung-Hwan Choi, Seong-Jin Jang, Chi-Wook Kim, Jung-Bae Lee, Joo-Sun Choi
2012	—	`conf`	A 1.2V 30nm 3.2Gb/s/pin 4Gb DDR4 SDRAM with dual-error detection and PVT-tolerant data-fetch scheme. ISSCC Kyomin Sohn, Taesik Na, Indal Song, Yong Shim, Wonil Bae, Sanghee Kang, Dongsu Lee, Hangyun Jung, Hanki Jeoung, Ki Won Lee, Junsuk Park, Jongeun Lee, ByungHyun Lee, Inwoo Jun, Juseop Park, Junghwan Park, Hundai Choi, Sanghee Kim, Haeyoung Chung, Young Choi, Dae-Hee Jung, Jang Seok Choi, Byung-Sick Moon, Jung-Hwan Choi, Byungchul Kim, Seong-Jin Jang, Joo-Sun Choi, Kyungseok Oh
2008	J	`jnl`	An ethernet switch architecture for bandwidth provision of broadband access networks. IEEE Commun. Mag. Jonghoon Lee, Chul-Ki Lee, Jiho Han, Hanku Chi, Taesik Na, Deog-Kyoon Jeong, Jae-Hwa Kwak, Jin-su Ahn, Sangho Yoon