Taeik Kim

24 papers Journal 5Unranked 19
YearRankTypeTitle / Venue / Authors
2021 — conf
Session 5 Overview: Analog Interfaces Analog Subcommittee.
ISSCC
Jens Anders, Taeik Kim, David T. Blaauw
2020 J jnl
A Programmable On-Chip Reference Oscillator With Slow-Wave Coplanar Waveguide in 14-nm FinFET CMOS.
IEEE Trans. Circuits Syst. II Express Briefs
Jeongho Hwang, Sang-Hyeok Chu, Gyu-Seob Jeong, Yeojoon Youn, Wooseok Kim, Taeik Kim, Deog-Kyoon Jeong
2019 — conf
A 5GHz 200kHz/5000ppm Spread-Spectrum Clock Generator with Calibration-Free Two-Point Modulation Using a Nested-Loop BBPLL.
CICC
Xiaohua Huang, Kunnong Zeng, Yuguang Liu, Woogeun Rhee, Taeik Kim, Zhihua Wang
2018 — conf
A 0.02mm
ISSCC
Kangyeop Choo, Hyunik Kim, Wooseok Kim, Jihyun F. Kim, Taeik Kim, Hyung Jong Ko
2018 — conf
A Crystal-Less Programmable Clock Generator with RC-LC Hybrid Oscillator for GHz Applications in 14 nm FinFET CMOS.
BCICTS
Jeongho Hwang, Gyu-Seob Jeong, Sang-Hyeok Chu, Wooseok Kim, Taeik Kim, Deog-Kyoon Jeong
2018 — conf
Session 19 overview: Sensors and interfaces: Analog subcommittee.
ISSCC
Man-Kay Law, Taeik Kim, Kofi A. A. Makinwa
2017 J jnl
A 0.015-mm
IEEE Trans. Circuits Syst. II Express Briefs
Gyu-Seob Jeong, Wooseok Kim, Jaejin Park, Taeik Kim, Hojin Park, Deog-Kyoon Jeong
2017 J jnl
A 2.4-GHz 1.5-mW Digital Multiplying Delay-Locked Loop Using Pulsewidth Comparator and Double Injection Technique.
IEEE J. Solid State Circuits
Hyunik Kim, Yongjo Kim, Taeik Kim, Hyung Jong Ko, SeongHwan Cho
2016 — conf
19.3 A 2.4GHz 1.5mW digital MDLL using pulse-width comparator and double injection technique in 28nm CMOS.
ISSCC
Hyunik Kim, Yongjo Kim, Taeik Kim, Hojin Park, SeongHwan Cho
2015 — conf
14.4 A 5GHz -95dBc-reference-Spur 9.5mW digital fractional-N PLL using reference-multiplied time-to-digital converter and reference-spur cancellation in 65nm CMOS.
ISSCC
Hyojun Kim, Jinwoo Sang, Hyunik Kim, Youngwoo Jo, Taeik Kim, Hojin Park, SeongHwan Cho
2015 — conf
14.8 A 0.009mm
ISSCC
Minyoung Song, Taeik Kim, Jihyun F. Kim, Wooseok Kim, Sung-Jin Kim, Hojin Park
2015 — conf
15.5 A 0.6V 1.17ps PVT-tolerant and synthesizable time-to-digital converter using stochastic phase interpolation with 16× spatial redundancy in 14nm FinFET technology.
ISSCC
Sung-Jin Kim, Wooseok Kim, Minyoung Song, Jihyun F. Kim, Taeik Kim, Hojin Park
2015 J jnl
A 0.35-0.5-V 18-152 MHz Digitally Controlled Relaxation Oscillator With Adaptive Threshold Calibration in 65-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs
Yudong Zhang, Woogeun Rhee, Taeik Kim, Hojin Park, Zhihua Wang
2015 — conf
A 72μW, 2.4GHz, 11.7% tuning range, 212dBc/Hz FoM LC-VCO in 65nm CMOS.
CICC
Joo-Myoung Kim, Jae-Seung Lee, Sun-a Kim, Taeik Kim, Hojin Park, Sang-Gug Lee
2014 — conf
15.2 A 0.012mm
ISSCC
Jenlung Liu, Tae-Kwang Jang, Yonghee Lee, Jungeun Shin, Seunghoon Lee, Taeik Kim, Jaejin Park, Hojin Park
2014 — conf
A 0.010mm
CICC
Kangyeop Choo, Sung-Jin Kim, Wooseok Kim, Jihyun F. Kim, Taeik Kim, Hojin Park
2014 — conf
A 0.63ps, 12b, synchronous cyclic TDC using a time adder for on-chip jitter measurement of a SoC in 28nm CMOS technology.
VLSIC
Sung-Jin Kim, Taeik Kim, Hojin Park
2013 — conf
A 0.026mm
ISSCC
Tae-Kwang Jang, Nan Xing, Frank Liu, Jungeun Shin, Hyungreal Ryu, Jihyun F. Kim, Taeik Kim, Jaejin Park, Hojin Park
2013 — conf
A 0.032mm
ISSCC
Wooseok Kim, Jaejin Park, Jihyun F. Kim, Taeik Kim, Hojin Park, Deog-Kyoon Jeong
2012 — conf
A 0.004mm
ISSCC
Jong-Phil Hong, Sung-Jin Kim, Jenlung Liu, Nan Xing, Tae-Kwang Jang, Jaejin Park, Jihyun F. Kim, Taeik Kim, Hojin Park
2004 — conf
A tunable transmission line phase shifter (TTPS).
ISCAS (1)
Taeik Kim, David J. Allstot
2004 J jnl
Compact model generation for on-chip transmission lines.
IEEE Trans. Circuits Syst. I Regul. Pap.
Taeik Kim, Xiaoyong Li, David J. Allstot
2003 — conf
Accurate compact model extraction for on-chip coplanar waveguides.
ISCAS (4)
Taeik Kim, Xiaoyong Li, David J. Allstot
2003 — conf
On-chip inductor structures: a comparative study.
ISCAS (1)
Srinivas Kodali, Taeik Kim, David J. Allstot