Taehyoun Oh

12 papers Journal 9Unranked 3
YearRankTypeTitle / Venue / Authors
2026 J jnl
A DTC-Based Snapshot ADPLL With Feedforward Fractional Spur Cancellation and Asynchronous Duty-Modulation Dithering DCO Achieving-71.6 dBc Fractional Spur in 65-nm CMOS Process.
IEEE Access
Kihoon Kwon, Sangwon Kim, Minseo Park, Jinhyuk Ahn, Gahyeon Lee, Joonho Gil, Chulhyun Park, Yunseong Eo, Hyungkyu Choi, Chulho Kang, Eun Seong Kim, Nam-Young Kim, Ramesh Harjani, Taehyoun Oh
2025 J jnl
A 8.9 to 10-GHz -97.86-dBc Reference Spur Pulser-Free Continuous Charge Pump Sub-Sampling PLL With Fine-Tunable Dead-Zone Generator in 65-nm CMOS Process.
IEEE Access
Sangwon Kim, Kihoon Kwon, Minseo Park, Jinhyuk Ahn, Junseo Kim, Joonho Gil, Chulhyun Park, Yunseong Eo, Ramesh Harjani, Taehyoun Oh
2024 J jnl
A 3.5 to 4.7-GHz Fractional-N ADPLL With a Low-Power Time-Interleaved GRO-TDC of 6.2-ps Resolution in 65-nm CMOS Process.
IEEE Access
Kyoung-Ub Cho, Joonho Gil, Chulhyun Park, Kyu-Jin Cho, Jae-Woo Shin, Eun Seong Kim, Yun Seong Eo, Ramesh Harjani, Nam-Young Kim, Taehyoun Oh
2023 J jnl
A Highly Integrated Radio Frequency Receiver RF CMOS Module for Core Body Temperature Thermometer.
IEEE Access
IkHwan Kim, Won Il Jang, Hyeon-Sik Hwang, Byeong-Jae Seo, Dong-Min Lee, Ji-Ho Han, Jae-Woo Shin, Young-Ro Yoon, Taehyoun Oh, Hyung-Chul Park, Eun Seong Kim, Yun Seong Eo, Nam-Young Kim
2022 J jnl
Linear Characteristic Analysis of High-Resolution Counter-Based Frequency Detector in Type-I Digital PLL.
IEEE Trans. Circuits Syst. II Express Briefs
Taehyoun Oh, Joonho Gil, Ramesh Harjani
2022 J jnl
Pseudo-Reference Counter-Based FLL for 6 Gb/s Reference-Less CDR in 65-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs
Sanggeun Lee, Ramesh Harjani, Taehyoun Oh
2016 — conf
A 4.1mA adaptive duty-cycle corrector loop with background calibration in 45nm CMOS process.
ISOCC
Esther Kim, Deokgwan Jeong, Taehyoun Oh
2014 J jnl
A 4Gb/s, 370µA low-power Tx FIR driver for LPDDR4 applications.
IEICE Electron. Express
Taehyoun Oh, Myung Chul Park, Yun Seong Eo
2013 J jnl
A 12-Gb/s Multichannel I/O Using MIMO Crosstalk Cancellation and Signal Reutilization in 65-nm CMOS.
IEEE J. Solid State Circuits
Taehyoun Oh, Ramesh Harjani
2012 — conf
4×12 Gb/s 0.96 pJ/b/lane analog-IIR crosstalk cancellation and signal reutilization receiver for single-ended I/Os in 65 nm CMOS.
VLSIC
Taehyoun Oh, Ramesh Harjani
2011 J jnl
A 6-Gb/s MIMO Crosstalk Cancellation Scheme for High-Speed I/Os.
IEEE J. Solid State Circuits
Taehyoun Oh, Ramesh Harjani
2010 — conf
A 5Gb/s 2×2 MIMO crosstalk cancellation scheme for high-speed I/Os.
CICC
Taehyoun Oh, Ramesh Harjani