| Year | Rank | Type | Title / Venue / Authors |
|---|---|---|---|
| 2020 | C | conf |
PACLIC
|
| 2014 | — | conf |
A 48 fJ/CS, 74 dB SNDR, 87 dB SFDR, 85 dB THD, 30 MS/s pipelined ADC using hybrid dynamic amplifier.
VLSIC
|
| 2014 | J | jnl |
IEEE J. Solid State Circuits
|
| 2013 | J | jnl |
IEEE J. Solid State Circuits
|
| 2013 | — | conf |
CICC
|
| 2012 | — | conf |
VLSIC
|
| 2012 | — | conf |
VLSIC
|
| 2012 | C | conf |
ISCAS
|
| 2012 | C | conf |
ISCAS
|
| 2012 | C | conf |
ISCAS
|
| 2011 | J | jnl |
IEEE Trans. Circuits Syst. II Express Briefs
|