Taeho Seong

20 papers Journal 11Unranked 9
YearRankTypeTitle / Venue / Authors
2024 J jnl
A 12.8-15.0-GHz Low-Jitter Fractional-N Subsampling PLL Using a Voltage-Domain Quantization-Error Cancellation.
IEEE J. Solid State Circuits
Juyeop Kim, Yongwoo Jo, Hangi Park, Taeho Seong, Younghyun Lim, Jaehyouk Choi
2022 — conf
A 188fsrms-Jitter and -243d8-FoMjitter 5.2GHz-Ring-DCO-Based Fractional-N Digital PLL with a 1/8 DTC-Range-Reduction Technique Using a Quadruple-Timing-Margin Phase Selector.
ISSCC
Chanwoong Hwang, Hangi Park, Taeho Seong, Jaehyouk Choi
2022 J jnl
A Low-Jitter Ring-DCO-Based Fractional-N Digital PLL With a 1/8 DTC-Range-Reduction Technique Using a Quadruple-Timing-Margin Phase Selector.
IEEE J. Solid State Circuits
Hangi Park, Chanwoong Hwang, Taeho Seong, Jaehyouk Choi
2022 J jnl
A Low-Jitter and Low-Fractional-Spur Ring-DCO-Based Fractional-N Digital PLL Using a DTC's Second-/Third-Order Nonlinearity Cancellation and a Probability-Density-Shaping ΔΣM.
IEEE J. Solid State Circuits
Chanwoong Hwang, Hangi Park, Yongsun Lee, Taeho Seong, Jaehyouk Choi
2021 — conf
32.4 A 104fsrms-Jitter and -61dBc-Fractional Spur 15GHz Fractional-N Subsampling PLL Using a Voltage-Domain Quantization-Error Cancelation Technique.
ISSCC
Juyeop Kim, Yongwoo Jo, Younghyun Lim, Taeho Seong, Hangi Park, Seyeon Yoo, Yongsun Lee, Seojin Choi, Jaehyouk Choi
2021 — conf
A 365fsrms-Jitter and -63dBc-Fractional Spur 5.3GHz-Ring-DCO-Based Fractional-N DPLL Using a DTC Second/Third- Order Nonlinearity Cancelation and a Probability-Density-Shaping Δ ΣM.
ISSCC
Hangi Park, Chanwoong Hwang, Taeho Seong, Yongsun Lee, Jaehyouk Choi
2021 J jnl
A Low-Jitter and Low-Reference-Spur Ring-VCO- Based Injection-Locked Clock Multiplier Using a Triple-Point Background Calibrator.
IEEE J. Solid State Circuits
Seyeon Yoo, Seojin Choi, Yongsun Lee, Taeho Seong, Younghyun Lim, Jaehyouk Choi
2020 — conf
17.1 A -240dB-FoMjitter and -115dBc/Hz PN @ 100kHz, 7.7GHz Ring-DCO-Based Digital PLL Using P/I-Gain Co-Optimization and Sequence-Rearranged Optimally Spaced TDC for Flicker-Noise Reduction.
ISSCC
Yongsun Lee, Taeho Seong, Jeonghyun Lee, Chanwoong Hwang, Hangi Park, Jaehyouk Choi
2020 — conf
17.3 A -58dBc-Worst-Fractional-Spur and -234dB-FoMjitter, 5.5GHz Ring-DCO-Based Fractional-N DPLL Using a Time-Invariant-Probability Modulator, Generating a Nonlinearity-Robust DTC-Control Word.
ISSCC
Taeho Seong, Yongsun Lee, Chanwoong Hwang, Jeonghyun Lee, Hangi Park, Kyuho Jason Lee, Jaehyouk Choi
2019 — conf
A 140fsrms-Jitter and -72dBc-Reference-Spur Ring-VCO-Based Injection-Locked Clock Multiplier Using a Background Triple-Point Frequency/Phase/Slope Calibrator.
ISSCC
Seyeon Yoo, Seojin Choi, Yongsun Lee, Taeho Seong, Younghyun Lim, Jaehyouk Choi
2019 J jnl
A 320-fs RMS Jitter and - 75-dBc Reference-Spur Ring-DCO-Based Digital PLL Using an Optimal-Threshold TDC.
IEEE J. Solid State Circuits
Taeho Seong, Yongsun Lee, Seyeon Yoo, Jaehyouk Choi
2019 — conf
A 76fsrms Jitter and -40dBc Integrated-Phase-Noise 28-to-31GHz Frequency Synthesizer Based on Digital Sub-Sampling PLL Using Optimally Spaced Voltage Comparators and Background Loop-Gain Optimization.
ISSCC
Juyeop Kim, Heein Yoon, Younghyun Lim, Yongsun Lee, Yoonseo Cho, Taeho Seong, Jaehyouk Choi
2019 J jnl
An Ultra-Low-Jitter, mmW-Band Frequency Synthesizer Based on Digital Subsampling PLL Using Optimally Spaced Voltage Comparators.
IEEE J. Solid State Circuits
Juyeop Kim, Younghyun Lim, Heein Yoon, Yongsun Lee, Hangi Park, Yoonseo Cho, Taeho Seong, Jaehyouk Choi
2018 — conf
A -242dB FOM and -75dBc-reference-spur ring-DCO-based all-digital PLL using a fast phase-error correction technique and a low-power optimal-threshold TDC.
ISSCC
Taeho Seong, Yongsun Lee, Seyeon Yoo, Jaehyouk Choi
2018 J jnl
A Low-Jitter and Low-Reference-Spur Ring-VCO-Based Switched-Loop Filter PLL Using a Fast Phase-Error Correction Technique.
IEEE J. Solid State Circuits
Yongsun Lee, Taeho Seong, Seyeon Yoo, Jaehyouk Choi
2018 — conf
A switched-loop-filter PLL with fast phase-error correction technique.
ASP-DAC
Yongsun Lee, Taeho Seong, Seyeon Yoo, Jaehyouk Choi
2016 J jnl
A Low-Jitter and Fractional-Resolution Injection-Locked Clock Multiplier Using a DLL-Based Real-Time PVT Calibrator With Replica-Delay Cells.
IEEE J. Solid State Circuits
Mina Kim, Seojin Choi, Taeho Seong, Jaehyouk Choi
2015 J jnl
A Low Phase Noise Injection-Locked Programmable Reference Clock Multiplier With a Two-Phase PVT-Calibrator for ΔΣ PLLs.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yongsun Lee, Mina Kim, Taeho Seong, Jaehyouk Choi
2015 J jnl
Analysis and Design of a Core-Size-Scalable Low Phase Noise LC-VCO for Multi-Standard Cellular Transceivers.
IEEE Trans. Circuits Syst. I Regul. Pap.
Taeho Seong, Jae Joon Kim, Jaehyouk Choi
2014 J jnl
Ultralow In-Band Phase Noise Injection-Locked Frequency Multiplier Design Based on Open-Loop Frequency Calibration.
IEEE Trans. Circuits Syst. II Express Briefs
Taeho Seong, Yongsun Lee, Jaehyouk Choi