Tadeusz Kwasniewski

18 papers Journal 6Unranked 12
YearRankTypeTitle / Venue / Authors
2016 J jnl
A reduced reference spur multiplying delay-locked loop.
Int. J. Circuit Theory Appl.
Xinjie Wang, Tadeusz Kwasniewski
2015 — conf
A DLL fractional M/N frequency synthesizer.
CCECE
Haizheng Guo, Tadeusz Kwasniewski
2015 — conf
A DLL-based period synthesis.
CCECE
Haizheng Guo, Tadeusz Kwasniewski
2015 — conf
Low noise CMOS voltage-control oscillator design methodology with emphasis on non-linear effect contributions, 2.4 GHz CMOS design example.
CCECE
Zhe Jiang, Haizheng Guo, Tadeusz Kwasniewski
2013 — conf
Spur analysis and reduction of edge combining DLL-based frequency multiplier.
CCECE
Haizheng Guo, Xinjie Wang, Tadeusz Kwasniewski
2012 — conf
A novel fractional-N PLL architecture with hybrid of DCO and VCO.
CCECE
Chao He, Tadeusz Kwasniewski
2012 — conf
Bang-Bang CDR's acquisition, locking, and jitter tolerance.
CCECE
Chao He, Tadeusz Kwasniewski
2009 — conf
A Simulator for High-Speed Backplane Transceivers.
UKSim
Dianyong Chen, Bo Wang, Bangli Liang, Tadeusz Kwasniewski
2009 J jnl
FIR filter optimization using bit-edge equalization in high-speed backplane data transmission.
Microelectron. J.
Lei Zhang, Tadeusz Kwasniewski
2009 — conf
Modeling, Simulation and Analysis of High-Speed Serial Link Transceiver over Band-Limited Channel.
UKSim
Bo Wang, Dianyong Chen, Bangli Liang, Jinguang Jiang, Tadeusz Kwasniewski
2008 — conf
Phase Noise Simulation and Modeling of ADPLL by SystemVerilog.
BMAS
Tingjun Wen, Tadeusz Kwasniewski
2007 J jnl
Design Considerations for a Direct RF Sampling Mixer.
IEEE Trans. Circuits Syst. II Express Briefs
Dianyong Chen, Wei Wang, Tadeusz Kwasniewski
2007 — conf
Dual Mode K-Best MIMO Detector Architecture and VLSI Implementation.
ICECS
Ramin Shariat-Yazdi, Tadeusz Kwasniewski
2005 — conf
Behavioral test benches for digital clock and data recovery circuits using Verilog-A.
CICC
S. I. Ahmed, Kent Orthner, Tadeusz Kwasniewski
2005 — conf
Design considerations for 2nd-order and 3rd-order bang-bang CDR loops.
CICC
Shoujun Wang, Haitao Mei, Mashkoor Baig, William Bereza, Tadeusz Kwasniewski, Rakesh H. Patel
2001 J jnl
A 1.25-GHz 0.35-μm monolithic CMOS PLL based on a multiphase ring oscillator.
IEEE J. Solid State Circuits
Lizhong Sun, Tadeusz Kwasniewski
1997 J jnl
CMOS VCO's for PLL frequency synthesis in GHz digital mobile radio communications.
IEEE J. Solid State Circuits
Manop Thamsirianunt, Tadeusz Kwasniewski
1995 J jnl
CMOS high-speed dual-modulus frequency divider for RF frequency synthesis.
IEEE J. Solid State Circuits
Navid Foroudi, Tadeusz Kwasniewski