Tadayoshi Horita

24 papers C 2Misc 4Journal 9Unranked 9
YearRankTypeTitle / Venue / Authors
2016 J jnl
A Built-in Self-repair Circuit for Restructuring Mesh-Connected Processor Arrays by Direct Spare Replacement.
Trans. Comput. Sci.
Itsuo Takanami, Tadayoshi Horita, Masakazu Akiba, Mina Terauchi, Tsuneo Kanno
2015 J jnl
An FPGA-Based Multiple-Weight-and-Neuron-Fault Tolerant Digital Multilayer Perceptron (Full Version).
Trans. Comput. Sci.
Tadayoshi Horita, Itsuo Takanami, Masakazu Akiba, Mina Terauchi, Tsuneo Kanno
2014 — conf
A GPGPU-Based Acceleration of Fault-Tolerant MLP Learnings.
MCSoC
Tadayoshi Horita, Itsuo Takanami, Masakazu Akiba, Mina Terauchi, Tsuneo Kanno
2014 J jnl
Multilayer Perceptrons Which Are Tolerant to Multiple Faults and Learnings to Realize Them.
Trans. Comput. Sci.
Tadayoshi Horita, Itsuo Takanami, Kazuhiro Nishimura
2013 J jnl
An FPGA-based multiple-weight-and-neuron-fault tolerant digital multilayer perceptron.
Neurocomputing
Tadayoshi Horita, Itsuo Takanami
2012 C conf
A Built-in Circuit for Self-Repairing Mesh-Connected Processor Arrays by Direct Spare Replacement.
PRDC
Itsuo Takanami, Tadayoshi Horita
2011 J jnl
An FPGA-Based Fault-Tolerant 2D Systolic Array for Matrix Multiplications.
Trans. Comput. Sci.
Tadayoshi Horita, Itsuo Takanami
2010 J jnl
An FPGA-based fast classifier with high generalization property.
SIGARCH Comput. Archit. News
Tadayoshi Horita, Itsuo Takanami
2009 Misc conf
A Computer Cluster for Tests of Parallel Programming Environments Including Operating Systems.
PDPTA
Tadayoshi Horita, Koichi Kitano, Koji Teramoto
2009 Misc conf
An Implementation of a Fault-Tolerant 2D Systolic Array on FPGAs and Its Evaluation.
PDPTA
Tadayoshi Horita, Itsuo Takanami
2009 Misc conf
Novel Value Injection Learning Methods Which Make Multilayer Neural Networks Multiple-Weight-and-Neuron-Fault Tolerant.
PDPTA
Kazuhiro Nishimura, Tadayoshi Horita, Masato Otsu, Itsuo Takanami
2008 J jnl
An Analysis for Fault-Tolerant 3D Processor Arrays Using 1.5-Track Switches.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Tadayoshi Horita, Yuuji Katou, Itsuo Takanami
2008 J jnl
Learning Algorithms Which Make Multilayer Neural Networks Multiple-Weight-and-Neuron-Fault Tolerant.
IEICE Trans. Inf. Syst.
Tadayoshi Horita, Itsuo Takanami, Masatoshi Mori
2006 — conf
A Multiple-Weight-and-Neuron-Fault Tolerant Digital Multilayer Neural Network.
DFT
Tadayoshi Horita, Takurou Murata, Itsuo Takanami
2001 C conf
Analytical Results for Reconfiguration of E-11/2- Track Switch Torus Arrays with Multiple Fault Types.
PRDC
Tadayoshi Horita, Itsuo Takanami
2000 Misc conf
A System for Efficiently Self-Reconstructing 1½-Track Switch Torus Arrays.
PDPTA
Tadayoshi Horita, Itsuo Takanami
2000 — conf
A System for Efficiently Self-Reconstructing E-1½-Track Switch Torus Arrays.
ISPAN
Tadayoshi Horita, Itsuo Takanami
2000 J jnl
Fault-Tolerant Processor Arrays Based on the 1½-Track Switches with Flexible Spare Distributions.
IEEE Trans. Computers
Tadayoshi Horita, Itsuo Takanami
1999 — conf
Fault Tolerant Processor Arrays Based on 1 1/2-Track Switch with Generalized Spare Distributions.
ISPAN
Tadayoshi Horita, Itsuo Takanami
1997 — conf
A Polynomial Time Algorithm for Reconfiguring the 1 1/2 Track-Switch Model with PE and Bus faults.
ISPAN
Tadayoshi Horita, Itsuo Takanami
1997 — conf
A built-in self-reconfigurable scheme for 3D mesh arrays.
ISPAN
Itsuo Takanami, Tadayoshi Horita
1997 — conf
Self-reconstruction of mesh-arrays with 1 1/2 -track switches by digital neural circuits.
DFT
Itsuo Takanami, Tadayoshi Horita
1996 — conf
Reconfiguration of 1 1/2 track-switch mesh-arrays with PE and bus faults.
DFT
Tadayoshi Horita, Itsuo Takanami
1995 — conf
Reconfigurable architectures for mesh-arrays with PE and link faults.
DFT
Itsuo Takanami, Tadayoshi Horita