Tadashi Shibata

106 papers A 1B 1C 17Misc 3Journal 28Unranked 56
YearRankTypeTitle / Venue / Authors
2016 J jnl
A Nearest Neighbor Classifier Employing Critical Boundary Vectors for Efficient On-Chip Template Reduction.
IEEE Trans. Neural Networks Learn. Syst.
Wenjun Xia, Yoshio Mita, Tadashi Shibata
2014 J jnl
A Real-Time Motion-Feature-Extraction VLSI Employing Digital-Pixel-Sensor-Based Parallel Architecture.
IEEE Trans. Circuits Syst. Video Technol.
Hongbo Zhu, Tadashi Shibata
2014 C conf
A single-chip 600-fps real-time action recognition system employing a hardware friendly algorithm.
ISCAS
Zuoxun Hou, Hongbo Zhu, Nanning Zheng, Tadashi Shibata
2014 J jnl
Unsupervised Object Extraction by Contour Delineation and Texture Discrimination Based on Oriented Edge Features.
IEEE Trans. Circuits Syst. Video Technol.
Litian Sun, Tadashi Shibata
2013 J jnl
A Directional-Edge-Based Real-Time Object Tracking System Employing Multiple Candidate-Location Generation.
IEEE Trans. Circuits Syst. Video Technol.
Pushe Zhao, Hongbo Zhu, He Li, Tadashi Shibata
2013 C conf
A VLSI DBSCAN processor composed as an array of micro agents having self-growing interconnects.
ISCAS
Atsushi Shimada, Hongbo Zhu, Tadashi Shibata
2013 J jnl
A hardware friendly algorithm for action recognition using spatio-temporal motion-field patches.
Neurocomputing
Ruihan Bao, Tadashi Shibata
2013 C conf
A multiple-candidate-regeneration-based object tracking system with enhanced learning capability by nearest neighbor classifier.
ISCAS
Pushe Zhao, Hongbo Zhu, Tadashi Shibata
2013 C conf
An MTJ-based nonvolatile associative memory architecture with intelligent power-saving scheme for high-speed low-power recognition applications.
ISCAS
Yitao Ma, Tadashi Shibata, Tetsuo Endoh
2012 — conf
A Hierarchical Action Recognition System Applying Fisher Discrimination Dictionary Learning via Sparse Representation.
ICAISC (1)
Ruihan Bao, Tadashi Shibata
2012 C conf
A real-time motion-feature-extraction image processor employing digital-pixel-sensor-based parallel architecture.
ISCAS
Hongbo Zhu, Tadashi Shibata
2012 — conf
Real-Time Object Tracking Algorithm Employing On-Line Support Vector Machine and Multiple Candidate Regeneration.
ICAISC (1)
Pushe Zhao, Renyuan Zhang, Tadashi Shibata
2012 — conf
Real-Time On-Line-Learning Support Vector Machine Based on a Fully-Parallel Analog VLSI Processor.
ICAISC (2)
Renyuan Zhang, Tadashi Shibata
2012 Misc conf
Scene image recognition based on the sequence of local image vectors represented by oriented edges.
ICASSP
Shigetaka Morikawa, Tadashi Shibata
2012 C conf
Self-adaptive quasi-Gaussian circuits for analog on-chip-trainable multi-class classifiers.
ISCAS
Wenjun Xia, Tadashi Shibata
2012 — conf
Translation-invariant motion perception for multiple objects using grid partitioning representation.
ICSPCS
Mio Nishiyama, Tadashi Shibata
2012 — conf
Unsupervised object extraction by contour delineation and texture-based discrimination.
EUSIPCO
Litian Sun, Tadashi Shibata
2011 — conf
A dominant-noise discrimination system for images corrupted by content-independent noises without a priori references.
ICSPCS
Robert Grou-Szabo, Tadashi Shibata
2011 — conf
A vertical-MOSFET-based digital core circuit for high-speed low-power vector matching.
ISOCC
Yitao Ma, Tetsuo Endoh, Tadashi Shibata
2011 — conf
Critical Boundary Vector Concept in Nearest Neighbor Classifiers using k-Means Centers for Efficient Template Reduction.
IJCCI (NCTA)
Wenjun Xia, Tadashi Shibata
2011 — conf
Spatio-temporal motion field descriptors for the hierarchical action recognition system.
ICSPCS
Ruihan Bao, Tadashi Shibata
2010 — conf
A Low-Power Associative Processor with the R-th Nearest-Match Hamming-Distance Search Engine Employing Time-Domain Techniques.
DELTA
Trong Tu Bui, Tadashi Shibata
2010 J jnl
A Neuron-MOS-Based VLSI Implementation of Pulse-Coupled Neural Networks for Image Feature Generation.
IEEE Trans. Circuits Syst. I Regul. Pap.
Jun Chen, Tadashi Shibata
2010 C conf
A row-parallel cyclic-line-access edge detection CMOS image sensor employing global thresholding operation.
ISCAS
Norihiro Takahashi, Tadashi Shibata
2010 C conf
A self-learning multiple-class classifier using multi-dimensional quasi-Gaussian analog circuits.
ISCAS
Zhuoli Sun, Kyunghee Kang, Tadashi Shibata
2010 J jnl
An Ego-Motion Detection System Employing Directional-Edge-Based Motion Field Representations.
IEICE Trans. Inf. Syst.
Jia Hao, Tadashi Shibata
2010 J jnl
An On-Chip-Trainable Gaussian-Kernel Analog Support Vector Machine.
IEEE Trans. Circuits Syst. I Regul. Pap.
Kyunghee Kang, Tadashi Shibata
2010 J jnl
Block-matching-based motion field generation utilizing directional edge displacement.
Comput. Electr. Eng.
Hitoshi Hayakawa, Tadashi Shibata
2010 C conf
Directional-edge-based object tracking employing on-line learning and regeneration of multiple candidate locations.
ISCAS
Hongbo Zhu, Pushe Zhao, Tadashi Shibata
2009 J jnl
A Computational Digital Pixel Sensor Featuring Block-Readout Architecture for On-Chip Image Processing.
IEEE Trans. Circuits Syst. I Regul. Pap.
Kiyoto Ito, Benjamas Tongprasit, Tadashi Shibata
2009 — conf
A Non-subtraction Configuration of Self-similitude Architecture for Multiple-Resolution Edge-Filtering CMOS Image Sensor.
ICANN (1)
Norihiro Takahashi, Tadashi Shibata
2009 J jnl
A Pixel-Parallel Self-Similitude Processing for Multiple-Resolution Edge-Filtering Analog Image Sensors.
IEEE Trans. Circuits Syst. I Regul. Pap.
Norihiro Takahashi, Kazuhide Fujita, Tadashi Shibata
2009 C conf
A Real-time Image Feature Vector Generator Employing Functional Cache Memory for Edge Flags.
ISCAS
Takuki Nakagawa, Tadashi Shibata
2009 C conf
A Single-motion-vector/Cycle-generation Optical Flow Processor Employing Directional-edge Histogram Matching.
ISCAS
Kazuhide Fujita, Kiyoto Ito, Tadashi Shibata
2009 J jnl
A low-power switched-current CDMA matched filter employing MOS linear matching cell with on-chip A/D converter.
Integr.
Toshihiko Yamasaki, Tomoyuki Nakayama, Tadashi Shibata
2009 — conf
A real-time image recognition system using a global directional-edge-feature extraction VLSI processor.
ESSCIRC
Hongbo Zhu, Tadashi Shibata
2009 C conf
An On-chip-trainable Gaussian-kernel Analog Support Vector Machine.
ISCAS
Kyunghee Kang, Tadashi Shibata
2009 — conf
Bio-inspired devices, circuits and systems.
ESSCIRC
Tadashi Shibata
2009 C conf
Block-matching-based CMOS Optical Flow Sensor using Only-nearest-neighbor Computation.
ISCAS
Yudai Fukuoka, Tadashi Shibata
2009 B conf
Normalized scoring of Hidden Markov Models by on-line learning and its application to gesture-sequence perception.
ICIP
Mio Nishiyama, Tadashi Shibata
2008 C conf
An analog self-similitude edge-filtering processor for multiple-resolution image perception.
ISCAS
Norihiro Takahashi, Kazuhide Fujita, Tadashi Shibata
2008 Misc conf
Blind image compression history determination using dynamic thresholding.
ICASSP
Robert Grou-Szabo, Tadashi Shibata
2008 C conf
Spatiotemporal projection of motion field sequence for generating feature vectors in gesture perception.
ISCAS
Hitoshi Hayakawa, Tadashi Shibata
2008 J jnl
Special Section on Advanced Processors Based on Novel Concepts in Computation.
IEICE Trans. Electron.
Tadashi Shibata
2007 — conf
A Feature-Based Optical Flow Processor Architecture Featuring Single-Motion-Vector/Cycle Generation.
SoC
Kazuhide Fujita, Kiyoto Ito, Tadashi Shibata
2007 J jnl
A Low-Power Floating-Gate-MOS-Based CDMA Matched Filter Featuring Coupling Capacitor Disconnection.
IEEE J. Solid State Circuits
Toshihiko Yamasaki, Tadashi Shibata
2007 J jnl
A Real-Time Image-Feature-Extraction and Vector-Generation VLSI Employing Arrayed-Shift-Register Architecture.
IEEE J. Solid State Circuits
Hideo Yamasaki, Tadashi Shibata
2007 — conf
A Real-Time Learning Processor Based on K-means Algorithm with Automatic Seeds Generation.
SoC
Hirotsugu Shikano, Kiyoto Ito, Kazuhide Fujita, Tadashi Shibata
2007 — conf
A speed adaptive ego-motion detection system using EDGE-histograms produced by variable graduation method.
EUSIPCO
Jia Hao, Tadashi Shibata
2007 J jnl
An Intelligent Action Control System Based on Extended Vector Annotated Logic Program and its Hardware Implementation.
Intell. Autom. Soft Comput.
Kazumi Nakamatsu, Yoshio Mita, Tadashi Shibata
2007 — conf
Mixed-Signal Focal-Plane Image Processor Employing Tme-domaiin Computation Architecture.
SoC
Kiyoto Ito, Tadashi Shibata
2007 — conf
Validating directional edge-based image feature representations in face recognition by spatial correlation-based clustering.
EUSIPCO
Yasufumi Suzuki, Tadashi Shibata
2006 — conf
A Vlsi-Implementation-Friendly EGO-Motion Detection Algorithm Based on Edge-Histogram Matching.
ICASSP (2)
Jia Hao, Tadashi Shibata
2006 C conf
A time-domain gradient-detection architecture for VLSI analog motion sensors.
ISCAS
Kiyoto Ito, Tadashi Shibata
2006 — conf
Illumination-invariant face identification using edge-based feature vectors in pseudo-2D Hidden Markov Models.
EUSIPCO
Yasufumi Suzuki, Tadashi Shibata
2006 — conf
Multi-view face detection and pose estimation employing edge-based feature vectors.
EUSIPCO
Daisuke Moriya, Yasufumi Suzuki, Tadashi Shibata, Masakazu Yagi, Kenji Takada
2006 C conf
Power-balanced reconfigurable floating-gate-MOS logic circuit for tamper resistant VLSI.
ISCAS
Benjamas Tongprasit, Tadashi Shibata
2005 — conf
A computational digital-pixel-sensor VLSI featuring block-readout architecture for pixel-parallel rank-order filtering.
ISCAS (3)
Benjamas Tongprasit, Kiyoto Ito, Tadashi Shibata
2005 J jnl
A delay-encoding-logic array processor for dynamic-programming matching of data sequences.
IEEE J. Solid State Circuits
Makoto Ogawa, Tadashi Shibata
2005 — conf
A high-speed median filter VLSI using floating-gate-MOS-based low-power majority voting circuits.
ESSCIRC
Hideo Yamasaki, Tadashi Shibata
2005 J jnl
A low-power and compact CDMA matched filter based on switched-current technology.
IEEE J. Solid State Circuits
Toshihiko Yamasaki, Tomoyuki Nakayama, Tadashi Shibata
2005 — conf
A low-power switched-current CDMA matched filter employing MOS-linear matching cell and output A/D converter.
ISCAS (6)
Tomoyuki Nakayama, Toshihiko Yamasaki, Tadashi Shibata
2005 — conf
A new distance measure employing element-significance factors for robust image classification.
EUSIPCO
Kunio Kawahara, Tadashi Shibata
2005 — conf
A real-time image-feature-extraction and vector-generation VLSI employing arrayed-shift-register architecture.
ESSCIRC
Hideo Yamasaki, Tadashi Shibata
2005 — conf
An Analog Visual Pre-Processing Processor Employing Cyclic Line Access in Only-Nearest-Neighbor-Interconnects Architecture.
NIPS
Yusuke Nakashita, Yoshio Mita, Tadashi Shibata
2005 — conf
Multiple-resolution edge-based feature representations for robust face segmentation and verification.
EUSIPCO
Yasufumi Suzuki, Tadashi Shibata
2004 — conf
A bump-circuit-based motion detector using projected-activity histograms.
ISCAS (1)
Masayuki Umejima, Toshihiko Yamasaki, Tadashi Shibata
2004 — conf
A delay-encoding-logic array processor for dynamic programming matching.
ESSCIRC
Makoto Ogawa, Tadashi Shibata
2004 — conf
A real-time VLSI median filter employing two-dimensional bit-propagating architecture.
ISCAS (2)
Hideo Yamasaki, Tadashi Shibata
2004 — conf
An edge-based face detection algorithm robust against illumination, focus, and scale variations.
EUSIPCO
Yasufumi Suzuki, Tadashi Shibata
2004 — conf
Multiple-clue face detection algorithm using edge-based feature vectors.
ICASSP (5)
Yasufumi Suzuki, Tadashi Shibata
2004 — conf
Quasi-parallel multi-path detection architecture using floating-gate-MOS-based CDMA matched filters.
ISCAS (1)
Tomoyuki Nakayama, Toshihiko Yamasaki, Tadashi Shibata
2003 — conf
A Mixed-Signal VLSI for Real-Time Generation of Edge-Based Image Vectors.
NIPS
Masakazu Yagi, Hideo Yamasaki, Tadashi Shibata
2003 — conf
A Robust Medical Image Recognition System Employing Edge-Based Feature Vector Representation.
SCIA
Masakazu Yagi, Tadashi Shibata, Chihiro Tanikawa, Kenji Takada
2003 J jnl
A fully integrated 0.13-μm CMOS mixed-signal SoC for DVD player applications.
IEEE J. Solid State Circuits
Koji Okamoto, Takashi Morie, Akira Yamamoto, Kouichi Nagano, Koji Sushihara, Hiroyuki Nakahira, Ryusuke Horibe, Kazutoshi Aida, Toshihiko Takahashi, Minoru Ochiai, Akinobu Soneda, Toru Kakiage, Tamaki Iwasaki, Hiroshi Taniuchi, Tadashi Shibata, Takahiro Ochi, Masao Takiguchi, Takashi Yamamoto, Tadayoshi Seike, Akira Matsuzawa
2003 — conf
An analog image processing LSI employing scanning line-parallel processing.
ESSCIRC
Teruyasu Taguchi, Makoto Ogawa, Tadashi Shibata
2003 J jnl
An image representation algorithm compatible with neural-associative-processor-based hardware recognition systems.
IEEE Trans. Neural Networks
Masakazu Yagi, Tadashi Shibata
2003 J jnl
Analog soft-pattern-matching classifier using floating-gate MOS technology.
IEEE Trans. Neural Networks
Toshihiko Yamasaki, Tadashi Shibata
2003 J jnl
Guest editorial - Special issue on neural networks hardware implementations.
IEEE Trans. Neural Networks
Bernabé Linares-Barranco, Andreas G. Andreou, Giacomo Indiveri, Tadashi Shibata
2003 — conf
Robust cephalometric landmark identification using support vector machines.
ICASSP (2)
Shantanu Chakrabartty, Masakazu Yagi, Tadashi Shibata, Gert Cauwenberghs
2003 A conf
Robust cephalometric landmark identification using support vector machines.
ICME
Shantanu Chakrabartty, Masakazu Yagi, Tadashi Shibata, Gert Cauwenberghs
2003 — conf
Speaker and text independent language identification using predictive error histogram vectors.
ICASSP (1)
Qian-Rong Gu, Tadashi Shibata
2002 Misc conf
A human-perception-like image recognition system based on PAP vector representation with multi resolution concept.
ICASSP
Masakazu Yagi, Tadashi Shibata
2002 — conf
A motion-based analog VLSI saliency detector using quasi-two-dimensional hardware algorithm.
ISCAS (3)
Hiroe Kimura, Tadashi Shibata
2002 — conf
A zone-programmed EEPROM with real-time write monitoring for analog data storage.
ISCAS (4)
Keng Hoong Wee, T. Yonezawa, Toshiyuki Nozawa, Tadashi Shibata, Tadahiro Ohmi
2002 — conf
An associative-processor-based mixed signal system for robust grayscale image recognition.
ISCAS (5)
Masakazu Yagi, Tadashi Shibata
2002 — conf
Human-perception-like image recognition system based on the Associative Processor architecture.
EUSIPCO
Masakazu Yagi, Tadashi Shibata, Kenji Takada
2002 — conf
Intelligent Internet Search Applications Based on VLSI Associative Processors.
SAINT
Huaiyu Xu, Yoshio Mita, Tadashi Shibata
2002 J jnl
Intelligent Signal Processing Based on a Psychologically-Inspired VLSI Brain Model.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Tadashi Shibata
2002 — conf
Low-power CDMA analog matched filters based on floating-gate technology.
ISCAS (5)
Toshihiko Yamasaki, Teruyasu Taguchi, Tadashi Shibata
2001 — conf
A fast self-convergent flash-memory programming scheme for MV and analog data storage.
ISCAS (4)
Toshihiko Yamasaki, Atsushi Suzuki, Daisuke Kobayashi, Tadashi Shibata
2001 — conf
An analog similarity evaluation circuit featuring variable functional forms.
ISCAS (3)
Toshihiko Yamasaki, Tadashi Shibata
2001 — conf
Analog Soft-Pattern-Matching Classifier using Floating-Gate MOS Technology.
NIPS
Toshihiko Yamasaki, Tadashi Shibata
2001 — conf
High-precision analog EEPROM with real-time write monitoring.
ISCAS (1)
Keng Hoong Wee, Toshiyuki Nozawa, Takemi Yonezawa, Yuichiro Yamashita, Tadashi Shibata, Tadahiro Ohmi
2000 — conf
A hardware-friendly soft-computing algorithm for image recognition.
EUSIPCO
Masakazu Yagi, Masayoshi Adachi, Tadashi Shibata
1999 J jnl
A fully parallel vector-quantization processor for real-time motion-picture compression.
IEEE J. Solid State Circuits
Akira Nakada, Tadashi Shibata, Masahiro Konda, Tatsuo Morimoto, Tadahiro Ohmi
1999 — conf
A neuron-MOS parallel associator for high-speed CDMA matched filter.
ISCAS (2)
Atsuhiko Okada, Tadashi Shibata
1999 J jnl
Association hardware for intelligent electronic systems.
Syst. Comput. Jpn.
Tadahiro Ohmi, Tadashi Shibata, Koji Kotani, Tsutomu Nakai, Akira Nakada, Ning Mei Yu, Masahiro Konda, Tatsuo Morimoto, Yuichiro Yamashita
1998 J jnl
CMOS charge-transfer preamplifier for offset-fluctuation cancellation in low-power A/D converters.
IEEE J. Solid State Circuits
Koji Kotani, Tadashi Shibata, Tadahiro Ohmi
1998 — conf
Functional-Device-Based VLSI for Intelligent Electronic Systems.
ISMVL
Tadashi Shibata
1998 — conf
Neuron-MOS continuous-time winner-take-all circuit for intelligent data processing.
KES (3)
Tatsuo Morimoto, Tadashi Shibata, Tadahiro Ohmi
1998 — conf
Right brain computing hardware: a psychological brain model on silicon.
KES (3)
Tadashi Shibata
1996 J jnl
Implementing Intelligence in Silicon Integrated Circuits Using Neuron-Like High-Functionality Transistors.
J. Robotics Mechatronics
Tadashi Shibata, Tadahiro Ohmi
1995 J jnl
A neuron-MOS neural network using self-learning-compatible synapse circuits.
IEEE J. Solid State Circuits
Tadashi Shibata, Hideo Kosaka, Hiroshi Ishii, Tadahiro Ohmi
1995 — conf
Neuron-MOS Temporal Winner Search Hardware for Fully-Parallel Data Processing.
NIPS
Tadashi Shibata, Tsutomu Nakai, Tatsuo Morimoto, Ryu Kaihara, Takeo Yamashita, Tadahiro Ohmi
1993 — conf
Implementing Intelligence on Silicon Using Neuron-Like Functional MOS Transistors.
NIPS
Tadashi Shibata, Koji Kotani, Takeo Yamashita, Hiroshi Ishii, Hideo Kosaka, Tadahiro Ohmi