Tadao Nakamura

74 papers A* 2B 4C 6Misc 1Journal 34Unranked 27

Year	Rank	Type	Title / Venue / Authors
2023	J	`jnl`	Two symmetric measurements may cause an unforeseen effect. Quantum Inf. Process. Koji Nagata, Do Ngoc Diep, Tadao Nakamura
2022	J	`jnl`	Computational complexity in high-dimensional quantum computing. Quantum Mach. Intell. Koji Nagata, Do Ngoc Diep, Tadao Nakamura
2021	J	`jnl`	Quantum cryptography based on an algorithm for determining simultaneously all the mappings of a Boolean function. IACR Cryptol. ePrint Arch. Koji Nagata, Renata Wong, Do Ngoc Diep, Tadao Nakamura
2020	J	`jnl`	Nonparametric Regression Quantum Neural Networks. CoRR Do Ngoc Diep, Koji Nagata, Tadao Nakamura
2019	—	`conf`	An Introduction to Marching Memory (MM). 3DIC Tadao Nakamura
2017	—	`conf`	Panel discussions: "Cool chips for the next decade". COOL Chips Hideharu Amano, Tadao Nakamura, Hiroaki Kobayashi, Hironori Kasahara, Yoshiaki Hagiwara, Jeffrey L. Burns, David Brash
2017	J	`jnl`	Scalable Networks-on-Chip with Elastic Links Demarcated by Decentralized Routers. IEEE Trans. Computers Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tadao Nakamura
2016	—	`conf`	Message from the advisory committee chair. COOL Chips Tadao Nakamura
2015	—	`conf`	On-Chip Decentralized Routers with Balanced Pipelines for Avoiding Interconnect Bottleneck. NOCS Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tadao Nakamura
2014	—	`conf`	A low power NoC router using the marching memory through type. COOL Chips Ryota Yasudo, Takahiro Kagami, Hideharu Amano, Yasunobu Nakase, Masashi Watanabe, Tsukasa Oishi, Toru Shimizu, Tadao Nakamura
2014	—	`conf`	Design of a low power NoC router using Marching Memory Through type. NOCS Ryota Yasudo, Takahiro Kagami, Hideharu Amano, Yasunobu Nakase, Masashi Watanabe, Tsukasa Oishi, Toru Shimizu, Tadao Nakamura
2014	J	`jnl`	Identifying Program Loop Nesting Structures during Execution of Machine Code. IEICE Trans. Inf. Syst. Yukinori Sato, Yasushi Inoguchi, Tadao Nakamura
2014	—	`conf`	Message from the advisory committee chair. COOL Chips Tadao Nakamura
2013	J	`jnl`	An additional condition for Bell experiments for accepting local realistic theories. Quantum Inf. Process. Koji Nagata, Tadao Nakamura
2013	—	`conf`	Influence of wafer thinning process on backside damage in 3D integration. 3DIC Tadao Nakamura, Yoriko Mizushima, Hideki Kitada, Young-Suk Kim, Nobuhide Maeda, Shoichi Kodama, Ryuichi Sugie, Hiroshi Hashimoto, Akihito Kawai, Kazuhisa Arai, Akira Uedono, Takayuki Ohba
2013	—	`conf`	Message from the Advisory Committee Chair. COOL Chips Tadao Nakamura
2012	—	`conf`	Evaluating reconfigurable dataflow computing using the Himeno benchmark. ReConFig Yukinori Sato, Yasushi Inoguchi, Wayne Luk, Tadao Nakamura
2012	—	`conf`	Whole program data dependence profiling to unveil parallel regions in the dynamic execution. IISWC Yukinori Sato, Yasushi Inoguchi, Tadao Nakamura
2011	—	`conf`	Development of ultra-thinning technology for logic and memory heterogeneous stack applications. 3DIC Nobuhide Maeda, Young-Suk Kim, Y. Hikosaka, Takashi Eshita, Hideki Kitada, K. Fujimoto, Yoriko Mizushima, K. Suzuki, Tadao Nakamura, Akihito Kawai, Kazuhisa Arai, Takayuki Ohba
2011	—	`conf`	On-the-fly detection of precise loop nests across procedures on a dynamic binary translation system. Conf. Computing Frontiers Yukinori Sato, Yasushi Inoguchi, Tadao Nakamura
2009	J	`jnl`	Guest Editors' Introduction: ICFPT 2007. ACM Trans. Reconfigurable Technol. Syst. Hideharu Amano, Tadao Nakamura
2007	J	`jnl`	Power Estimation of Partitioned Register Files in a Clustered Architecture with Performance Evaluation. IEICE Trans. Inf. Syst. Yukinori Sato, Ken-Ichi Suzuki, Tadao Nakamura
2006	B	`conf`	Ray Tracing Hardware System Using Plane-Sphere Intersections. FPL Yoshiyuki Kaeriyama, Daichi Zaitsu, Kazuhiko Komatsu, Ken-Ichi Suzuki, Tadao Nakamura, Nobuyuki Ohba
2005	J	`jnl`	A Competitive Learning Algorithm with Controlling Maximum Distortion. J. Adv. Comput. Intell. Intell. Informatics Takeshi Miura, Kentaro Sano, Ken-Ichi Suzuki, Tadao Nakamura
2005	—	`conf`	An Operand Status Based Instruction Steering Scheme for Clustered Architectures. CDES Yukinori Sato, Ken-Ichi Suzuki, Tadao Nakamura
2005	C	`conf`	Cooperation of Neighboring PEs in Clustered Architectures. SBAC-PAD Yukinori Sato, Ken-Ichi Suzuki, Tadao Nakamura
2004	—	`conf`	A Systolic Memory Architecture for Fast Codebook Design based on MMPDCL Algorithm. ITCC (1) Kentaro Sano, Chiaki Takagi, Ryusuke Egawa, Ken-Ichi Suzuki, Tadao Nakamura
2004	J	`jnl`	Differential coding scheme for efficient parallel image composition on a PC cluster system. Parallel Comput. Kentaro Sano, Yusuke Kobayashi, Tadao Nakamura
2004	J	`jnl`	Efficient parallel processing of competitive learning algorithms. Parallel Comput. Kentaro Sano, Shintaro Momose, Hiroyuki Takizawa, Hiroaki Kobayashi, Tadao Nakamura
2004	C	`conf`	Parallel competitive learning algorithm for fast codebook design on partitioned space. CLUSTER Shintaro Momose, Kentaro Sano, Ken-Ichi Suzuki, Tadao Nakamura
2003	—	`conf`	Toward Architecting and Designing Novel Computers. Asia-Pacific Computer Systems Architecture Conference Tadao Nakamura
2002	C	`conf`	Exploiting Loop-Level Parallelism with the Shift Architecture. SBAC-PAD Clecio Donizete Lima, Tadao Nakamura
2002	—	`conf`	Hardware Support for Concurrent Execution of Loops Containing Loop-carried Data Dependences. IASTED PDCS C. D. Lima, Kentaro Sano, Tadao Nakamura
2002	C	`conf`	Moderating traffic flow over conventional ATM service. ISCC Tomoyuki Nagase, Takashi Araki, Yoshio Yoshioka, Tadao Nakamura
2002	—	`conf`	Parallel Algorithm for the Law-of-the-Jungle Learning to the Fast Design of Optimal Codebooks. IASTED PDCS Kentaro Sano, Shintaro Momose, Hiroyuki Takizawa, Taira Nakajima, C. D. Lima, Hiroaki Kobayashi, Tadao Nakamura
2001	C	`conf`	3DCGiRAM: An Intelligent Memory Architecture for Photo-Realistic Image Synthesis. ICCD Hiroaki Kobayashi, Ken-Ichi Suzuki, Kentaro Sano, Yoshiyuki Kaeriyama, Yasumasa Saida, Nobuyuki Oba, Tadao Nakamura
2001	—	`conf`	An Active Network for Improving Performance of Traffic Flow over Conventional ATM Service. ICN (2) Emad Rashid, Takashi Araki, Tadao Nakamura
2001	Misc	`conf`	Scaling Up Of Wave Pipelines. VLSI Design Masa-Aki Fukase, Ryusuke Egawa, Tomoaki Sato, Tadao Nakamura
2001	C	`conf`	Variable-Length Coding based on Bent Sequences for W.ireless Advertising. ISCC Emad Rashid, Yoshio Yoshioka, Takashi Araki, Tadao Nakamura
2000	J	`jnl`	Cool Chips III. IEEE Micro Tadao Nakamura
2000	J	`jnl`	Fast parallel algorithms for vandermonde determinants. Int. J. Comput. Math. Lei Li, Tadao Nakamura
2000	—	`conf`	Reconfigurable synchronized dataflow processor. ASP-DAC Hiroshi Sasaki, Hitoshi Maruyama, Hideaki Tsukioka, Nobuyoshi Shoji, Hiroaki Kobayashi, Tadao Nakamura
1999	J	`jnl`	A scheduling method for instruction-level parallel processing of vectorand scalar instructions. Syst. Comput. Jpn. Takuya Nakaike, Takehito Sasaki, Masayuki Katahira, Hiroaki Kobayashi, Tadao Nakamura
1999	B	`conf`	A self-organizing network system forming memory from nonstationary probability distributions. IJCNN Taira Nakajima, Hiroyuki Takizawa, Hiroaki Kobayashi, Tadao Nakamura
1999	J	`jnl`	Introducing cool chips. IEEE Micro Tadao Nakamura
1999	J	`jnl`	Time stamp invalidation of TLB-unified cache and its performance evaluation. Syst. Comput. Jpn. Ken-Ichi Suzuki, Nobuyuki Oba, Shigenori Shimizu, Hiroaki Kobayashi, Tadao Nakamura
1998	—	`conf`	Automated Design of Wave Pipelined Multiport Register Files. ASP-DAC Kouji Takano, Takehito Sasaki, Nobuyuki Oba, Hiroaki Kobayashi, Tadao Nakamura
1997	J	`jnl`	Asynchronous Monotone Newton Iterative Method on Distributed Computers. Parallel Algorithms Appl. Jie Hu, Tadao Nakamura, Lei Li
1997	J	`jnl`	Convergence, Complexity and Simulation of Monotone Asynchronous Iterative Method for Computing Fixed Point on a Distributed Computer. Parallel Algorithms Appl. Jie Hu, Tadao Nakamura, Lei Li
1997	J	`jnl`	Decoupled modified-bit cache. Syst. Comput. Jpn. Masafumi Takahashi, Nobuyuki Oba, Hiroaki Kobayashi, Tadao Nakamura
1997	—	`conf`	Parallel processing of the shear-warp factorization with the binary-swap method on a distributed-memory multiprocessor system. PRS Kentaro Sano, Hiroyuki Kitajima, Hiroaki Kobayashi, Tadao Nakamura
1996	—	`conf`	A Hierarchical Parallel Processing System for the Multipass-Rendering Method. IPPS Hiroaki Kobayashi, Hitoshi Yamauchi, Yuichiro Toh, Tadao Nakamura
1996	J	`jnl`	A Simple Parallel Algorithm for Polynomial Evaluation. SIAM J. Sci. Comput. Lei Li, Jie Hu, Tadao Nakamura
1996	J	`jnl`	A construction of back-propagation neural networks including time delay elements (BPD). Syst. Comput. Jpn. Masaaki Nishi, Junji Furuya, Tadao Nakamura
1995	J	`jnl`	A Divide-and-inner Product Parallel Algorithm for Polynomial Evaluation. Parallel Algorithms Appl. Jie Hu, Lei Li, Tadao Nakamura
1995	J	`jnl`	The Convergence of Asynchronous Iterations for the Fixed Point of a Splitting Operator. Parallel Algorithms Appl. Lei Li, Tadao Nakamura
1995	—	`conf`	The Convergence of Asynchronous Monotone Newton Iterations on Distributed Computer. PP Jie Hu, Tadao Nakamura, Lei Li
1994	—	`conf`	Software pipelining for Jetpipeline architecture. ISPAN Masayuki Katahira, Takehito Sasaki, Hong Shen, Hiroaki Kobayashi, Tadao Nakamura
1993	A*	`conf`	An Adaptive Network Routing Method by Electrical-Circuit Modeling. INFOCOM Nobuyuki Oba, Hiroaki Kobayashi, Tadao Nakamura
1993	B	`conf`	Parallel Processing and Hardware Support of Symbols. ICTAI Masa-Aki Fukase, Tadao Nakamura
1991	B	`conf`	Semiparallel execution of compiled Lisp programs. COMPSAC Masa-Aki Fukase, Tadao Nakamura
1988	J	`jnl`	Load balancing strategies for a parallel ray-tracing system based on constant subdivision. Vis. Comput. Hiroaki Kobayashi, Satoshi Nishimura, Hideyuki Kubota, Tadao Nakamura, Yoshiharu Shigei
1987	J	`jnl`	An adaptive routing method for computer networks by electric-circuit modeling. Syst. Comput. Jpn. Nobuyuki Oba, Tadao Nakamura, Yoshiharu Shigei
1987	J	`jnl`	Characteristics of a programmable logic unit. Syst. Comput. Jpn. Takahiko Murayama, Hidekazu Yamada, Tadao Nakamura, Yoshiharu Shigei, Yoshio Yoshioka
1987	J	`jnl`	Parallel processing of an object space for image synthesis using ray tracing. Vis. Comput. Hiroaki Kobayashi, Tadao Nakamura, Yoshiharu Shigei
1987	J	`jnl`	Performance evaluation of a computer using programmable logic units. Syst. Comput. Jpn. Takahiko Murayama, Hidekazu Yamada, Tadao Nakamura, Yoshiharu Shigei, Yoshio Yoshioka
1987	J	`jnl`	Realization of computers using programmable logic units. Syst. Comput. Jpn. Hidekazu Yamada, Tadao Nakamura, Yoshiharu Shigei, Takahiko Murayama, Yoshio Yoshioka
1986	J	`jnl`	A Hierarchical General-Purpose Pipeline System. Syst. Comput. Jpn. Noboru Endo, Tadao Nakamura, Yoshiharu Shigei
1986	J	`jnl`	Matrix representation of programs within an intelligent link. Syst. Comput. Jpn. Jun Miyajima, Noboru Endo, Tadao Nakamura, Yoshiharu Shigei
1986	J	`jnl`	Signal processing on a parallel pipeline-structured data-flow computer system. Syst. Comput. Jpn. Nobuyuki Oba, Tadao Nakamura, Yoshiharu Shigei
1985	J	`jnl`	Evaluating the parallelism of the feed-forward machine and algorithms of the machine. Syst. Comput. Jpn. Masayuki Tomisawa, Hidekazu Yamada, Tadao Nakamura, Yoshiharu Shigei
1984	—	`conf`	A Language Processor of an Intelligent Link System. ICC (2) Tadao Nakamura, Hiroaki Kobayashi, Jun Miyajima, Noboru Endo, Yoshiharu Shigei
1984	—	`conf`	An Analysis of the Receiving Behaviour of a Window Flow Control Mechanism in Packet Switching Networks. ICC (3) Kuninobu Tanno, Tadao Nakamura, Risaburo Sato
1981	A*	`conf`	Distributed Communicating Media-A Multitrack Bus-Capable of Concurrent Data Exchanging. ISCA Makoto Hasegawa, Tadao Nakamura, Yoshiharu Shigei