Tadahiro Kuroda

237 papers A* 2A 4B 6C 11Misc 1Journal 104Unranked 108

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	Agile-X: A Structured-ASIC Created With a Mask-Less Lithography System Enabling Low-Cost and Agile Chip Fabrication. IEEE Trans. Very Large Scale Integr. Syst. Atsutake Kosuge, Hirofumi Sumi, Naonobu Shimamoto, Yukinori Ochiai, Yurie Inoue, Hideharu Amano, Tohru Mogami, Yoshio Mita, Makoto Ikeda, Tadahiro Kuroda
2024	J	`jnl`	A 0.13mJ/Prediction CIFAR-100 Fully Synthesizable Raster-Scan-Based Wired-Logic Processor in 16-nm FPGA. IEICE Trans. Electron. Dongzhu Li, Zhijie Zhan, Rei Sumikawa, Mototsugu Hamada, Atsutake Kosuge, Tadahiro Kuroda
2024	C	`conf`	Efficient FPGA Resource Utilization in Wired-Logic Processors Using Coarse and Fine Segmentation of LUTs for Non-Linear Functions. ISCAS Dongzhu Li, Tianqi Zhao, Kenji Kobayashi, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda
2024	J	`jnl`	Slashing IC Power and Democratizing IC Access for the Digital Age. IPSJ Trans. Syst. LSI Des. Methodol. Tadahiro Kuroda
2023	C	`conf`	A 0.13mJ/Prediction CIFAR-100 Raster-Scan- Based Wired-Logic Processor Using Non-Linear Neural Network. ISCAS Dongzhu Li, Yao-Chung Hsu, Rei Sumikawa, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda
2023	—	`conf`	A 1.2nJ/Classification Fully Synthesized All-Digital Asynchronous Wired-Logic Processor Using Quantized Non-Linear Function Blocks in 0.18μm CMOS. ASP-DAC Rei Sumikawa, Kota Shiba, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda
2023	J	`jnl`	A 10.7-µJ/Frame 88% Accuracy CIFAR-10 Single-Chip Neuromorphic Field-Programmable Gate Array Processor Featuring Various Nonlinear Functions of Dendrites in the Human Cerebrum. IEEE Micro Atsutake Kosuge, Yao-Chung Hsu, Rei Sumikawa, Mototsugu Hamada, Tadahiro Kuroda, Tomoe Ishikawa
2023	—	`conf`	A 183.4nJ/inference 152.8μW Single-Chip Fully Synthesizable Wired-Logic DNN Processor for Always-On 35 Voice Commands Recognition Application. VLSI Technology and Circuits Atsutake Kosuge, Rei Sumikawa, Yao-Chung Hsu, Kota Shiba, Mototsugu Hamada, Tadahiro Kuroda
2023	J	`jnl`	A 7-nm FinFET 1.2-TB/s/mm IEEE J. Solid State Circuits Kota Shiba, Mitsuji Okada, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda
2023	—	`conf`	A Fully Synthesized 13.7μJ/Prediction 88% Accuracy CIFAR-10 Single-Chip Data-Reusing Wired-Logic Processor Using Non-Linear Neural Network. ASP-DAC Yao-Chung Hsu, Atsutake Kosuge, Rei Sumikawa, Kota Shiba, Mototsugu Hamada, Tadahiro Kuroda
2023	C	`conf`	An Occlusion-Resilient mmWave Imaging Radar-Based Object Recognition System Using Synthetic Training Data Generation Technique. IECON Eitaro Kobayashi, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda
2023	—	`conf`	Analysis and Design of a 7 Gb/s Rotatable Non-contact Connector with Grid Array Package Application. NEWCAS Ximing Wang, Atsutake Kosuge, Yasuhiro Hayashi, Kota Shiba, Mototsugu Hamada, Tadahiro Kuroda
2023	J	`jnl`	Crosstalk Analysis and Countermeasures of High-Bandwidth 3D-Stacked Memory Using Multi-Hop Inductive Coupling Interface. IEICE Trans. Electron. Kota Shiba, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda
2023	J	`jnl`	Polyomino: A 3D-SRAM-Centric Accelerator for Randomly Pruned Matrix Multiplication With Simple Reordering Algorithm and Efficient Compression Format in 180-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. Kota Shiba, Mitsuji Okada, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda
2022	J	`jnl`	A 0.61-μJ/Frame Pipelined Wired-logic DNN Processor in 16-nm FPGA Using Convolutional Non-Linear Neural Network. IEEE Open J. Circuits Syst. Atsutake Kosuge, Yao-Chung Hsu, Mototsugu Hamada, Tadahiro Kuroda
2022	—	`conf`	A 13.7μJ/prediction 88% Accuracy CIFAR-10 Single-Chip Wired-logic Processor in 16-nm FPGA using Non-Linear Neural Network. HCS Yao-Chung Hsu, Atsutake Kosuge, Rei Sumikawa, Kota Shiba, Mototsugu Hamada, Tadahiro Kuroda
2022	—	`conf`	A 5.2GHz RFID Chip Contactlessly Mountable on FPC at any 90-Degree Rotation and Face Orientation. ASP-DAC Reiji Miura, Saito Shibata, Masahiro Usui, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda
2022	J	`jnl`	A 6-Gb/s Inductively-Powered Non-Contact Connector With Rotatable Transmission Line Coupler and Interface Bridge IC. IEEE J. Solid State Circuits Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda
2022	J	`jnl`	A 6.5Gb/s Shared Bus Using Electromagnetic Connectors for Downsizing and Lightening Satellite Processor System. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda
2022	—	`conf`	A 7 Gb/s Micro Rotatable Transmission Line Coupler with Deep Proximity Coupling Mode and Ground Shielding Vias. ICECS 2022 Ximing Wang, Atsutake Kosuge, Yasuhiro Hayashi, Mototsugu Hamada, Tadahiro Kuroda
2022	—	`conf`	A 7-nm FinFET 1.2-TB/s/mm HCS Kota Shiba, Mitsuji Okada, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda
2022	—	`conf`	A Low-power RFID with 100kbps Data Rate Employing High-speed Power Clock Generator for Complementary Pass-transistor Adiabatic Logic. ICECS 2022 Saito Shibata, Yoshiki Sawabe, Kota Shiba, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda
2022	B	`conf`	An Anomaly Detection System for Transparent Objects Using Polarized-Image Fusion Technique. SAS Lixing Yu, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda
2022	—	`conf`	Polyomino: A 3D-SRAM-Centric Architecture for Randomly Pruned Matrix Multiplication with Simple Rearrangement Algorithm and x0.37 Compression Format. NEWCAS Kota Shiba, Mitsuji Okada, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda
2022	J	`jnl`	Proximity Wireless Communication Technologies: An Overview and Design Guidelines. IEEE Trans. Circuits Syst. I Regul. Pap. Atsutake Kosuge, Tadahiro Kuroda
2022	J	`jnl`	mmWave-YOLO: A mmWave Imaging Radar-Based Real-Time Multiclass Object Recognition System for ADAS Applications. IEEE Trans. Instrum. Meas. Atsutake Kosuge, Satoshi Suehiro, Mototsugu Hamada, Tadahiro Kuroda
2021	J	`jnl`	A 16 nJ/Classification FPGA-Based Wired-Logic DNN Accelerator Using Fixed-Weight Non-Linear Neural Net. IEEE J. Emerg. Sel. Topics Circuits Syst. Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda
2021	—	`conf`	A 3D-Stacked SRAM Using Inductive Coupling Technology for AI Inference Accelerator in 40-nm CMOS. ASP-DAC Kota Shiba, Tatsuo Omori, Mototsugu Hamada, Tadahiro Kuroda
2021	—	`conf`	A 5-GHz 0.15-mm A-SSCC Saito Shibata, Reiji Miura, Yoshiki Sawabe, Kota Shiba, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda
2021	J	`jnl`	A 96-MB 3D-Stacked SRAM Using Inductive Coupling With 0.4-V Transmitter, Termination Scheme and 12: 1 SerDes in 40-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. Kota Shiba, Tatsuo Omori, Kodai Ueyoshi, Shinya Takamaeda-Yamazaki, Masato Motomura, Mototsugu Hamada, Tadahiro Kuroda
2021	—	`conf`	CA2 area detection from hippocampal microscope images using deep learning. MWSCAS Shohei Morinaga, Tomoe Ishikawa, Masato Yasui, Mototsugu Hamada, Tadahiro Kuroda
2021	—	`conf`	Sub-10-μm Coil Design for Multi-Hop Inductive Coupling Interface. ASP-DAC Tatsuo Omori, Kota Shiba, Mototsugu Hamada, Tadahiro Kuroda
2020	C	`conf`	A 3D-Stacked SRAM using Inductive Coupling with Low-Voltage Transmitter and 12: 1 SerDes. ISCAS Kota Shiba, Tatsuo Omori, Kodai Ueyoshi, Kota Ando, Kazutoshi Hirose, Shinya Takamaeda-Yamazaki, Masato Motomura, Mototsugu Hamada, Tadahiro Kuroda
2020	—	`conf`	A 50 Mbps/pin 12-input/output 40 nsec Latency Wireless Connector Using a Transmission Line Coupler with Compact SERDES IC in 180 nm CMOS. ICECS Kohei Ando, Kazuhisa Akatsuka, Chaoran Cheng, Tomoya Arakawa, Kota Shiba, Mototsugu Hamada, Tadahiro Kuroda
2019	C	`conf`	Live Demonstration: A Non-Contact Transmission Line Connector for USB3.1 HD-Video Streaming. ISCAS Tomoya Arakawa, Joshin Sone, Mitsuji Okada, Mototsugu Hamada, Tadahiro Kuroda
2019	—	`conf`	Low-Power and ppm-Level Detection of Gas Molecules by Integrated Metal Nanosheets. VLSI Circuits Takahisa Tanaka, K. Tabuchi, Kohei Tatehora, Yohsuke Shiiki, S. Nakagawa, Tsunaki Takahashi, R. Shimizu, Hiroki Ishikuro, Tadahiro Kuroda, T. Yanagida, Ken Uchida
2019	J	`jnl`	QUEST: Multi-Purpose Log-Quantized DNN Inference Engine Stacked on 96-MB 3-D SRAM Using Inductive Coupling Technology in 40-nm CMOS. IEEE J. Solid State Circuits Kodai Ueyoshi, Kota Ando, Kazutoshi Hirose, Shinya Takamaeda-Yamazaki, Mototsugu Hamada, Tadahiro Kuroda, Masato Motomura
2019	J	`jnl`	Transmission Line Coupler: High-Speed Interface for Non-Contact Connecter. IEICE Trans. Electron. Mototsugu Hamada, Tadahiro Kuroda
2018	J	`jnl`	BRein Memory: A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W. IEEE J. Solid State Circuits Kota Ando, Kodai Ueyoshi, Kentaro Orimo, Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Tetsuya Asai, Tadahiro Kuroda, Masato Motomura
2018	—	`conf`	Balanced Mini-Batch Training for Imbalanced Image Data Classification with Neural Network. AI4I Ryota Shimizu, Kosuke Asako, Hiroki Ojima, Shohei Morinaga, Mototsugu Hamada, Tadahiro Kuroda
2018	—	`conf`	Comparative Performance Analysis of Dual-Rail Domino Logic and CMOS Logic Under NearThreshold Operation. MWSCAS Tsuyoshi Maruyama, Mototsugu Hamada, Tadahiro Kuroda
2018	C	`conf`	Design Methodology in Wireless Power Transfer System for 3-D Stacked Multiple Receivers. ISCAS Shusuke Yanagawa, Ryota Shimizu, Mototsugu Hamada, Toru Shimizu, Tadahiro Kuroda
2018	J	`jnl`	Escalator Network for a 3D Chip Stack with Inductive Coupling ThruChip Interface. Int. J. Netw. Comput. Akio Nomura, Yusuke Matsushita, Junichiro Kadomoto, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano
2018	—	`conf`	Fully Integrated OOK-Powered Pad-Less Deep Sub-Wavelength-Sized 5-GHz RFID with On-Chip Antenna Using Adiabatic Logic in 0.18μM CMOS. VLSI Circuits Yuta Toeda, Takumi Fujimaki, Mototsugu Hamada, Tadahiro Kuroda
2018	J	`jnl`	Optimization of Resonant Capacitance in Wireless Power Transfer System with 3-D Stacked Two Receivers. IEICE Trans. Electron. Shusuke Yanagawa, Ryota Shimizu, Mototsugu Hamada, Toru Shimizu, Tadahiro Kuroda
2018	—	`conf`	QUEST: A 7.49TOPS multi-purpose log-quantized DNN inference engine stacked on 96MB 3D SRAM using inductive-coupling technology in 40nm CMOS. ISSCC Kodai Ueyoshi, Kota Ando, Kazutoshi Hirose, Shinya Takamaeda-Yamazaki, Junichiro Kadomoto, Tomoki Miyata, Mototsugu Hamada, Tadahiro Kuroda, Masato Motomura
2018	—	`conf`	Wireless Power Transfer System for 3-D stacked Multiple Receivers Switching between Single and Dual Frequency Modes. MWSCAS Shusuke Yanagawa, Ryota Shimizu, Mototsugu Hamada, Tadahiro Kuroda
2017	—	`conf`	A Practical Collision Avoidance Method for an Inter-Chip Bus with Wireless Inductive through Chip Interface. CANDAR Akio Nomura, Junichiro Kadomoto, Tadahiro Kuroda, Hideharu Amano
2017	—	`conf`	An image sensor/processor 3D stacked module featuring ThruChip interfaces. ASP-DAC Masayuki Ikebe, Tetsuya Asai, Masafumi Mori, Toshiyuki Itou, Daisuke Uchida, Yasuhiro Take, Tadahiro Kuroda, Masato Motomura
2017	—	`conf`	An inductive-coupling link for 3-D Network-on-Chips. ISOCC Junichiro Kadomoto, Hideharu Amano, Tadahiro Kuroda
2017	—	`conf`	Building block multi-chip systems using inductive coupling through chip interface. ISOCC Hideharu Amano, Tadahiro Kuroda, Hiroshi Nakamura, Kimiyoshi Usami, Masaaki Kondo, Hiroki Matsutani, Mitaro Namiki
2017	—	`conf`	Convolutional neural network for industrial egg classification. ISOCC Ryota Shimizu, Shusuke Yanagawa, Toru Shimizu, Mototsugu Hamada, Tadahiro Kuroda
2017	—	`conf`	Wireless power transfer to stacked modules for IoT sensor nodes. ISOCC Shusuke Yanagawa, Ryota Shimizu, Mototsugu Hamada, Toru Shimizu, Tadahiro Kuroda
2016	—	`conf`	A 1 Tb/s/mm ESSCIRC So Hasegawa, Junichiro Kadomoto, Atsutake Kosuge, Tadahiro Kuroda
2016	J	`jnl`	A 280 Mb/s In-Vehicle LAN System Using Electromagnetic Clip Connector and High-EMC Transceiver. IEEE Trans. Circuits Syst. I Regul. Pap. Atsutake Kosuge, Akira Okada, Masao Taguchi, Hiroki Ishikuro, Tadahiro Kuroda
2016	J	`jnl`	A 6 Gb/s 6 pJ/b 5 mm-Distance Non-Contact Interface for Modular Smartphones Using Two-Fold Transmission Line Coupler and High EMC Tolerant Pulse Transceiver. IEEE J. Solid State Circuits Atsutake Kosuge, Junichiro Kadomoto, Tadahiro Kuroda
2016	J	`jnl`	An Inductively Powered Wireless Solid-State Drive System With Merged Error Correction of High-Speed Wireless Data Links and NAND Flash Memories. IEEE J. Solid State Circuits Atsutake Kosuge, Junki Hashiba, Toru Kawajiri, So Hasegawa, Tsunaaki Shidei, Hiroki Ishikuro, Tadahiro Kuroda, Ken Takeuchi
2016	—	`conf`	An inductive-coupling bus with collision detection scheme using magnetic field variation for 3-D network-on-chips. A-SSCC Junichiro Kadomoto, Tomoki Miyata, Hideharu Amano, Tadahiro Kuroda
2016	J	`jnl`	Analysis and Evaluation of Electromagnetic Interference between ThruChip Interface and LC-VCO. IEICE Trans. Electron. Junichiro Kadomoto, So Hasegawa, Yusuke Kiuchi, Atsutake Kosuge, Tadahiro Kuroda
2016	—	`conf`	Analytical thruchip inductive coupling channel design optimization. ASP-DAC Li-Chung Hsu, Junichiro Kadomoto, So Hasegawa, Atsutake Kosuge, Yasuhiro Take, Tadahiro Kuroda
2016	—	`conf`	Deep learning application trial to lung cancer diagnosis for medical sensor systems. ISOCC Ryota Shimizu, Shusuke Yanagawa, Yasutaka Monde, Hiroki Yamagishi, Mototsugu Hamada, Toru Shimizu, Tadahiro Kuroda
2016	J	`jnl`	Efficient 3-D Bus Architectures for Inductive-Coupling ThruChip Interfaces. IEEE Trans. Very Large Scale Integr. Syst. Takahiro Kagami, Hiroki Matsutani, Michihiro Koibuchi, Yasuhiro Take, Tadahiro Kuroda, Hideharu Amano
2016	C	`conf`	Low-energy algorithm for self-controlled Wireless Sensor Nodes. WINCOM Ahmad Muzaffar bin Baharudin, Mika Saari, Pekka Sillberg, Petri Rantanen, Jari Soini, Tadahiro Kuroda
2016	—	`conf`	Motion-vector estimation and cognitive classification on an image sensor/processor 3D stacked system featuring ThruChip interfaces. ESSCIRC Tetsuya Asai, Masafumi Mori, Toshiyuki Itou, Yasuhiro Take, Masayuki Ikebe, Tadahiro Kuroda, Masato Motomura
2016	—	`conf`	Vertical Packet Switching Elevator Network Using Inductive Coupling ThruChip Interface. CANDAR Akio Nomura, Hiroki Matsutani, Tadahiro Kuroda, Junichiro Kadomoto, Yusuke Matsushita, Hideharu Amano
2015	—	`conf`	10.1 A 6Gb/s 6pJ/b 5mm-distance non-contact interface for modular smartphones using two-fold transmission-line coupler and EMC-qualified pulse transceiver. ISSCC Atsutake Kosuge, Shu Ishizuka, Junichiro Kadomoto, Tadahiro Kuroda
2015	—	`conf`	24.4 A 6.5Gb/s Shared bus using electromagnetic connectors for downsizing and lightening satellite processor system by 60%. ISSCC Atsutake Kosuge, Shu Ishizuka, Marni Abe, Satoshi Ichikawa, Tadahiro Kuroda
2015	J	`jnl`	A Study of Physical Design Guidelines in ThruChip Inductive Coupling Channel. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Li-Chung Hsu, Junichiro Kadomoto, So Hasegawa, Atsutake Kosuge, Yasuhiro Take, Tadahiro Kuroda
2015	J	`jnl`	An 8 bit 0.3-0.8 V 0.2-40 MS/s 2-bit/Step SAR ADC With Successively Activated Threshold Configuring Comparators in 40 nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. Kentaro Yoshioka, Akira Shikata, Ryota Sekimoto, Tadahiro Kuroda, Hiroki Ishikuro
2015	J	`jnl`	Analysis and Design of an 8.5-Gb/s/Link Multi-Drop Bus Using Energy-Equipartitioned Transmission Line Couplers. IEEE Trans. Circuits Syst. I Regul. Pap. Atsutake Kosuge, Shu Ishizuka, Masao Taguchi, Hiroki Ishikuro, Tadahiro Kuroda
2015	—	`conf`	Circuit and package design for 44GB/s inductive-coupling DRAM/SoC interface. ASP-DAC Akira Okada, Abdul Raziz Junaidi, Yasuhiro Take, Atsutake Kosuge, Tadahiro Kuroda
2015	J	`jnl`	Crosstalk Rejection in 3-D-Stacked Interchip Communication With Blind Source Separation. IEEE Trans. Circuits Syst. II Express Briefs Kamal El-Sankary, Tetsuya Asai, Masato Motomura, Tadahiro Kuroda
2015	—	`conf`	Design and analysis for ThruChip design for manufacturing (DFM). ASP-DAC Li-Chung Hsu, Yasuhiro Take, Atsutake Kosuge, So Hasegawa, Junichiro Kadamoto, Tadahiro Kuroda
2015	—	`conf`	Image sensor/digital logic 3D stacked module featuring inductive coupling channels for high speed/low-noise image transfer. VLSIC Masayuki Ikebe, Daisuke Uchida, Yasuhiro Take, Makito Someya, Satoshi Chikuda, Kento Matsuyama, Tetsuya Asai, Tadahiro Kuroda, Masato Motomura
2015	—	`conf`	Inductively-powered wireless solid-state drive (SSD) system with merged error correction of high-speed non-contact data links and NAND flash memory. VLSIC Atsutake Kosuge, Junki Hashiba, Toru Kawajiri, So Hasegawa, Tsunaaki Shidei, Hiroki Ishikuro, Tadahiro Kuroda, Ken Takeuchi
2015	J	`jnl`	Relay Transmission Thruchip Interface with Low-Skew 3D Clock Distribution Network. IEICE Trans. Electron. Yasuhiro Take, Tadahiro Kuroda
2015	J	`jnl`	Through Chip Interface Based Three-Dimensional FPGA Architecture Exploration. IEICE Trans. Electron. Li-Chung Hsu, Masato Motomura, Yasuhiro Take, Tadahiro Kuroda
2015	J	`jnl`	Transponder Array System with Universal On-Sheet Reference Scheme for Wireless Mobile Sensor Networks without Battery or Oscillator. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Takahide Terada, Haruki Fukuda, Tadahiro Kuroda
2014	—	`conf`	30.6 An electromagnetic clip connector for in-vehicle LAN to reduce wire harness weight by 30%. ISSCC Atsutake Kosuge, Shu Ishizuka, Lechang Liu, Akira Okada, Masao Taguchi, Hiroki Ishikuro, Tadahiro Kuroda
2014	J	`jnl`	3D NoC with Inductive-Coupling Links for Building-Block SiPs. IEEE Trans. Computers Yasuhiro Take, Hiroki Matsutani, Daisuke Sasaki, Michihiro Koibuchi, Tadahiro Kuroda, Hideharu Amano
2014	J	`jnl`	A 0.15-mm-Thick Noncontact Connector for MIPI Using a Vertical Directional Coupler. IEEE J. Solid State Circuits Atsutake Kosuge, Wataru Mizuhara, Tsunaaki Shidei, Tsutomu Takeya, Noriyuki Miura, Masao Taguchi, Hiroki Ishikuro, Tadahiro Kuroda
2014	—	`conf`	A 352Gb/s inductive-coupling DRAM/SoC interface using overlapping coils with phase division multiplexing and ultra-thin fan-out wafer level package. VLSIC Abdul Raziz Junaidi, Yasuhiro Take, Tadahiro Kuroda
2014	—	`conf`	An 8b extremely area efficient threshold configuring SAR ADC with source voltage shifting technique. ASP-DAC Kentaro Yoshioka, Akira Shikata, Ryota Sekimoto, Tadahiro Kuroda, Hiroki Ishikuro
2014	—	`conf`	F2: 3D stacking technologies for image sensors and memories. ISSCC Yusuke Oike, Makoto Ikeda, Albert Theuwissen, Johannes Solhusvik, Jonathan Chang, Tadahiro Kuroda
2014	J	`jnl`	Highlights of the ISSCC 2013 Processors and High Performance Digital Sessions. IEEE J. Solid State Circuits Timothy C. Fischer, Byeong-Gyu Nam, Leland Chang, Tadahiro Kuroda, Michiel A. P. Pertijs
2014	A	`conf`	Low-latency wireless 3D NoCs via randomized shortcut chips. DATE Hiroki Matsutani, Michihiro Koibuchi, Ikki Fujiwara, Takahiro Kagami, Yasuhiro Take, Tadahiro Kuroda, Paul Bogdan, Radu Marculescu, Hideharu Amano
2014	J	`jnl`	Parametric Resonance Based Frequency Multiplier for Sub-Gigahertz Radio Receiver with 0.3V Supply Voltage. IEICE Trans. Electron. Lechang Liu, Keisuke Ishikawa, Tadahiro Kuroda
2014	J	`jnl`	Wearable sensor-based human activity recognition from environmental background sounds. J. Ambient Intell. Humaniz. Comput. Yi Zhan, Tadahiro Kuroda
2013	—	`conf`	3D clock distribution using vertically/horizontally-coupled resonators. ISSCC Yasuhiro Take, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda
2013	—	`conf`	A 0.15mm-thick non-contact connector for MIPI using vertical directional coupler. ISSCC Wataru Mizuhara, Tsunaaki Shidei, Atsutake Kosuge, Tsutomu Takeya, Noriyuki Miura, Masao Taguchi, Hiroki Ishikuro, Tadahiro Kuroda
2013	—	`conf`	A 0.35-0.8V 8b 0.5-35MS/s 2bit/step extremely-low power SAR ADC. ASP-DAC Kentaro Yoshioka, Akira Shikata, Ryota Sekimoto, Tadahiro Kuroda, Hiroki Ishikuro
2013	J	`jnl`	A 0.5-V 5.2-fJ/Conversion-Step Full Asynchronous SAR ADC With Leakage Power Reduction Down to 650 pW by Boosted Self-Power Gating in 40-nm CMOS. IEEE J. Solid State Circuits Ryota Sekimoto, Akira Shikata, Kentaro Yoshioka, Tadahiro Kuroda, Hiroki Ishikuro
2013	—	`conf`	A 0.8V 1.1pJ/bit inductive-coupling receiver with pulse extracting clock recovery circuit and intermittently operating LNA. RWS Teruo Jyo, Tadahiro Kuroda, Hiroki Ishikuro
2013	C	`conf`	A 1.26mW/Gbps 8 locking cycles versatile all-digital CDR with TDC combined DLL. ISCAS Yuki Urano, Won-Joo Yun, Tadahiro Kuroda, Hiroki Ishikuro
2013	J	`jnl`	A 12-Gb/s Non-Contact Interface With Coupled Transmission Lines. IEEE J. Solid State Circuits Tsutomu Takeya, Lan Nan, Shinya Nakano, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda
2013	—	`conf`	A 12.5Gb/s/link non-contact multi drop bus system with impedance-matched Transmission Line Couplers and Dicode partial-response channel transceivers. ASP-DAC Atsutake Kosuge, Wataru Mizuhara, Noriyuki Miura, Masao Taguchi, Hiroki Ishikuro, Tadahiro Kuroda
2013	J	`jnl`	A 4-10 bit, 0.4-1 V Power Supply, Power Scalable Asynchronous SAR-ADC in 40 nm-CMOS with Wide Supply Voltage Range SAR Controller. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Akira Shikata, Ryota Sekimoto, Kentaro Yoshioka, Tadahiro Kuroda, Hiroki Ishikuro
2013	—	`conf`	A 6nW inductive-coupling wake-up transceiver for reducing standby power of non-contact memory card by 500×. ISSCC Noriyuki Miura, Mitsuko Saito, Masao Taguchi, Tadahiro Kuroda
2013	J	`jnl`	A Scalable 3D Heterogeneous Multicore with an Inductive ThruChip Interface. IEEE Micro Noriyuki Miura, Yusuke Koizumi, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura
2013	—	`conf`	A case for wireless 3D NoCs for CMPs. ASP-DAC Hiroki Matsutani, Paul Bogdan, Radu Marculescu, Yasuhiro Take, Daisuke Sasaki, Hao Zhang, Michihiro Koibuchi, Tadahiro Kuroda, Hideharu Amano
2013	—	`conf`	A scalable 3D heterogeneous multi-core processor with inductive-coupling thruchip interface. COOL Chips Noriyuki Miura, Yusuke Koizumi, Eiichi Sasaki, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura
2013	—	`conf`	A scalable 3D heterogeneous multi-core processor with inductive-coupling thruchip interface. Hot Chips Symposium Noriyuki Miura, Yusuke Koizumi, Eiichi Sasaki, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura
2013	B	`conf`	Adaptive window search using semantic texton forests for real-time object detection. ICIP Yuki Ono, Abdul Raziz Junaidi, Tadahiro Kuroda
2013	J	`jnl`	An Adaptive DAC Settling Waiting Time Optimized Ultra Low Voltage Asynchronous SAR ADC in 40 nm CMOS. IEICE Trans. Electron. Ryota Sekimoto, Akira Shikata, Kentaro Yoshioka, Tadahiro Kuroda, Hiroki Ishikuro
2013	B	`conf`	Demonstration of a heterogeneous multi-core processor with 3-D inductive coupling links. FPL Yusuke Koizumi, Noriyuki Miura, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura
2013	—	`conf`	F3: Emerging technologies for wireline communication. ISSCC Elad Alon, Azita Emami, Gerrit den Besten, Ichiro Fujimori, Tadahiro Kuroda, Masafumi Nogawa, Hisakatsu Yamaguchi
2013	—	`conf`	Hardware-oriented stereo vision algorithm based on 1-D guided filtering and its FPGA implementation. ICECS Katsuki Ohata, Yukitoshi Sanada, Tetsuro Ogaki, Kento Matsuyama, Takanori Ohira, Satoshi Chikuda, Masaki Igarashi, Masayuki Ikebe, Tetsuya Asai, Masato Motomura, Tadahiro Kuroda
2013	—	`conf`	Retrodirective transponder array with universal on-sheet reference for wireless mobile sensor networks without battery or oscillator. ISSCC Haruki Fukuda, Takahide Terada, Tadahiro Kuroda
2013	J	`jnl`	Symbol-Rate Clock Recovery for Integrating DFE Receivers. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Tsutomu Takeya, Tadahiro Kuroda
2013	J	`jnl`	Transmission Line Coupler Design and Mixer-Based Receiver for Dicode Partial Response Communications. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Tsutomu Takeya, Tadahiro Kuroda
2013	J	`jnl`	Vertical Link On/Off Regulations for Inductive-Coupling Based Wireless 3-D NoCs. IEICE Trans. Inf. Syst. Hao Zhang, Hiroki Matsutani, Yasuhiro Take, Tadahiro Kuroda, Hideharu Amano
2012	J	`jnl`	1-W 3.3-16.3-V Boosting Wireless Power Transfer Circuits With Vector Summing Power Controller. IEEE J. Solid State Circuits Kazutoshi Tomita, Ryota Shinoda, Tadahiro Kuroda, Hiroki Ishikuro
2012	J	`jnl`	6 W/25 mm IEICE Trans. Electron. Andrzej Radecki, Hayun Chung, Yoichi Yoshida, Noriyuki Miura, Tsunaaki Shidei, Hiroki Ishikuro, Tadahiro Kuroda
2012	J	`jnl`	A 0.025-0.45 W 60%-Efficiency Inductive-Coupling Power Transceiver With 5-Bit Dual-Frequency Feedforward Control for Non-Contact Memory Cards. IEEE J. Solid State Circuits Hayun Chung, Andrzej Radecki, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda
2012	J	`jnl`	A 0.5 V 1.1 MS/sec 6.3 fJ/Conversion-Step SAR-ADC With Tri-Level Comparator in 40 nm CMOS. IEEE J. Solid State Circuits Akira Shikata, Ryota Sekimoto, Tadahiro Kuroda, Hiroki Ishikuro
2012	—	`conf`	A 0.7V 4.1mW 850Mbps/ch inductive-coupling transceiver with adaptive pulse width controller in 65nm CMOS. RWS Takeshi Matsubara, Isamu Hayashi, Abul Hasan Johari, Tadahiro Kuroda, Hiroki Ishikuro
2012	J	`jnl`	A 1 TB/s 1 pJ/b 6.4 mm IEEE J. Emerg. Sel. Topics Circuits Syst. Noriyuki Miura, Mitsuko Saito, Tadahiro Kuroda
2012	J	`jnl`	A 10-Bit 80-MS/s Decision-Select Successive Approximation TDC in 65-nm CMOS. IEEE J. Solid State Circuits Hayun Chung, Hiroki Ishikuro, Tadahiro Kuroda
2012	—	`conf`	A 100Mb/s 13.7pJ/bit DC-960MHz band plesiochronous IR-UWB receiver with costas-loop based synchronization scheme in 65nm CMOS. CICC Lechang Liu, Hiroki Ishikuro, Tadahiro Kuroda
2012	—	`conf`	A 12.5Gb/s/link non-contact multi drop bus system with impedance-matched transmission line couplers and Dicode partial-response channel transceivers. CICC Atsutake Kosuge, Wataru Mizuhara, Noriyuki Miura, Masao Taguchi, Hiroki Ishikuro, Tadahiro Kuroda
2012	—	`conf`	A 2Gb/s 150mW UWB direct-conversion coherent transceiver with IQ-switching carrier recovery scheme. ISSCC Takayuki Abe, Yuxiang Yuan, Hiroki Ishikuro, Tadahiro Kuroda
2012	—	`conf`	A 5.184Gbps/ch through-chip interface and automated place-and-route design methodology for 3-D integration of 45nm CMOS processors. COOL Chips Yasuhisa Shimazaki, Noriyuki Miura, Tadahiro Kuroda
2012	J	`jnl`	A 65fJ/b Inter-Chip Inductive-Coupling Data Transceivers Using Charge-Recycling Technique for Low-Power Inter-Chip Communication in 3-D System Integration. IEEE Trans. Very Large Scale Integr. Syst. Kiichi Niitsu, Shusuke Kawai, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda
2012	—	`conf`	A 7Gb/s/link non-contact memory module for multi-drop bus system using energy-equipartitioned coupled transmission line. ISSCC Won-Joo Yun, Shinya Nakano, Wataru Mizuhara, Atsutake Kosuge, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda
2012	J	`jnl`	A 9-bit 100 MS/s SAR ADC with Digitally Assisted Background Calibration. IEICE Trans. Electron. Xiaolei Zhu, Yanfei Chen, Sanroku Tsukamoto, Tadahiro Kuroda
2012	—	`conf`	A 9-bit 100MS/s tri-level charge redistribution SAR ADC with asymmetric CDAC array. VLSI-DAT Xiaolei Zhu, Yanfei Chen, Sanroku Tsukamoto, Tadahiro Kuroda
2012	—	`conf`	An 8bit 0.35-0.8V 0.5-30MS/s 2bit/step SAR ADC with wide range threshold configuring comparator. ESSCIRC Kentaro Yoshioka, Akira Shikata, Ryota Sekimoto, Tadahiro Kuroda, Hiroki Ishikuro
2012	B	`conf`	CMA-Cube: A scalable reconfigurable accelerator with 3-D wireless inductive coupling interconnect. FPL Yusuke Koizumi, Eiichi Sasaki, Hideharu Amano, Hiroki Matsutani, Yasuhiro Take, Tadahiro Kuroda, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura
2012	—	`conf`	Dynamic power control with a heterogeneous multi-core system using a 3-D wireless inductive coupling interconnect. FPT Yusuke Koizumi, Hideharu Amano, Hiroki Matsutani, Noriyuki Miura, Tadahiro Kuroda, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura
2012	J	`jnl`	Rotary Coding for Power Reduction and S/N Improvement in Inductive-Coupling Data Communication. IEEE J. Solid State Circuits Andrzej Radecki, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda
2012	—	`conf`	Session 23 overview: Advances in heterogeneous integration: Technology directions subcommittee. ISSCC Tadahiro Kuroda, David Ruffieux
2012	J	`jnl`	Simultaneous 6-Gb/s Data and 10-mW Power Transmission Using Nested Clover Coils for Noncontact Memory Card. IEEE J. Solid State Circuits Andrzej Radecki, Yuxiang Yuan, Noriyuki Miura, Iori Aikawa, Yasuhiro Take, Hiroki Ishikuro, Tadahiro Kuroda
2012	—	`conf`	Simultaneous data and power transmission using nested clover coils. ASP-DAC Yasuhiro Take, Hayun Chung, Noriyuki Miura, Tadahiro Kuroda
2012	—	`conf`	Vertical Link On/Off Control Methods for Wireless 3-D NoCs. ARCS Hao Zhang, Hiroki Matsutani, Yasuhiro Take, Tadahiro Kuroda, Hideharu Amano
2011	—	`conf`	1W 3.3V-to-16.3V boosting wireless power transfer circuits with vector summing power controller. A-SSCC Kazutoshi Tomita, Ryota Shinoda, Tadahiro Kuroda, Hiroki Ishikuro
2011	—	`ch.`	3-D NoC on Inductive Wireless Interconnect. 3D Integration for NoC-based SoC Architectures Hiroki Matsutani, Michihiro Koibuchi, Tadahiro Kuroda, Hideharu Amano
2011	—	`conf`	6W/25mm ISSCC Andrzej Radecki, Hayun Chung, Yoichi Yoshida, Noriyuki Miura, Tsunaaki Shidei, Hiroki Ishikuro, Tadahiro Kuroda
2011	J	`jnl`	A 0.55 V 10 fJ/bit Inductive-Coupling Data Link and 0.7 V 135 fJ/Cycle Clock Link With Dual-Coil Transmission Scheme. IEEE J. Solid State Circuits Noriyuki Miura, Tsunaaki Shidei, Yuxiang Yuan, Shusuke Kawai, Keita Takatsu, Yuji Kiyota, Yuichi Asano, Tadahiro Kuroda
2011	—	`conf`	A 0.6V noise rejectable all-digital CDR with free running TDC for a pulse-based inductive-coupling interface. A-SSCC Won-Joo Yun, Hiroki Ishikuro, Tadahiro Kuroda
2011	—	`conf`	A 12Gb/s non-contact interface with coupled transmission lines. ISSCC Tsutomu Takeya, Lan Nan, Shinya Nakano, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda
2011	J	`jnl`	A 14-GHz AC-Coupled Clock Distribution Scheme With Phase Averaging Technique Using Single LC-VCO and Distributed Phase Interpolators. IEEE Trans. Very Large Scale Integr. Syst. Kiichi Niitsu, Vishwesh V. Kulkarni, Shinmo Kang, Hiroki Ishikuro, Tadahiro Kuroda
2011	—	`conf`	A 2.7Gb/s/mm ISSCC Noriyuki Miura, Yasuhiro Take, Mitsuko Saito, Yoichi Yoshida, Tadahiro Kuroda
2011	J	`jnl`	A 30 Gb/s/Link 2.2 Tb/s/mm IEEE J. Solid State Circuits Yasuhiro Take, Noriyuki Miura, Tadahiro Kuroda
2011	—	`conf`	A 40nm 50S/s-8MS/s ultra low voltage SAR ADC with timing optimized asynchronous clock generator. ESSCIRC Ryota Sekimoto, Akira Shikata, Tadahiro Kuroda, Hiroki Ishikuro
2011	J	`jnl`	A 60-GHz Injection-Locked Frequency Divider Using Multi-Order IEICE Trans. Electron. Keita Takatsu, Hirotaka Tamura, Takuji Yamamoto, Yoshiyasu Doi, Kouichi Kanda, Takayuki Shibasaki, Tadahiro Kuroda
2011	—	`conf`	A vertical bubble flow network using inductive-coupling for 3-D CMPs. NOCS Hiroki Matsutani, Yasuhiro Take, Daisuke Sasaki, Masayuki Kimura, Yuki Ono, Yukinori Nishiyama, Michihiro Koibuchi, Tadahiro Kuroda, Hideharu Amano
2011	J	`jnl`	Analysis and Techniques for Mitigating Interference From Power/Signal Lines and to SRAM Circuits in CMOS Inductive-Coupling Link for Low-Power 3-D System Integration. IEEE Trans. Very Large Scale Integr. Syst. Kiichi Niitsu, Yasufumi Sugimori, Yoshinori Kohama, Kenichi Osada, Naohiko Irie, Hiroki Ishikuro, Tadahiro Kuroda
2011	—	`conf`	Rotary coding for power reduction and S/N improvement in inductive-coupling data communication. A-SSCC Andrzej Radecki, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda
2011	C	`conf`	ThruChip interface (TCI) for 3D networks on chip. VLSI-SoC Tadahiro Kuroda
2010	J	`jnl`	2 Gb/s 15 pJ/b/chip Inductive-Coupling Programmable Bus for NAND Flash Memory Stacking. IEEE J. Solid State Circuits Mitsuko Saito, Yasufumi Sugimori, Yoshinori Kohama, Yoichi Yoshida, Noriyuki Miura, Hiroki Ishikuro, Takayasu Sakurai, Tadahiro Kuroda
2010	J	`jnl`	3-D System Integration of Processor and Multi-Stacked SRAMs Using Inductive-Coupling Link. IEEE J. Solid State Circuits Makoto Saen, Kenichi Osada, Yasuyuki Okuma, Kiichi Niitsu, Yasuhisa Shimazaki, Yasufumi Sugimori, Yoshinori Kohama, Kazutaka Kasuga, Itaru Nonomura, Naohiko Irie, Toshihiro Hattori, Atsushi Hasegawa, Tadahiro Kuroda
2010	J	`jnl`	47% Power Reduction and 91% Area Reduction in Inductive-Coupling Programmable Bus for NAND Flash Memory Stacking. IEEE Trans. Circuits Syst. I Regul. Pap. Mitsuko Saito, Yoichi Yoshida, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda
2010	—	`conf`	A 2.5Gb/s/ch 4PAM inductive-coupling transceiver for non-contact memory card. ISSCC Shusuke Kawai, Hiroki Ishikuro, Tadahiro Kuroda
2010	—	`conf`	A 2Gb/s 1.8pJ/b/chip inductive-coupling through-chip bus for 128-Die NAND-Flash memory stacking. ISSCC Mitsuko Saito, Noriyuki Miura, Tadahiro Kuroda
2010	J	`jnl`	A 4-Gbps Quasi-Millimeter-Wave Transmitter in 65 nm CMOS and a Fast Carrier and Symbol Timing Recovery Scheme. IEICE Trans. Electron. Vishal V. Kulkarni, Hiroki Ishikuro, Tadahiro Kuroda
2010	—	`conf`	A 60-GHz 1.65mW 25.9% locking range multi-order LC oscillator based injection locked frequency divider in 65nm CMOS. CICC Keita Takatsu, Hirotaka Tamura, Takuji Yamamoto, Yoshiyasu Doi, Kouichi Kanda, Takayuki Shibasaki, Tadahiro Kuroda
2010	—	`conf`	A 6Gb/s receiver with discrete-time based channel filtering for wireline FDM communications. CICC Tsutomu Takeya, Kazuhisa Sunaga, Koichi Yamaguchi, Hideyuki Sugita, Yoichi Yoshida, Masayuki Mizuno, Tadahiro Kuroda
2010	J	`jnl`	A 9-bit 100-MS/s 1.46-mW Tri-Level SAR ADC in 65 nm CMOS. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yanfei Chen, Sanroku Tsukamoto, Tadahiro Kuroda
2010	J	`jnl`	A Dynamic Offset Control Technique for Comparator Design in Scaled CMOS Technology. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Xiaolei Zhu, Yanfei Chen, Masaya Kibune, Yasumoto Tomita, Takayuki Hamada, Hirotaka Tamura, Sanroku Tsukamoto, Tadahiro Kuroda
2010	—	`conf`	A versatile recognition processor for sensor network applications. ASP-DAC Risako Takashima, Yuya Hanai, Yuichi Hori, Tadahiro Kuroda
2010	—	`conf`	An 8Tb/s 1pJ/b 0.8mm ISSCC Noriyuki Miura, Kazutaka Kasuga, Mitsuko Saito, Tadahiro Kuroda
2010	J	`jnl`	An Inductive-Coupling DC Voltage Transceiver for Highly Parallel Wafer-Level Testing. IEEE J. Solid State Circuits Yoichi Yoshida, Koichi Nose, Yoshihiro Nakagawa, Koichiro Noguchi, Yasuhiro Morita, Masamoto Tago, Masayuki Mizuno, Tadahiro Kuroda
2010	J	`jnl`	Analysis of Inductive Coupling and Design of Rectifier Circuit for Inter-Chip Wireless Power Link. IEICE Trans. Electron. Yuxiang Yuan, Yoichi Yoshida, Tadahiro Kuroda
2010	J	`jnl`	Modeling and Experimental Verification of Misalignment Tolerance in Inductive-Coupling Inter-Chip Link for Low-Power 3-D System Integration. IEEE Trans. Very Large Scale Integr. Syst. Kiichi Niitsu, Yoshinori Kohama, Yasufumi Sugimori, Kazutaka Kasuga, Kenichi Osada, Naohiko Irie, Hiroki Ishikuro, Tadahiro Kuroda
2010	J	`jnl`	Split Capacitor DAC Mismatch Calibration in Successive Approximation ADC. IEICE Trans. Electron. Yanfei Chen, Xiaolei Zhu, Hirotaka Tamura, Masaya Kibune, Yasumoto Tomita, Takayuki Hamada, Masato Yoshioka, Kiyoshi Ishikawa, Takeshi Takayama, Junji Ogawa, Sanroku Tsukamoto, Tadahiro Kuroda
2010	J	`jnl`	Wireless proximity interfaces with a pulse-based inductive coupling technique. IEEE Commun. Mag. Hiroki Ishikuro, Tadahiro Kuroda
2009	—	`conf`	47% power reduction and 91% area reduction in inductive-coupling programmable bus for NAND flash memory stacking. CICC Mitsuko Saito, Yasufumi Sugimori, Yoshinori Kohama, Yoichi Yoshida, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda
2009	—	`conf`	A 1 GHz CMOS comparator with dynamic offset control technique. ASP-DAC Xiaolei Zhu, Sanroku Tsukamoto, Tadahiro Kuroda
2009	J	`jnl`	A 107-pJ/bit 100-kb/s 0.18- muhboxm Capacitive-Coupling Transceiver With Data Edge Signaling and DC Power-Free Pulse Detector for Printable Communication Sheet. IEEE Trans. Circuits Syst. I Regul. Pap. Lechang Liu, Makoto Takamiya, Tsuyoshi Sekitani, Yoshiaki Noguchi, Shintaro Nakano, Koichiro Zaitsu, Tadahiro Kuroda, Takao Someya, Takayasu Sakurai
2009	—	`conf`	A 2Gb/s 15pJ/b/chip Inductive-Coupling programmable bus for NAND Flash memory stacking. ISSCC Yasufumi Sugimori, Yoshinori Kohama, Mitsuko Saito, Yoichi Yoshida, Noriyuki Miura, Hiroki Ishikuro, Takayasu Sakurai, Tadahiro Kuroda
2009	J	`jnl`	A 750 Mb/s, 12 pJ/b, 6-to-10 GHz CMOS IR-UWB Transmitter With Embedded On-Chip Antenna. IEEE J. Solid State Circuits Vishal V. Kulkarni, Muhammad Muqsith, Kiichi Niitsu, Hiroki Ishikuro, Tadahiro Kuroda
2009	J	`jnl`	A High-Speed Inductive-Coupling Link With Burst Transmission. IEEE J. Solid State Circuits Noriyuki Miura, Yoshinori Kohama, Yasufumi Sugimori, Hiroki Ishikuro, Takayasu Sakurai, Tadahiro Kuroda
2009	—	`conf`	A versatile recognition processor employing Haar-like feature and cascaded classifier. ISSCC Yuya Hanai, Yuichi Hori, Jun Nishimura, Tadahiro Kuroda
2009	—	`conf`	A wireless real-time on-chip bus trace system. ASP-DAC Shusuke Kawai, Takayuki Ikari, Yutaka Takikawa, Hiroki Ishikuro, Tadahiro Kuroda
2009	—	`conf`	An inductive-coupling link for 3D integration of a 90nm CMOS processor and a 65nm CMOS SRAM. ISSCC Kiichi Niitsu, Yasuhisa Shimazaki, Yasufumi Sugimori, Yoshinori Kohama, Kazutaka Kasuga, Itaru Nonomura, Makoto Saen, Shigenobu Komatsu, Kenichi Osada, Naohiko Irie, Toshihiro Hattori, Atsushi Hasegawa, Tadahiro Kuroda
2009	J	`jnl`	Architecture Design of Versatile Recognition Processor for Sensornet Applications. IEEE Micro Yuichi Hori, Yuya Hanai, Jun Nishimura, Tadahiro Kuroda
2009	B	`conf`	Face detection through compact classifier using Adaptive Look-Up-Table. ICIP Yuya Hanai, Tadahiro Kuroda
2009	B	`conf`	MuCCRA-Cube: A 3D dynamically reconfigurable processor with inductive-coupling link. FPL Shotaro Saito, Yoshinori Kohama, Yasufumi Sugimori, Yohei Hasegawa, Hiroki Matsutani, Toru Sano, Kazutaka Kasuga, Yoichi Yoshida, Kiichi Niitsu, Noriyuki Miura, Tadahiro Kuroda, Hideharu Amano
2009	—	`conf`	Split capacitor DAC mismatch calibration in successive approximation ADC. CICC Yanfei Chen, Xiaolei Zhu, Hirotaka Tamura, Masaya Kibune, Yasumoto Tomita, Takayuki Hamada, Masato Yoshioka, Kiyoshi Ishikawa, Takeshi Takayama, Junji Ogawa, Sanroku Tsukamoto, Tadahiro Kuroda
2009	—	`conf`	Wireless DC voltage transmission using inductive-coupling channelfor highly-parallel wafer-level testing. ISSCC Yoichi Yoshida, Koichi Nose, Yoshihiro Nakagawa, Koichiro Noguchi, Yasuhiro Morita, Masamoto Tago, Tadahiro Kuroda, Masayuki Mizuno
2008	J	`jnl`	20-GHz Quadrature Injection-Locked LC Dividers With Enhanced Locking Range. IEEE J. Solid State Circuits Takayuki Shibasaki, Hirotaka Tamura, Kouichi Kanda, Hisakatsu Yamaguchi, Junji Ogawa, Tadahiro Kuroda
2008	J	`jnl`	A 0.14 pJ/b Inductive-Coupling Transceiver With Digitally-Controlled Precise Pulse Shaping. IEEE J. Solid State Circuits Noriyuki Miura, Hiroki Ishikuro, Kiichi Niitsu, Takayasu Sakurai, Tadahiro Kuroda
2008	—	`conf`	A 107pJ/b 100kb/s 0.18μm Capacitive-Coupling Transceiver for Printable Communication Sheet. ISSCC Lechang Liu, Makoto Takamiya, Tsuyoshi Sekitani, Yoshiaki Noguchi, Shintaro Nakano, Koichiro Zaitsu, Tadahiro Kuroda, Takao Someya, Takayasu Sakurai
2008	J	`jnl`	A 2 Gb/s Bi-Directional Inter-Chip Data Transceiver With Differential Inductors for High Density Inductive Channel Array. IEEE J. Solid State Circuits Yoichi Yoshida, Noriyuki Miura, Tadahiro Kuroda
2008	—	`conf`	A dynamic offset control technique for comparator design in scaled CMOS technology. CICC Xiaolei Zhu, Yanfei Chen, Masaya Kibune, Yasumoto Tomita, Takayuki Hamada, Hirotaka Tamura, Sanroku Tsukamoto, Tadahiro Kuroda
2008	—	`conf`	An 11Gb/s Inductive-Coupling Link with Burst Transmission. ISSCC Noriyuki Miura, Yoshinori Kohama, Yasufumi Sugimori, Hiroki Ishikuro, Takayasu Sakurai, Tadahiro Kuroda
2008	J	`jnl`	Constant Magnetic Field Scaling in Inductive-Coupling Data Link. IEICE Trans. Electron. Daisuke Mizoguchi, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda
2008	—	`conf`	Eating habits monitoring using wireless wearable in-ear microphone. ISWPC Jun Nishimura, Tadahiro Kuroda
2008	C	`conf`	Speaker Siglet Detection for Business Microscope. ICMLA Jun Nishimura, Nobuo Sato, Tadahiro Kuroda
2008	A*	`conf`	Speech "Siglet" Detection for Business Microscope (concise contribution). PerCom Jun Nishimura, Nobuo Sato, Tadahiro Kuroda
2007	J	`jnl`	18-GHz Clock Distribution Using a Coupled VCO Array. IEICE Trans. Electron. Takayuki Shibasaki, Hirotaka Tamura, Kouichi Kanda, Hisakatsu Yamaguchi, Junji Ogawa, Tadahiro Kuroda
2007	—	`conf`	A 0.14pJ/b Inductive-Coupling Inter-Chip Data Transceiver with Digitally-Controlled Precise Pulse Shaping. ISSCC Noriyuki Miura, Hiroki Ishikuro, Takayasu Sakurai, Tadahiro Kuroda
2007	J	`jnl`	A 0.79-mm IEEE J. Solid State Circuits Yuichi Hori, Tadahiro Kuroda
2007	J	`jnl`	A 1 Tb/s 3 W Inductive-Coupling Transceiver for 3D-Stacked Inter-Chip Clock and Data Link. IEEE J. Solid State Circuits Noriyuki Miura, Daisuke Mizoguchi, Mari Inoue, Kiichi Niitsu, Yoshihiro Nakagawa, Masamoto Tago, Muneo Fukaishi, Takayasu Sakurai, Tadahiro Kuroda
2007	—	`conf`	A 1Tb/s 3W Inductive-Coupling Transceiver Chip. ASP-DAC Noriyuki Miura, Tadahiro Kuroda
2007	J	`jnl`	A 20-Gb/s Simultaneous Bidirectional Transceiver Using a Resistor-Transconductor Hybrid in 0.11-µm CMOS. IEEE J. Solid State Circuits Yasumoto Tomita, Hirotaka Tamura, Masaya Kibune, Junji Ogawa, Kohtaroh Gotoh, Tadahiro Kuroda
2007	J	`jnl`	A 40-44 Gb/s 3 × Oversampling CMOS CDR/1: 16 DEMUX. IEEE J. Solid State Circuits Nikola Nedovic, Nestoras Tzartzanis, Hirotaka Tamura, Francis M. Rotella, Magnus Wiklund, Yuma Mizutani, Yusuke Okaniwa, Tadahiro Kuroda, Junji Ogawa, William W. Walker
2007	—	`conf`	A 40-to-44Gb/s 3�? Oversampling CMOS CDR/1: 16 DEMUX. ISSCC Nikola Nedovic, Nestoras Tzartzanis, Hirotaka Tamura, Francis M. Rotella, Magnus Wiklund, Yuma Mizutani, Yusuke Okaniwa, Tadahiro Kuroda, Junji Ogawa, William W. Walker
2007	—	`conf`	A 750Mb/s 12pJ/b 6-to-10GHz Digital UWB Transmitter. CICC Vishal V. Kulkarni, Muhammad Muqsith, Hiroki Ishikuro, Tadahiro Kuroda
2007	—	`conf`	An Attachable Wireless Chip Access Interface for Arbitrary Data Rate Using Pulse-Based lnductive-Coupling through LSI Package. ISSCC Hiroki Ishikuro, Toshihiko Sugahara, Tadahiro Kuroda
2007	J	`jnl`	Crosstalk Countermeasures for High-Density Inductive-Coupling Channel Array. IEEE J. Solid State Circuits Noriyuki Miura, Takayasu Sakurai, Tadahiro Kuroda
2007	J	`jnl`	Daisy Chain Transmitter for Power Reduction in Inductive-Coupling CMOS Link. IEICE Trans. Electron. Kiichi Niitsu, Noriyuki Miura, Mari Inoue, Yoshihiro Nakagawa, Masamoto Tago, Masayuki Mizuno, Takayasu Sakurai, Tadahiro Kuroda
2007	J	`jnl`	Special Section on Low-Power, High-Speed LSIs and Related Technologies. IEICE Trans. Electron. Tadahiro Kuroda
2007	—	`conf`	Wideband Inductive-coupling Interface for High-performance Portable System. CICC Hiroki Ishikuro, Noriyuki Miura, Tadahiro Kuroda
2006	J	`jnl`	A 1.2 Gbps Non-contact 3D-Stacked Inter-Chip Data Communications Technology. IEICE Trans. Electron. Daisuke Mizoguchi, Noriyuki Miura, Takayasu Sakurai, Tadahiro Kuroda
2006	J	`jnl`	A 195-gb/s 1.2-W inductive inter-chip wireless superconnect with transmit power control scheme for 3-D-stacked system in a package. IEEE J. Solid State Circuits Noriyuki Miura, Daisuke Mizoguchi, Mari Inoue, Takayasu Sakurai, Tadahiro Kuroda
2006	—	`conf`	A 1Tb/s 3W inductive-coupling transceiver for inter-chip clock and data link. ISSCC Noriyuki Miura, Daisuke Mizoguchi, Mari Inoue, Kiichi Niitsu, Yoshihiro Nakagawa, Masamoto Tago, Muneo Fukaishi, Takayasu Sakurai, Tadahiro Kuroda
2006	—	`conf`	A 20Gb/s Bidirectional Transceiver Using a Resistor-Transconductor Hybrid. ISSCC Yasumoto Tomita, Hirotaka Tamura, Masaya Kibune, Junji Ogawa, Kohtaroh Gotoh, Tadahiro Kuroda
2006	J	`jnl`	A CMOS ultra-wideband impulse radio transceiver for 1-mb/s data communications and ±2.5-cm range finding. IEEE J. Solid State Circuits Takahide Terada, Shingo Yoshizumi, Muhammad Muqsith, Yukitoshi Sanada, Tadahiro Kuroda
2006	Misc	`conf`	Active Crosstalk Cancel for High-Density Inductive Inter-chip Wireless Communication. VLSI Design Amit Kumar, Noriyuki Miura, Muhammad Muqsith, Tadahiro Kuroda
2006	—	`conf`	Chip-to-Chip Inductive Wireless Power Transmission System for SiP Applications. CICC Kohei Onizuka, Hiroshi Kawaguchi, Makoto Takamiya, Tadahiro Kuroda, Takayasu Sakurai
2006	J	`jnl`	System LSI: Challenges and Opportunities. IEICE Trans. Electron. Tadahiro Kuroda
2005	J	`jnl`	A 10-Gb/s receiver with series equalizer and on-chip ISI monitor in 0.11-μm CMOS. IEEE J. Solid State Circuits Yasumoto Tomita, Masaya Kibune, Junji Ogawa, William W. Walker, Hirotaka Tamura, Tadahiro Kuroda
2005	J	`jnl`	A 40-Gb/s CMOS clocked comparator with bandwidth modulation technique. IEEE J. Solid State Circuits Yusuke Okaniwa, Hirotaka Tamura, Masaya Kibune, Daisuke Yamazaki, Tsz-Shing Cheung, Junji Ogawa, Nestoras Tzartzanis, William W. Walker, Tadahiro Kuroda
2005	J	`jnl`	Analysis and design of inductive coupling and transceiver circuit for inductive inter-chip wireless superconnect. IEEE J. Solid State Circuits Noriyuki Miura, Daisuke Mizoguchi, Takayasu Sakurai, Tadahiro Kuroda
2005	J	`jnl`	Introduction to the Special Issue. IEEE J. Solid State Circuits Bruce Gieseke, Tadahiro Kuroda
2004	—	`conf`	A Real-Time Multi Face Detection Technique Using Positive-Negative Lines-of-Face Template. ICPR (1) Yuichi Hori, Kenji Shimizu, Yutaka Nakamura, Tadahiro Kuroda
2004	—	`conf`	Cross talk countermeasures in inductive inter-chip wireless superconnect. CICC Noriyuki Miura, Daisuke Mizoguchi, Takayasu Sakurai, Tadahiro Kuroda
2004	—	`conf`	Practical methodology of post-layout gate sizing for 15% more power saving. ASP-DAC Noriyuki Miura, Naoki Kato, Tadahiro Kuroda
2004	—	`conf`	Transceiver circuits for pulse-based ultra-wideband. ISCAS (4) Takahide Terada, Shingo Yoshizumi, Yukitoshi Sanada, Tadahiro Kuroda
2002	C	`conf`	Low-Power, High-Speed CMOS VLSI Design. ICCD Tadahiro Kuroda
2002	A	`conf`	Optimization and control of ICCAD Tadahiro Kuroda
2001	J	`jnl`	A bitline leakage compensation scheme for low-voltage SRAMs. IEEE J. Solid State Circuits Ken-ichi Agawa, Hiroyuki Hara, Toshinari Takayanagi, Tadahiro Kuroda
2001	—	`conf`	Utilizing surplus timing for power reduction. CICC Mototsugu Hamada, Yukio Ootaguro, Tadahiro Kuroda
2000	J	`jnl`	A 60-MHz 240-mW MPEG-4 videophone LSI with 16-Mb embedded DRAM. IEEE J. Solid State Circuits Masafumi Takahashi, Tsuyoshi Nishikawa, Mototsugu Hamada, Toshinari Takayanagi, Hideho Arakida, Noriaki Machida, Hideaki Yamamoto, Toshihide Fujiyoshi, Yoko Ohashi, Osamu Yamagishi, Tatsuo Samata, Atsushi Asano, Toshihiro Terazawa, Kenji Ohmori, Yoshinori Watanabe, Hiroki Nakamura, Shigenobu Minami, Tadahiro Kuroda, Tohru Furuyama
2000	J	`jnl`	Low-power CMOS digital design with dual embedded adaptive power supplies. IEEE J. Solid State Circuits Tadahiro Kuroda, Mototsugu Hamada
1999	A	`conf`	Variable supply-voltage scheme with 95%-efficiency DC-DC converter for MPEG-4 codec. ISLPED Fuyuki Ichiba, Kojiro Suzuki, Shinji Mita, Tadahiro Kuroda, Tohru Furuyama
1998	J	`jnl`	A 60-mW MPEG4 video codec using clustered voltage scaling with variable supply-voltage scheme. IEEE J. Solid State Circuits Masafumi Takahashi, Mototsugu Hamada, Tsuyoshi Nishikawa, Hideho Arakida, Tetsuya Fujita, Fumitoshi Hatori, Shinji Mita, Kojiro Suzuki, Akihiko Chiba, Toshihiro Terazawa, Fumihiko Sano, Yoshinori Watanabe, Kimiyoshi Usami, Mutsunori Igarashi, Takashi Ishikawa, Masahiro Kanazawa, Tadahiro Kuroda, Tohru Furuyama
1998	—	`conf`	A top-down low power design technique using clustered voltage scaling with variable supply-voltage scheme. CICC Mototsugu Hamada, Masafumi Takahashi, Hideho Arakida, Akihiko Chiba, Toshihiro Terazawa, Takashi Ishikawa, Masahiro Kanazawa, Mutsunori Igarashi, Kimiyoshi Usami, Tadahiro Kuroda
1998	A*	`conf`	Design Methodology of Ultra Low-Power MPEG4 Codec Core Exploiting Voltage Scaling Techniques. DAC Kimiyoshi Usami, Mutsunori Igarashi, Takashi Ishikawa, Masahiro Kanazawa, Masafumi Takahashi, Mototsugu Hamada, Hideho Arakida, Toshihiro Terazawa, Tadahiro Kuroda
1998	J	`jnl`	Variable supply-voltage scheme for low-power high-speed CMOS digital design. IEEE J. Solid State Circuits Tadahiro Kuroda, Kojiro Suzuki, Shinji Mita, Tetsuya Fujita, Fumiyuki Yamane, Fumihiko Sano, Akihiko Chiba, Yoshinori Watanabe, Koji Matsuda, Takeo Maeda, Takayasu Sakurai, Tohru Furuyama
1996	J	`jnl`	A 0.9-V, 150-MHz, 10-mW, 4 mm IEEE J. Solid State Circuits Tadahiro Kuroda, Tetsuya Fujita, Shinji Mita, Tetsu Nagamatsu, Shinichi Yoshioka, Kojiro Suzuki, Fumihiko Sano, Masayuki Norishima, Masayuki Murota, Makoto Kako, Masaaki Kinugawa, Masakazu Kakurnu, Takayasu Sakurai
1996	J	`jnl`	Capacitor-free level-sensitive active pull-down ECL circuit with self-adjusting driving capability. IEEE J. Solid State Circuits Tadahiro Kuroda, Tetsuya Fujita, Makato Noda, Yasushi Itabashi, Satohiko Kabumoto, T. S. Wong, Dave Beeson, Dave Gray
1996	A	`conf`	Substrate noise influence on circuit performance in variable threshold-voltage scheme. ISLPED Tadahiro Kuroda, Tetsuya Fujita, Shinji Mita, Toshiaki Mori, Kenji Matsuo, Masakazu Kakumu, Takayasu Sakurai
1996	J	`jnl`	Threshold-Volgage control schemes through substrate-bias for low-power high-speed CMOS LSI design. J. VLSI Signal Process. Tadahiro Kuroda, Takayasu Sakurai
1994	J	`jnl`	Analysis and optimization of BiCMOS gate circuits. IEEE J. Solid State Circuits Tadahiro Kuroda, Yoshinori Sakata, Kenji Matsuo
1992	J	`jnl`	Automated bias control (ABC) circuit for high-performance VLSIs. IEEE J. Solid State Circuits Tadahiro Kuroda, Toshiyuki Fukunaga, Kenji Matsuo, Kazuhiko Kasai, Ayako Hirata, Shinji Fujii, Masahiro Kimura, Hiroaki Suzuki