Tadahiko Sugibayashi

40 papers B 2C 3Journal 23Unranked 12

Year	Rank	Type	Title / Venue / Authors
2022	J	`jnl`	28nm Atom-Switch FPGA: Static Timing Analysis and Evaluation. IEICE Trans. Electron. Xu Bai, Ryusuke Nebashi, Makoto Miyamura, Kazunori Funahashi, Naoki Banno, Koichiro Okamoto, Hideaki Numata, Noriyuki Iguchi, Tadahiko Sugibayashi, Toshitsugu Sakamoto, Munehiro Tada
2022	J	`jnl`	Via-Switch FPGA: 65-nm CMOS Implementation and Evaluation. IEEE J. Solid State Circuits Xu Bai, Naoki Banno, Makoto Miyamura, Ryusuke Nebashi, Koichiro Okamoto, Hideaki Numata, Noriyuki Iguchi, Masanori Hashimoto, Tadahiko Sugibayashi, Toshitsugu Sakamoto, Munehiro Tada
2020	—	`conf`	33.3 Via-Switch FPGA: 65nm CMOS Implementation and Architecture Extension for Al Applications. ISSCC Masanori Hashimoto, Xu Bai, Naoki Banno, Munehiro Tada, Toshitsugu Sakamoto, Jaehoon Yu, Ryutaro Doi, Yusuke Araki, Hidetoshi Onodera, Takashi Imagawa, Hiroyuki Ochi, Kazutoshi Wakabayashi, Yukio Mitsuyama, Tadahiko Sugibayashi
2020	B	`conf`	A 171k-LUT Nonvolatile FPGA using Cu Atom-Switch Technology in 28nm CMOS. FPL Ryusuke Nebashi, Naoki Banno, Makoto Miyamura, Xu Bai, Kazunori Funahashi, Koichiro Okamoto, Noriyuki Iguchi, Hideaki Numata, Tadahiko Sugibayashi, Toshitsugu Sakamoto, Munehiro Tada
2020	—	`conf`	ON-state retention of Atom Switch eNVM for IoT/AI Inference Solution. IRPS Koichiro Okamoto, Ryusuke Nebashi, Naoki Banno, Xu Bai, Hideaki Numata, Noriyuki Iguchi, Makoto Miyamura, Hiromitsu Hada, Kazunori Funahashi, Tadahiko Sugibayashi, Toshitsugu Sakamoto, Munehiro Tada
2018	J	`jnl`	Sensor Signal Processing Using High-Level Synthesis With a Layered Architecture. IEEE Embed. Syst. Lett. Hiroki Hihara, Akira Iwasaki, Masanori Hashimoto, Hiroyuki Ochi, Yukio Mitsuyama, Hidetoshi Onodera, Hiroyuki Kanbara, Kazutoshi Wakabayashi, Tadahiko Sugibayashi, Takashi Takenaka, Hiromitsu Hada, Munehiro Tada, Makoto Miyamura, Toshitsugu Sakamoto
2018	J	`jnl`	Via-Switch FPGA: Highly Dense Mixed-Grained Reconfigurable Architecture With Overlay Via-Switch Crossbars. IEEE Trans. Very Large Scale Integr. Syst. Hiroyuki Ochi, Kosei Yamaguchi, Tetsuaki Fujimoto, Junshi Hotate, Takashi Kishimoto, Toshiki Higashi, Takashi Imagawa, Ryutaro Doi, Munehiro Tada, Tadahiko Sugibayashi, Wataru Takahashi, Kazutoshi Wakabayashi, Hidetoshi Onodera, Yukio Mitsuyama, Jaehoon Yu, Masanori Hashimoto
2017	J	`jnl`	NanoBridge-Based FPGA in High-Temperature Environments. IEEE Micro Makoto Miyamura, Toshitsugu Sakamoto, Xu Bai, Yukihide Tsuji, Ayuka Morioka, Ryusuke Nebashi, Munehiro Tada, Naoki Banno, Koichiro Okamoto, Noriyuki Iguchi, Hiromitsu Hada, Tadahiko Sugibayashi, Yuya Nagamatsu, Soichi Ookubo, Takuma Shirai, Fumihito Sugai, Masayuki Inaba
2016	—	`conf`	A 2× logic density Programmable Logic array using atom switch fully implemented with logic transistors at 40nm-node and beyond. VLSI Circuits Yukihide Tsuji, Xu Bai, Ayuka Morioka, Makoto Miyamura, Ryusuke Nebashi, Toshitsugu Sakamoto, Munehiro Tada, Naoki Banno, Koichiro Okamoto, Noriyuki Iguchi, Hiromitsu Hada, Tadahiko Sugibayashi
2016	B	`conf`	A highly-dense mixed grained reconfigurable architecture with overlay crossbar interconnect using via-switch. FPL Junshi Hotate, Takashi Kishimoto, Toshiki Higashi, Hiroyuki Ochi, Ryutaro Doi, Munehiro Tada, Tadahiko Sugibayashi, Kazutoshi Wakabayashi, Hidetoshi Onodera, Yukio Mitsuyama, Masanori Hashimoto
2016	J	`jnl`	Evaluation of Soft-Delay-Error Effects in Content-Addressable Memory. J. Multiple Valued Log. Soft Comput. Naoya Onizawa, Noboru Sakimura, Ryusuke Nebashi, Tadahiko Sugibayashi, Takahiro Hanyu
2015	J	`jnl`	Nonvolatile Logic-in-Memory LSI Using Cycle-Based Power Gating and its Application to Motion-Vector Prediction. IEEE J. Solid State Circuits Masanori Natsui, Daisuke Suzuki, Noboru Sakimura, Ryusuke Nebashi, Yukihide Tsuji, Ayuka Morioka, Tadahiko Sugibayashi, Sadahiko Miura, Hiroaki Honjo, Keizo Kinoshita, Shoji Ikeda, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu
2014	—	`conf`	10.5 A 90nm 20MHz fully nonvolatile microcontroller for standby-power-critical applications. ISSCC Noboru Sakimura, Yukihide Tsuji, Ryusuke Nebashi, Hiroaki Honjo, Ayuka Morioka, Kunihiko Ishihara, Keizo Kinoshita, Shunsuke Fukami, Sadahiko Miura, Naoki Kasai, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu, Tadahiko Sugibayashi
2014	J	`jnl`	A Nonvolatile Associative Memory-Based Context-Driven Search Engine Using 90 nm CMOS/MTJ-Hybrid Logic-in-Memory Architecture. IEEE J. Emerg. Sel. Topics Circuits Syst. Hooman Jarollahi, Naoya Onizawa, Vincent Gripon, Noboru Sakimura, Tadahiko Sugibayashi, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu, Warren J. Gross
2014	J	`jnl`	A compact low-power nonvolatile flip-flop using domain-wall-motion-device-based single-ended structure. IEICE Electron. Express Daisuke Suzuki, Noboru Sakimura, Masanori Natsui, Akira Mochizuki, Tadahiko Sugibayashi, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu
2014	C	`conf`	A delay circuit with 4-terminal magnetic-random-access-memory device for power-efficient time- domain signal processing. ISCAS Ryusuke Nebashi, Noboru Sakimura, Hiroaki Honjo, Ayuka Morioka, Yukihide Tsuji, Kunihiko Ishihara, Keiichi Tokutome, Sadahiko Miura, Shunsuke Fukami, Keizo Kinoshita, Takahiro Hanyu, Tetsuo Endoh, Naoki Kasai, Hideo Ohno, Tadahiko Sugibayashi
2014	J	`jnl`	Complementary 5T-4MTJ nonvolatile TCAM cell circuit with phase-selective parallel writing scheme. IEICE Electron. Express Shoun Matsunaga, Akira Mochizuki, Noboru Sakimura, Ryusuke Nebashi, Tadahiko Sugibayashi, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu
2014	—	`conf`	Soft-Delay-Error Evaluation in Content-Addressable Memory. ISMVL Naoya Onizawa, Shoun Matsunaga, Noboru Sakimura, Ryusuke Nebashi, Tadahiko Sugibayashi, Takahiro Hanyu
2013	J	`jnl`	A Non-volatile Reconfigurable Offloader for Wireless Sensor Nodes. Inf. Media Technol. Shogo Nakaya, Makoto Miyamura, Noboru Sakimura, Yuichi Nakamura, Tadahiko Sugibayashi
2013	J	`jnl`	A Non-volatile Reconfigurable Offloader for Wireless Sensor Nodes. IPSJ Trans. Syst. LSI Des. Methodol. Shogo Nakaya, Makoto Miyamura, Noboru Sakimura, Yuichi Nakamura, Tadahiko Sugibayashi
2013	—	`conf`	Energy evaluation for two-level on-chip cache with non-volatile memory on mobile processors. ASICON Shota Matsuno, Masashi Tawada, Masao Yanagisawa, Shinji Kimura, Nozomu Togawa, Tadahiko Sugibayashi
2013	C	`conf`	MTJ/MOS-hybrid logic-circuit design flow for nonvolatile logic-in-memory LSI. ISCAS Masanori Natsui, Takahiro Hanyu, Noboru Sakimura, Tadahiko Sugibayashi
2013	—	`conf`	Nonvolatile logic-in-memory array processor in 90nm MTJ/MOS achieving 75% leakage reduction using cycle-based power gating. ISSCC Masanori Natsui, Daisuke Suzuki, Noboru Sakimura, Ryusuke Nebashi, Yukihide Tsuji, Ayuka Morioka, Tadahiko Sugibayashi, Sadahiko Miura, Hiroaki Honjo, Keizo Kinoshita, Shoji Ikeda, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu
2012	J	`jnl`	A non-volatile reconfigurable offloader for wireless sensor nodes. SIGARCH Comput. Archit. News Shogo Nakaya, Makoto Miyamura, Noboru Sakimura, Yuichi Nakamura, Tadahiko Sugibayashi
2012	C	`conf`	High-speed simulator including accurate MTJ models for spintronics integrated circuit design. ISCAS Noboru Sakimura, Ryusuke Nebashi, Yukihide Tsuji, Hiroaki Honjo, Tadahiko Sugibayashi, Hiroki Koike, Takashi Ohsawa, Shunsuke Fukami, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh
2011	—	`conf`	Programmable cell array using rewritable solid-electrolyte switch integrated in 90nm CMOS. ISSCC Makoto Miyamura, Shogo Nakaya, Munehiro Tada, Toshitsugu Sakamoto, Koichiro Okamoto, Naoki Banno, Shinji Ishida, Kimihiko Ito, Hiromitsu Hada, Noboru Sakimura, Tadahiko Sugibayashi, Masato Motomura
2009	—	`conf`	A 90nm 12ns 32Mb 2T1MTJ MRAM. ISSCC Ryusuke Nebashi, Noboru Sakimura, Hiroaki Honjo, Shinsaku Saito, Yuichi Ito, Sadahiko Miura, Yuko Kato, Kaoru Mori, Yasuaki Ozaki, Yosuke Kobayashi, Norikazu Ohshima, Keizo Kinoshita, Tetsuhiro Suzuki, Kiyokazu Nagahara, Nobuyuki Ishiwata, Katsumi Suemitsu, Shunsuke Fukami, Hiromitsu Hada, Tadahiko Sugibayashi, Naoki Kasai
2009	J	`jnl`	Nonvolatile Magnetic Flip-Flop for Standby-Power-Free SoCs. IEEE J. Solid State Circuits Noboru Sakimura, Tadahiko Sugibayashi, Ryusuke Nebashi, Naoki Kasai
2009	J	`jnl`	Shared Write-Selection Transistor Cell and Leakage-Replication Read Scheme for Large Capacity MRAM Macros. IEICE Trans. Electron. Ryusuke Nebashi, Noboru Sakimura, Tadahiko Sugibayashi, Naoki Kasai
2008	—	`conf`	Nonvolatile Magnetic Flip-Flop for standby-power-free SoCs. CICC Noboru Sakimura, Tadahiko Sugibayashi, Ryusuke Nebashi, Naoki Kasai
2007	J	`jnl`	A 16-Mb Toggle MRAM With Burst Modes. IEEE J. Solid State Circuits Tadahiko Sugibayashi, Noboru Sakimura, Takeshi Honda, Kiyokazu Nagahara, Kiyotaka Tsuji, Hideaki Numata, Sadahiko Miura, Ken-ichi Shimura, Yuko Kato, Shinsaku Saito, Yoshiyuki Fukumoto, Hiroaki Honjo, Tetsuhiro Suzuki, Katsumi Suemitsu, Tomonori Mukai, Kaoru Mori, Ryusuke Nebashi, Shunsuke Fukami, Norikazu Ohshima, Hiromitsu Hada, Nobuyuki Ishiwata, Naoki Kasai, Shuichi Tahara
2007	J	`jnl`	MRAM Applications Using Unlimited Write Endurance. IEICE Trans. Electron. Tadahiko Sugibayashi, Takeshi Honda, Noboru Sakimura, Shuichi Tahara, Naoki Kasai
2007	J	`jnl`	MRAM Cell Technology for Over 500-MHz SoC. IEEE J. Solid State Circuits Noboru Sakimura, Tadahiko Sugibayashi, Takeshi Honda, Hiroaki Honjo, Shinsaku Saito, Tetsuhiro Suzuki, Nobuyuki Ishiwata, Shuichi Tahara
2007	J	`jnl`	Writing Circuitry for Toggle MRAM to Screen Intermittent Failure Mode. IEICE Trans. Electron. Takeshi Honda, Noboru Sakimura, Tadahiko Sugibayashi, Naoki Kasai, Hiromitsu Hada, Shuichi Tahara
2006	—	`conf`	A 16Mb MRAM with FORK Wiring Scheme and Burst Modes. ISSCC Yoshihisa Iwata, Kenji Tsuchida, Tsuneo Inaba, Yui Shimizu, R. Takizawa, Yoshihiro Ueda, Tadahiko Sugibayashi, Yoshiaki Asao, Takeshi Kajiyama, Keiji Hosotani, Sumio Ikegawa, Tadashi Kai, Masahiko Nakayama, Shuichi Tahara, Hiroaki Yoda
2003	—	`conf`	Resistance ratio read (R CICC Tsuneo Inaba, Kenji Tsuchida, Tadahiko Sugibayashi, Shuichi Tahara, Hiroaki Yoda
2000	J	`jnl`	A 12-ns 8-Mbyte DRAM secondary cache for a 64-bit microprocessor. IEEE J. Solid State Circuits Takashi Okuda, Isao Naritake, Tadahiko Sugibayashi, Yuji Nakajima, Tatsunori Murotani
1999	J	`jnl`	Noncomplimentary rewriting and serial-data coding scheme for shared-sense-amplifier open-bit-line DRAM. IEEE J. Solid State Circuits Satoshi Utsugi, Masami Hanyu, Yoshinori Muramatsu, Tadahiko Sugibayashi
1995	J	`jnl`	A 1-Gb DRAM for file applications. IEEE J. Solid State Circuits Tadahiko Sugibayashi, Isao Naritake, Satoshi Utsugi, Kentaro Shibahara, Ryuichi Oikawa, Hidemitsu Mori, Shouichi Iwao, Tatsunori Murotani, Kuniaki Koyama, Shinichi Fukuzawa, Toshiro Itani, Kunihiko Kasama, Takashi Okuda, Shuichi Ohya, Masaki Ogawa
1993	J	`jnl`	A 30-ns 256-Mb DRAM with a multidivided array structure. IEEE J. Solid State Circuits Tadahiko Sugibayashi, Toshio Takeshima, Isao Naritake, Tatsuya Matano, Hiroshi Takada, Yoshiharu Aimoto, Koichiro Furuta, Mamoru Fujita, Takanori Saeki, Hiroshi Sugawara, Tatsunori Murotani, Naoki Kasai, Kentaro Shibahara, Ken Nakajima, Hiromitsu Hada, Takehiko Hamada, Naoaki Aizaki, Takemitsu Kunio, Eiichiro Kakehashi, Katsuhiro Masumori, Takaho Tanigawa