Tadaaki Yamauchi

19 papers Journal 5Unranked 13

Year	Rank	Type	Title / Venue / Authors
2019	—	`conf`	A 28nm 600MHz Automotive Flash Microcontroller with Virtualization-Assisted Processor for Next-Generation Automotive Architecture Complying with ISO26262 ASIL-D. ISSCC Sugako Otani, Norimasa Otsuki, Yasufumi Suzuki, Naoto Okumura, Shohei Maeda, Tomonori Yanagita, Takao Koike, Yasuhisa Shimazaki, Masao Ito, Minoru Uemura, Toshihiro Hattori, Tadaaki Yamauchi, Hiroyuki Kondo
2018	—	`ch.`	Overview of Embedded Flash Memory Technology. Embedded Flash Memory for Embedded Systems Takashi Kono, Tomoya Saito, Tadaaki Yamauchi
2016	—	`conf`	7.6 A 90nm embedded 1T-MONOS flash macro for automotive applications with 0.07mJ/8kB rewrite energy and endurance over 100M cycles under Tj of 175°C. ISSCC Hidenori Mitani, Ken Matsubara, Hiroshi Yoshida, Takashi Hashimoto, Hideaki Yamakoshi, Shinichiro Abe, Takashi Kono, Yasuhiko Taito, Takashi Ito, Takashi Krafuji, Kenji Noguchi, Hideto Hidaka, Tadaaki Yamauchi
2016	—	`conf`	A 20uA/MHz at 200MHz microcontroller with low power memory access scheme for small sensing nodes. COOL Chips Masami Nakajima, Ichiro Naka, Fumihiro Matsushima, Tadaaki Yamauchi
2016	J	`jnl`	A 28 nm Embedded Split-Gate MONOS (SG-MONOS) Flash Macro for Automotive Achieving 6.4 GB/s Read Throughput by 200 MHz No-Wait Read Operation and 2.0 MB/s Write Throughput at Tj of 170°C. IEEE J. Solid State Circuits Yasuhiko Taito, Takashi Kono, Masaya Nakano, Tomoya Saito, Takashi Ito, Kenji Noguchi, Hideto Hidaka, Tadaaki Yamauchi
2015	—	`conf`	7.3 A 28nm embedded SG-MONOS flash macro for automotive achieving 200MHz read operation and 2.0MB/S write throughput at Ti, of 170°C. ISSCC Yasuhiko Taito, Masaya Nakano, Hiromi Okimoto, Daisuke Okada, Takashi Ito, Takashi Kono, Kenji Noguchi, Hideto Hidaka, Tadaaki Yamauchi
2015	—	`conf`	Automotive low power technology for IoT society. VLSIC Tadaaki Yamauchi, Hiroyuki Kondo, Koji Nii
2015	—	`conf`	Prospect of embedded non-volatile memory in the smart society. VLSI-DAT Tadaaki Yamauchi
2015	—	`conf`	Technology/circuits joint evening panel discussion semiconductor industry in 2020: Evolution or revolution? VLSIC N. Sugii, G. Jurczak, Masanao Yamaoka, A. Molnar, J. Tham, T. Piliszczuk, O. Nalamasu, J. Hausner, Shu Tanaka, Tadaaki Yamauchi, S. Sivaram, C. Diaz, W. Dai
2014	J	`jnl`	40-nm Embedded Split-Gate MONOS (SG-MONOS) Flash Macros for Automotive With 160-MHz Random Access for Code and Endurance Over 10 M Cycles for Data at the Junction Temperature of 170°C. IEEE J. Solid State Circuits Takashi Kono, Takashi Ito, Tamaki Tsuruda, Takayuki Nishiyama, Tsutomu Nagasawa, Tomoya Ogawa, Yoshiyuki Kawashima, Hideto Hidaka, Tadaaki Yamauchi
2013	—	`conf`	40nm embedded SG-MONOS flash macros for automotive with 160MHz random access for code and endurance over 10M cycles for data. ISSCC Takashi Kono, Takashi Ito, Tamaki Tsuruda, Takayuki Nishiyama, Tsutomu Nagasawa, Tomoya Ogawa, Yoshiyuki Kawashima, Hideto Hidaka, Tadaaki Yamauchi
2012	—	`conf`	Robust VLSI circuit design & systems for sustainable society. ISSCC Ken Takeuchi, Jan Crols, Kevin Zhang, Mike Clinton, Tadaaki Yamauchi
2012	—	`conf`	Session 25 overview: Non-volatile memory solutions: Memory subcommittee. ISSCC Tadaaki Yamauchi, Satoru Hanzawa
2011	—	`conf`	Ultra-low voltage VLSIs for energy efficient systems. ISSCC Ken Takeuchi, Ken Chang, Kevin Zhang, Tadaaki Yamauchi, Roberto Gastaldi
2001	J	`jnl`	Design methodology of embedded DRAM with virtual-socket architecture. IEEE J. Solid State Circuits Tadaaki Yamauchi, Mitsuya Kinoshita, Teruhiko Amano, Katsumi Dosaka, Kazutami Arimoto, Hideyuki Ozaki, Michihiro Yamada, Tsutomu Yoshihara
2000	—	`conf`	Design methodology of the embedded DRAM with the virtual socket architecture. CICC Mitsuya Kinoshita, Tadaaki Yamauchi, Teruhiko Amano, Katsumi Dosaka, Kenshin Arimoto
2000	J	`jnl`	High-performance embedded SOI DRAM architecture for the low-power supply. IEEE J. Solid State Circuits Tadaaki Yamauchi, Fukashi Morishita, Shigenobu Maeda, Kazutami Arimoto, Kazuyasu Fujishima, Hideyuki Ozaki, Tsutomu Yoshihara
1997	—	`conf`	The Hierarchical Multi-Bank DRAM: A High-Performance Architecture for Memory Integrated with Processors. ARVLSI Tadaaki Yamauchi, Lance Hammond, Kunle Olukotun
1996	J	`jnl`	A low power and high speed data transfer scheme with asynchronous compressed pulse width modulation for AS-Memory. IEEE J. Solid State Circuits Tadaaki Yamauchi, Yoshikazu Morooka, Hideyuki Ozaki