Tad A. Kwasniewski

46 papers A* 1B 1C 4Misc 1Journal 7Unranked 32

Year	Rank	Type	Title / Venue / Authors
2017	—	`conf`	On-die power grid broadband model determination using a priori narrowband measurements. MWSCAS Leonard MacEachem, Xin-Jie Wang, Tad A. Kwasniewski
2012	—	`conf`	A DLL-based fractional-N frequency synthesizer with a programmable injection clock. CCECE Haizheng Guo, Tad A. Kwasniewski
2011	—	`conf`	A reduced signal feed-through 6-tap pre-emphasis circuit for use in a 10GB/S backplane communications system. SoCC Harry Tai, Peter Noel, Tad A. Kwasniewski
2010	J	`jnl`	Low Complexity Reconfigurable DSP Circuit Implementations Based on Common Sub-expression Elimination. J. Signal Process. Syst. Huong Ho, Valek Szwarc, Tad A. Kwasniewski
2010	—	`conf`	Optimized LNA for analog RF front-end circuit in brain-machine interface. WCNIS Haizheng Guo, Bo Wang, Bangli Liang, Tad A. Kwasniewski, Robert Sobot
2009	—	`conf`	A 10-Gb/s backplane transmitter with a FIR pre-emphasis equalizer to suppress ISI at data centers and edges simultaneously. CCECE Dianyong Chen, Bo Wang, Bangli Liang, Tad A. Kwasniewski
2009	J	`jnl`	A Low-Power, Fast Acquisition, Data Recovery Circuit With Digital Threshold Decision for SFI-5 Application. IEEE Trans. Very Large Scale Integr. Syst. Qingjin Du, Jingcheng Zhuang, Tad A. Kwasniewski
2009	J	`jnl`	A Reconfigurable Systolic Array Architecture for Multicarrier Wireless and Multirate Applications. Int. J. Reconfigurable Comput. Huong Ho, Valek Szwarc, Tad A. Kwasniewski
2009	—	`conf`	A full-rate truly monolithic CMOS CDR for low-cost applications. CCECE Bangli Liang, Zhigong Wang, Dianyong Chen, Bo Wang, Guohui Situ, Tad A. Kwasniewski
2009	—	`conf`	A monolithic high modulation efficiency CMOS laser diode / modulator driver. ICT Bangli Liang, Dianyong Chen, Bo Wang, Guohui Situ, Tad A. Kwasniewski, Zhigong Wang
2009	—	`conf`	A programmable pre-cursor ISI equalization circuit for high-speed serial link over highly lossy backplane channel. CCECE Bo Wang, Dianyong Chen, Bangli Liang, Jinguang Jiang, Tad A. Kwasniewski
2008	C	`conf`	A 0.18-µm CMOS clock and data recovery circuit with reference-less dual loops. ISCAS Miao Li, Tad A. Kwasniewski, Shoujun Wang
2008	—	`conf`	A 42-Gb/s Decision Circuit in 0.13µm CMOS. CNSR Bangli Liang, Tad A. Kwasniewski, Dianyong Chen
2008	—	`conf`	A multi-mode sphere detector architecture for WLAN applications. SoCC Ramin Shariat-Yazdi, Tad A. Kwasniewski
2008	—	`conf`	Low complexity sphere decoding algorithms. ISWCS Ramin Shariat-Yazdi, Tad A. Kwasniewski
2007	C	`conf`	A 40 GHz Quadrature LC VCO and Frequency Divider in 90-nm CMOS Technology. ISCAS Muhammad Usama, Tad A. Kwasniewski
2007	—	`conf`	A 4GHz Low Complexity ADPLL-based Frequency Synthesizer in 90nm CMOS. CICC Jingcheng Zhuang, Qingjin Du, Tad A. Kwasniewski
2006	—	`conf`	A 0.18µm CMOS Receiver with Decision-feedback Equalization for Backplane Applications. APCCAS Miao Li, Tad A. Kwasniewski, Shoujun Wang
2006	C	`conf`	A 0.18µm CMOS clock and data recovery circuit with extended operation range. ISCAS Miao Li, Wenjie Huang, Tad A. Kwasniewski, Shoujun Wang
2006	—	`conf`	A Low Phase Noise Dll Clock Generator with a Programmable Dynamic Frequency Divider. CCECE Qingjin Du, Jingcheng Zhuang, Tad A. Kwasniewski
2006	J	`jnl`	A Low-Phase Noise, Anti-Harmonic Programmable DLL Frequency Multiplier With Period Error Compensation for Spur Reduction. IEEE Trans. Circuits Syst. II Express Briefs Qingjin Du, Jingcheng Zhuang, Tad A. Kwasniewski
2006	—	`conf`	A Timing Jitter Reduction Technique in a Cyclic Injection Clock Multiplier for Data Communication System. SoCC Qingjin Du, Jingcheng Zhuang, Tad A. Kwasniewski
2006	—	`conf`	An Anti-Harmonic Locking, DLL Frequency Multiplier with Low Phase Noise and Reduced Spur. CICC Qingjin Du, Jingcheng Zhuang, Tad A. Kwasniewski
2006	C	`conf`	An eye detection technique for clock and data recovery applications. ISCAS Jingcheng Zhuang, Qingjin Du, Tad A. Kwasniewski
2006	A*	`conf`	PELE: pre-emphasis & equalization link estimator to address the effects of signal integrity limitations. DAC William Bereza, Yuming Tao, Shoujun Wang, Tad A. Kwasniewski, Rakesh H. Patel
2005	—	`conf`	A 0.18µm CMOS transceiver design for high-speed backplane data communications. ISCAS (2) Miao Li, Wenjie Huang, Tad A. Kwasniewski, Shoujun Wang
2005	—	`conf`	A 10Gb/s transmitter with multi-tap FIR pre-emphasis in 0.18µm CMOS technology. ASP-DAC Miao Li, Tad A. Kwasniewski, Shoujun Wang, Yuming Tao
2005	—	`conf`	A 4-GB/S half-rate clock and data recovery circuit with a 3-stage VCO. Circuits, Signals, and Systems Jingcheng Zhuang, Qingjin Du, Tad A. Kwasniewski
2005	—	`conf`	A Review of Common Receive-End Adaptive Equalization Schemes and Algorithms for a High-Speed Serial Backplane. IWSOC Charles E. Berndt, Tad A. Kwasniewski
2005	—	`conf`	A signal integrity-based link performance simulation platform. CICC Yuming Tao, William Bereza, Rakesh H. Patel, Sergey Y. Shumarayev, Tad A. Kwasniewski
2005	—	`conf`	An all-digital data recovery circuit optimization using Matlab/Simulink. ISCAS (5) S. I. Ahmed, Tad A. Kwasniewski
2005	—	`conf`	Decision Feedback Equalization with Quarter-Rate Clock Timing for High-Speed Backplane Data Communications. IWSOC Miao Li, Peter Noel, Tad A. Kwasniewski, Shoujun Wang
2005	—	`conf`	Decision feedback equalization for high-speed backplane data communications. ISCAS (2) Jing Chen, Miao Li, Tad A. Kwasniewski
2005	—	`conf`	PLL-Based Fractional-N Frequency Synthesizers. IWSOC Farhad Zarkeshvari, Peter Noel, Tad A. Kwasniewski
2005	—	`conf`	Turbo Codes - Digital IC Design. IWSOC Moeed Israr, Tad A. Kwasniewski
2004	—	`conf`	2.4 GHz RF down-conversion mixers in standard CMOS technology. ISCAS (4) Arif A. Siddiqi, Tad A. Kwasniewski
2004	—	`conf`	Design and comparison of CMOS Current Mode Logic latches. ISCAS (4) Muhammad Usama, Tad A. Kwasniewski
2003	—	`conf`	A -107dBe, 10kHz carrier offset 2-GHz DLL-based frequency synthesizer. CICC Jingcheng Zhuang, Qingjin Du, Tad A. Kwasniewski
1999	—	`conf`	A 1.25 GHz 0.35 μm monolithic CMOS PLL clock generator for data communications. CICC Lizhong Sun, Tad A. Kwasniewski
1999	—	`conf`	A quadrature output voltage controlled ring oscillator based on three-stage sub-feedback loops. ISCAS (2) Lizhong Sun, Tad A. Kwasniewski, Kris Iniewski
1999	—	`conf`	Reduced complexity, high performance digital delta-sigma modulator for fractional-N frequency synthesis. ISCAS (2) Lizhong Sun, Thierry Lepley, Franck Nozahic, Amaud Bellissant, Tad A. Kwasniewski, Bany Heim
1996	Misc	`conf`	Is High Frequency Analog DFT Possible? VTS Bozena Kaminska, Tad A. Kwasniewski, Linda S. Milor, G. Roberts, P. Flahive, Jérôme Wojcik
1994	J	`jnl`	A chip set for pipeline and parallel pipeline FFT architectures. J. VLSI Signal Process. Valek Szwarc, Luc Desormeaux, Wilson Wong, Clifford P. S. Yeung, Chong H. Chan, Tad A. Kwasniewski
1994	B	`conf`	A low power, single chip realization of a low-speed, low-delay CELP coder/decoder for indoor wireless systems. VTC D. P. Noel, Tad A. Kwasniewski, Samy A. Mahmoud, Wilf P. LeBlanc
1993	J	`jnl`	Delta-sigma modulation in fractional-N frequency synthesis. IEEE J. Solid State Circuits Tom A. D. Riley, Miles A. Copeland, Tad A. Kwasniewski
1991	J	`jnl`	Baseband Trellis-Coded Modulation with Combined Equalization/Decoding for High Bit Rate Digital Subscriber Loops. IEEE J. Sel. Areas Commun. P. Mohanraj, David D. Falconer, Tad A. Kwasniewski