T. Sansaloni

13 papers B 1Journal 6Unranked 6
YearRankTypeTitle / Venue / Authors
2009 J jnl
Design and FPGA-Implementation of a High Performance Timing Recovery Loop for Broadband Communications.
J. Signal Process. Syst.
Vicente Torres-Carot, A. Perez-Pascual, T. Sansaloni, Javier Valls
2009 J jnl
Design of Power and Area Efficient Digital Down-converters for Broadband Communications Systems.
J. Signal Process. Syst.
A. Perez-Pascual, T. Sansaloni, Vicente Torres-Carot, Vicenc Almenar-Terre, Javier Valls
2008 J jnl
Architectures for the Implementation of a OFDM-WLAN Viterbi Decoder.
J. Signal Process. Syst.
Fabian Angarita, Ma José Canet, T. Sansaloni, Javier Valls, Vicenc Almenar-Terre
2008 J jnl
Efficient Mapping of CORDIC Algorithm for OFDM-Based WLAN.
J. Signal Process. Syst.
Fabian Angarita, Ma José Canet, T. Sansaloni, A. Perez-Pascual, Javier Valls
2007 — conf
Design of an efficient digital down-converter for a SDR-based DVB-S receiver.
ECCTD
A. Perez-Pascual, T. Sansaloni, Vicente Torres, Vicenç Almenar, Javier Valls
2007 J jnl
Scheme for Reducing the Storage Requirements of FFT Twiddle Factors on FPGAs.
J. VLSI Signal Process.
T. Sansaloni, A. Perez-Pascual, Vicente Torres-Carot, Javier Valls
2006 — conf
Design of high performance timing recovery loops for communication applications.
SiPS
Vicente Torres-Carot, A. Perez-Pascual, T. Sansaloni, Javier Valls
2005 B conf
Efficient FPGA Implementation of CORDIC Algorithm for Circular and Linear Coordinates.
FPL
Fabian Angarita, A. Perez-Pascual, T. Sansaloni, Javier Valls
2003 J jnl
Digit-Serial Complex-Number Multipliers on FPGAs.
J. VLSI Signal Process.
T. Sansaloni, Javier Valls, Keshab K. Parhi
2002 — conf
FPGA-based radix-4 butterflies for HIPERLAN/2.
ISCAS (3)
A. Perez-Pascual, T. Sansaloni, Javier Valls
2001 — conf
Distributed arithmetic radix-2 butterflies for FPGA.
ICECS
T. Sansaloni, A. Perez-Pascual, Javier Valls
2001 — conf
FPGA based on-line complex-number multipliers.
ICECS
A. Perez-Pascual, T. Sansaloni, Javier Valls
1999 — conf
A comparison between lattice, cascade and direct form FIR filter structures by using a FPGA bit-serial distributed arithmetic implementation.
ICECS
Marcos Martínez-Peiró, Javier Valls, T. Sansaloni, A. Perez-Pascual, Eduardo I. Boemo