T. R. Viswanathan

20 papers C 1Journal 11Unranked 8
YearRankTypeTitle / Venue / Authors
2023 J jnl
A Single-Step Subranging Relaxation Oscillator-Based Open-Loop Sigma-Delta ADC.
IEEE Trans. Circuits Syst. I Regul. Pap.
Sudhanva Vasishta, K. R. Raghunandan, Ananth Dodabalapur, T. R. Viswanathan
2020 — conf
Level-Crossing Detection based Low-Power Sigma-Delta ADC for Sensor Applications.
MWSCAS
Sudhanva Vasishta, K. R. Raghunandan, Ananth Dodabalapur, T. R. Viswanathan
2014 — conf
A 1.1mW, 63.7dB-SNDR, 10MHz-BW hybrid voltage -time domain ADC.
MWSCAS
Amit Kumar Gupta, Krishnaswamy Nagaraj, T. R. Viswanathan
2014 — conf
A hybrid SAR-VCO ΔΣ ADC with first-order noise shaping.
CICC
Arindam Sanyal, Kareem Ragab, Long Chen, T. R. Viswanathan, Shouli Yan, Nan Sun
2014 — conf
Analog signal processing in deep submicron CMOS technologies using inverters.
MWSCAS
K. R. Raghunandan, Nan Sun, T. R. Viswanathan
2013 J jnl
Harmonic Rejection Mixing Techniques Using Clock-Gating.
IEEE J. Solid State Circuits
Aslam A. Rafi, T. R. Viswanathan
2013 — conf
Operational current to frequency converter.
MWSCAS
Rohit Yadav, K. R. Raghunandan, Ananth Dodabalapur, T. Lakshmi Viswanathan, T. R. Viswanathan
2012 — conf
An uncalibrated 2MHz, 6mW, 63.5dB SNDR discrete-time input VCO-based ΔΣ ADC.
CICC
Joseph Hamilton, Shouli Yan, T. R. Viswanathan
2012 — conf
Clock-gated harmonic rejection mixers.
CICC
Aslam A. Rafi, T. R. Viswanathan
2011 J jnl
A Two-Stage ADC Architecture With VCO-Based Second Stage.
IEEE Trans. Circuits Syst. II Express Briefs
Amit Kumar Gupta, Krishnaswamy Nagaraj, T. R. Viswanathan
2010 J jnl
A Discrete-Time Input Delta Sigma ADC Architecture Using a Dual-VCO-Based Integrator.
IEEE Trans. Circuits Syst. II Express Briefs
Joseph Hamilton, Shouli Yan, T. R. Viswanathan
2009 J jnl
Self-Biased Unity-Gain Buffers With Low Gain Error.
IEEE Trans. Circuits Syst. II Express Briefs
Guangmao Xing, Stephen H. Lewis, T. R. Viswanathan
2007 J jnl
A 1.4 V Supply CMOS Fractional Bandgap Reference.
IEEE J. Solid State Circuits
Raymond T. Perry, Stephen H. Lewis, A. Paul Brokaw, T. R. Viswanathan
2006 — conf
A Unity-Gain Buffer with Reduced Offset and Gain Error.
CICC
Guangmao Xing, Stephen H. Lewis, T. R. Viswanathan
2002 J jnl
A CMOS bandgap reference without resistors.
IEEE J. Solid State Circuits
Arne E. Buck, Charles L. McDonald, Stephen H. Lewis, T. R. Viswanathan
2000 J jnl
A dual-mode 700-Msamples/s 6-bit 200-Msamples/s 7-bit A/D converter in a 0.25-μm digital CMOS process.
IEEE J. Solid State Circuits
Krishnaswamy Nagaraj, David A. Martin, Mark A. Wolfe, Ranjan Chattopadhyay, Shanthi Pavan, Jason Cancio, T. R. Viswanathan
1999 J jnl
Efficient 6-bit A/D converter using a 1-bit folding front end.
IEEE J. Solid State Circuits
K. Nagaraj, F. Chen, T. R. Viswanathan
1993 C conf
A Non-uniform Sampling Technique for A/D Conversion.
ISCAS
N. Sayiner, Henrik V. Sorensen, T. R. Viswanathan
1992 J jnl
A 10-b 20-Msample/s analog-to-digital converter.
IEEE J. Solid State Circuits
Stephen H. Lewis, H. Scott Fetterman, George F. Gross, Ravi Ramachandran, T. R. Viswanathan
1989 J jnl
A dual-channel voice-band PCM codec using Sigma Delta modulation technique.
IEEE J. Solid State Circuits
Vladimir Friedman, Douglas M. Brinthaupt, De-Ping Chen, Timothy W. Deppa, John P. Elward Jr., Evelyn M. Fields, Jeffrey W. Scott, T. R. Viswanathan