T. M. Mak - RankMe

64 papers A* 2A 16C 10Misc 6Journal 17Unranked 13

Year	Rank	Type	Title / Venue / Authors
2020	J	`jnl`	High-speed I/O capabilities added to military automatic test equipment (ATE) using synthetic instruments. IEEE Instrum. Meas. Mag. Louis Y. Ungar, Neil G. Jacobson, T. M. Mak
2017	J	`jnl`	A Comprehensive BIST Solution for Polar Transceivers Using On-Chip Resources. ACM Trans. Design Autom. Electr. Syst. Jae Woong Jeong, Vishwanath Natarajan, Shreyas Sen, T. M. Mak, Jennifer Kitchen, Sule Ozev
2015	J	`jnl`	Low-Cost On-Chip Clock Jitter Measurement Scheme. IEEE Trans. Very Large Scale Integr. Syst. Martin Omaña, Daniele Rossi, Daniele Giaffreda, Cecilia Metra, T. M. Mak, Asifur Rahman, Simon Tam
2014	J	`jnl`	Clock Faults Induced Min and Max Delay Violations. J. Electron. Test. Daniele Rossi, Martin Omaña, José Manuel Cazeaux, Cecilia Metra, T. M. Mak
2014	Misc	`conf`	Innovative practices session 3C: Solving today's test challenges. VTS John Kim, Wolfgang Meyer, T. M. Mak, Amitava Majumdar
2014	A	`conf`	Interposer test: Testing PCBs that have shrunk 100x. ITC T. M. Mak
2013	Misc	`conf`	Measurement of envelope/phase path delay skew and envelope path bandwidth in polar transmitters. VTS Jae Woong Jeong, Sule Ozev, Shreyas Sen, T. M. Mak
2012	J	`jnl`	Integrated Test-Architecture Optimization and Thermal-Aware Test Scheduling for 3-D SoCs Under Pre-Bond Test-Pin-Count Constraint. IEEE Trans. Very Large Scale Integr. Syst. Li Jiang, Qiang Xu, Krishnendu Chakrabarty, T. M. Mak
2012	J	`jnl`	New Design for Testability Approach for Clock Fault Testing. IEEE Trans. Computers Cecilia Metra, Martin Omaña, T. M. Mak, Simon Tam
2011	J	`jnl`	Low-Cost Dynamic Compensation Scheme for Local Clocks of Next Generation High Performance Microprocessors. IEEE Trans. Very Large Scale Integr. Syst. Martin Omaña, Cecilia Metra, T. M. Mak, Simon Tam
2010	—	`conf`	On-die Ring Oscillator Based Measurement Scheme for Process Parameter Variations and Clock Jitter. DFT Martin Omaña, Daniele Giaffreda, Cecilia Metra, T. M. Mak, Simon Tam, Asifur Rahman
2009	A	`conf`	An industrial case study for X-canceling MISR. ITC Joon-Sung Yang, Nur A. Touba, Shih-Yu Yang, T. M. Mak
2009	A	`conf`	Layout-driven test-architecture design and optimization for 3D SoCs under pre-bond test-pin-count constraint. ICCAD Li Jiang, Qiang Xu, Krishnendu Chakrabarty, T. M. Mak
2008	A	`conf`	Jitters in high performance microprocessors. ITC T. M. Mak
2008	—	`conf`	Novel On-Chip Clock Jitter Measurement Scheme for High Performance Microprocessors. DFT Cecilia Metra, Martin Omaña, T. M. Mak, Asifur Rahman, Simon Tam
2007	—	`conf`	Data Recovery Block Design for Impulse Modulated Power Line Communications in a Microprocessor. ISVLSI Rajesh Thirugnanam, Dong Sam Ha, T. M. Mak
2007	C	`conf`	Design for Resilience to Soft Errors and Variations. IOLTS Ming Zhang, T. M. Mak, James W. Tschanz, Kee Sup Kim, Norbert Seifert, Davia Lu
2007	C	`conf`	Infant Mortality--The Lesser Known Reliability Issue. IOLTS T. M. Mak
2007	—	`conf`	Invited Talk 1: Testing of Power Constraint Computing. ATS T. M. Mak
2007	Misc	`conf`	Novel Approach to Clock Fault Testing for High Performance Microprocessors. VTS Cecilia Metra, Martin Omaña, T. M. Mak, Simon Tam
2007	A	`conf`	Novel compensation scheme for local clocks of high performance microprocessors. ITC Cecilia Metra, Martin Omaña, T. M. Mak, Simon Tam
2007	J	`jnl`	The case for power with test. IEEE Des. Test Comput. T. M. Mak
2007	J	`jnl`	Won't On-Chip Clock Calibration Guarantee Performance Boost and Product Quality?. IEEE Trans. Computers Cecilia Metra, Daniele Rossi, T. M. Mak
2006	C	`conf`	Can Clock Faults be Detected Through Functional Test? DDECS Cecilia Metra, Daniele Rossi, Martin Omaña, José Manuel Cazeaux, T. M. Mak
2006	J	`jnl`	Guest Editors' Introduction: Process Variation and Stochastic Design and Test. IEEE Des. Test Comput. T. M. Mak, Sani R. Nassif
2006	J	`jnl`	Is System in Package the Panacea for Integration? IEEE Des. Test Comput. T. M. Mak
2006	C	`conf`	Path (Min) Delay Faults and Their Impact on Self-Checking Circuits' Operation. IOLTS Cecilia Metra, Martin Omaña, Daniele Rossi, José Manuel Cazeaux, T. M. Mak
2006	J	`jnl`	Sequential Element Design With Built-In Soft Error Resilience. IEEE Trans. Very Large Scale Integr. Syst. Ming Zhang, Subhasish Mitra, T. M. Mak, Norbert Seifert, Nicholas J. Wang, Quan Shi, Kee Sup Kim, Naresh R. Shanbhag, Sanjay J. Patel
2006	C	`conf`	Should Logic SER be Solved at the Circuit Level? IOLTS T. M. Mak, Subhasish Mitra
2006	—	`conf`	Simulating the Effects of Process Variations on Capacitive Crosstalk. ICECS Arani Sinha, Shahin Nazarian, T. M. Mak
2006	C	`conf`	Soft Error Resilient System Design through Error Correction. VLSI-SoC Subhasish Mitra, Ming Zhang, Norbert Seifert, T. M. Mak, Kee Sup Kim
2006	—	`conf`	Soft Error Resilient System Design through Error Correction. VLSI-SoC (Selected Papers) Subhasish Mitra, Ming Zhang, Norbert Seifert, T. M. Mak, Kee Sup Kim
2006	Misc	`conf`	Statistical Estimation of Correlated Leakage Power Variation and Its Application to Leakage-Aware Design. VLSI Design Maryam Ashouei, Abhijit Chatterjee, Adit D. Singh, Vivek De, T. M. Mak
2006	C	`conf`	Test Challenges for 3D Circuits. IOLTS T. M. Mak
2006	J	`jnl`	Test Consideration for Nanometer-Scale CMOS Circuits. IEEE Des. Test Comput. Kaushik Roy, T. M. Mak, Kwang-Ting (Tim) Cheng
2005	C	`conf`	DFT Assisted Built-In Soft Error Resilience. IOLTS T. M. Mak, Subhasish Mitra, Ming Zhang
2005	C	`conf`	Does It Mean Less Testing for Self Calibrating Design?. IOLTS T. M. Mak
2005	—	`conf`	Limitation of structural scan delay test. Asian Test Symposium T. M. Mak
2005	A	`conf`	Logic soft errors: a major barrier to robust platform design. ITC Subhasish Mitra, Ming Zhang, T. M. Mak, Norbert Seifert, Victor Zia, Kee Sup Kim
2005	Misc	`conf`	On Silicon-Based Speed Path Identification. VTS Leonard Lee, Li-C. Wang, Praveen Parvathala, T. M. Mak
2005	—	`conf`	The Other Side of the Timing Equation: a Result of Clock Faults. DFT Cecilia Metra, Martin Omaña, Daniele Rossi, José Manuel Cazeaux, T. M. Mak
2004	A	`conf`	A path-based methodology for post-silicon timing validation. ICCAD Leonard Lee, Li-C. Wang, T. M. Mak, Kwang-Ting Cheng
2004	A	`conf`	Are Our Design for Testability Features Fault Secure? DATE Cecilia Metra, T. M. Mak, Martin Omaña
2004	J	`jnl`	Defect and Error Tolerance in the Presence of Massive Numbers of Defects. IEEE Des. Test Comput. Melvin A. Breuer, Sandeep K. Gupta, T. M. Mak
2004	—	`conf`	Design considerations and DFT to enable testing of digital interfaces. CICC Mike Tripp, T. M. Mak, Anne Meixner
2004	—	`conf`	Do We Need Anything More Than Single Bit Error Correction (ECC)? MTDT Michael Spica, T. M. Mak
2004	A	`conf`	Elimination of Traditional Functional Testing of Interface Timings at Intel. ITC Mike Tripp, T. M. Mak, Anne Meixner
2004	—	`conf`	Fault secureness need for next generation high performance microprocessor design for testability structures. Conf. Computing Frontiers Cecilia Metra, T. M. Mak, Martin Omaña
2004	J	`jnl`	Implications of Clock Distribution Faults and Issues with Screening Them during Manufacturing Testing. IEEE Trans. Computers Cecilia Metra, Stefano Di Francescantonio, T. M. Mak
2004	J	`jnl`	New Challenges in Delay Testing of Nanometer, Multigigahertz Designs. IEEE Des. Test Comput. T. M. Mak, Angela Krstic, Kwang-Ting (Tim) Cheng, Li-C. Wang
2004	A*	`conf`	On path-based learning and its applications in delay test and diagnosis. DAC Li-C. Wang, T. M. Mak, Kwang-Ting Cheng, Magdy S. Abadir
2004	A	`conf`	Risks Associated with Faults within Test Pattern Compactors and Their Implications on Testing. ITC Cecilia Metra, T. M. Mak, Martin Omaña
2004	J	`jnl`	Testing Gbps Interfaces without a Gigahertz Tester. IEEE Des. Test Comput. T. M. Mak, Mike Tripp, Anne Meixner
2004	C	`conf`	Testing of Hard Faults in Simultaneous Multithreaded Processors. IOLTS Eric F. Weglarz, Kewal K. Saluja, T. M. Mak
2004	A	`conf`	Trends in manufacturing test methods and their implications. ITC Sandip Kundu, T. M. Mak, Rajesh Galivanche
2003	—	`conf`	Clock Calibration Faults and their Impact on Quality of High Performance Microprocessors. DFT Cecilia Metra, T. M. Mak, Daniele Rossi
2003	A	`conf`	Diagnosis-Based Post-Silicon Timing Validation Using Statistical Tools and Methodologies. ITC Angela Krstic, Li-C. Wang, Kwang-Ting Cheng, T. M. Mak
2003	A	`conf`	Elimination of Traditional Functional Testing of Interface Timings at Intel. ITC Mike Tripp, T. M. Mak, Anne Meixner
2003	Misc	`conf`	Embedded Tutorial: Test Consideration for Nanometer Scale CMOS Circuits. VTS Kaushik Roy, T. M. Mak, Kwang-Ting Cheng
2003	A*	`conf`	Enhancing diagnosis resolution for delay defects based upon statistical timing and statistical fault models. DAC Angela Krstic, Li-C. Wang, Kwang-Ting Cheng, Jing-Jia Liou, T. M. Mak
2002	A	`conf`	Clock Faults? Impact on Manufacturing Testing and Their Possible Detection Through On-Line Testing. ITC Cecilia Metra, Stefano Di Francescantonio, T. M. Mak
2001	A	`conf`	Crosstalk test generation on pseudo industrial circuits: a case study. ITC Liang-Chi Chen, T. M. Mak, Sandeep K. Gupta, Melvin A. Breuer
2001	—	`conf`	Evaluation of Clock Distribution Networks' Most Likely Faults and Produced Effects. DFT Cecilia Metra, Stefano Di Francescantonio, Bruno Riccò, T. M. Mak
1998	A	`conf`	Cache RAM inductive fault analysis with fab defect modeling. ITC T. M. Mak, Debika Bhattacharya, Cheryl Prunty, Bob Roeder, Nermine Ramadan, F. Joel Ferguson, Jianlin Yu