Sylvain Engels

26 papers A 1C 3Journal 6Unranked 16

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	Analysis of Representative Critical Path as Delay Line for Bundled-Data Circuits. SBCCI Jéssica Gonsalves Santos, Ismael de Almeida Junior, Sylvain Engels, Robin Wilson, Laurent Fesquet
2024	—	`conf`	Data-driven Processing Element for Sparse Convolutional Neural Networks. NewCAS Xavier Lesage, Cristiano Merio, Fernando Welzel, Luca Sauer de Araujo, Sylvain Engels, Laurent Fesquet
2023	C	`conf`	Method for Data-Driven Pruning in Micropipeline Circuits. VLSI-SoC Cristiano Merio, Xavier Lesage, Ali Naimi, Sylvain Engels, Katell Morin-Allory, Laurent Fesquet
2022	—	`conf`	A Novel Event-Based Method for ASK Demodulation. LASCAS Alexis Rodrigo Iga Jadue, Sylvain Engels, Laurent Fesquet
2021	—	`conf`	Comparison between an ASK Event-Based Demodulation and a Digital IQ Demodulation. EBCCSP Alexis Rodrigo Iga Jadue, Sylvain Engels, Laurent Fesquet
2019	C	`conf`	A Digital Event-Based Strategy for ASK demodulation. VLSI-SoC Alexis Rodrigo Iga Jadue, Sylvain Engels, Laurent Fesquet
2019	C	`conf`	A Distributed Body-Biasing Strategy for Asynchronous Circuits. VLSI-SoC Laurent Fesquet, Yoan Decoudu, Alexis Rodrigo Iga Jadue, Thiago Ferreira de Paiva Leite, Otto Aureliano Rolloff, M. Diallo, Rodrigo Possamai Bastos, Katell Morin-Allory, Sylvain Engels
2019	—	`conf`	An Event-Based Strategy for ASK demodulation. EBCCSP Alexis Rodrigo Iga Jadue, Sylvain Engels, Laurent Fesquet
2018	J	`jnl`	A 6-Wire Plug and Play Clockless Distributed On-Chip-Sensor Network in 28 nm UTBB FD-SOI. J. Low Power Electron. Marc Renaudin, Aymane Bouzafour, Sylvain Engels, Robin Wilson
2018	—	`conf`	A Design Flow for Shaping Electromagnetic Emissions in Micropipeline Circuits. ASYNC Sophie Germain, Sylvain Engels, Laurent Fesquet
2017	—	`conf`	Event-based design strategy for circuit electromagnetic compatibility. EBCCSP Sophie Germain, Sylvain Engels, Laurent Fesquet
2014	J	`jnl`	A Fine-Grain Variation-Aware Dynamic Vdd-Hopping AVFS Architecture on a 32 nm GALS MPSoC. IEEE J. Solid State Circuits Ivan Miro Panades, Edith Beigné, Yvain Thonnart, Laurent Alacoque, Pascal Vivet, Suzanne Lesecq, Diego Puschini, Anca Molnos, Farhat Thabet, Benoît Tain, Karim Ben Chehida, Sylvain Engels, Robin Wilson, Didier Fuin
2014	—	`conf`	Clockless Design Performance Monitoring for Nanometer Technologies. ASYNC Marc Renaudin, Aurélien Buhrig, Charles Guillemet, Robin Wilson, Sylvain Engels
2013	—	`conf`	A fine grain variation-aware dynamic Vdd-hopping AVFS architecture on a 32nm GALS MPSoC. ESSCIRC Edith Beigné, Ivan Miro-Panades, Yvain Thonnart, Laurent Alacoque, Pascal Vivet, Suzanne Lesecq, Diego Puschini, Farhat Thabet, Benoît Tain, K. Benchehida, Sylvain Engels, Robin Wilson, Didier Fuin
2013	—	`conf`	Ultra-wide body-bias range LDPC decoder in 28nm UTBB FDSOI technology. ISSCC Philippe Flatresse, Bastien Giraud, Jean-Philippe Noel, Bertrand Pelloux-Prayer, Fabien Giner, Deepak-Kumar Arora, Franck Arnaud, Nicolas Planes, Julien Le Coz, Olivier Thomas, Sylvain Engels, Giorgio Cesana, Robin Wilson, Pascal Urard
2013	A	`conf`	Ultra-wide voltage range designs in fully-depleted silicon-on-insulator FETs. DATE Edith Beigné, Alexandre Valentian, Bastien Giraud, Olivier Thomas, Thomas Benoist, Yvain Thonnart, Serge Bernard, Guillaume Moritz, Olivier Billoint, Y. Maneglia, Philippe Flatresse, Jean-Philippe Noel, Fady Abouzeid, Bertrand Pelloux-Prayer, Anuj Grover, Sylvain Clerc, Philippe Roche, Julien Le Coz, Sylvain Engels, Robin Wilson
2011	—	`conf`	Bottom-up digital system-level reliability modeling. CICC N. Ruiz Amador, Vincent Huard, E. Pion, Florian Cacho, Damien Croain, V. Robert, Sylvain Engels, Philippe Flatresse, Lorena Anghel
2011	—	`conf`	Comparison of 65nm LP bulk and LP PD-SOI with adaptive power gate body bias for an LDPC codec. ISSCC Julien Le Coz, Philippe Flatresse, Sylvain Engels, Alexandre Valentian, Marc Belleville, Christine Raynaud, Damien Croain, Pascal Urard
2010	J	`jnl`	On-Chip Process Variability Monitoring Flow. J. Low Power Electron. Nabila Moubdi, Philippe Maurine, Robin Wilson, Sylvain Engels, Nadine Azémard, Vincent Dumettier, Pierre Busson
2009	—	`conf`	Product On-Chip Process Compensation for Low Power and Yield Enhancement. PATMOS Nabila Moubdi, Philippe Maurine, Robin Wilson, Nadine Azémard, Vincent Dumettier, Abhishek Bansal, Sebastien Barasinski, Alain Tournier, Guy Durieu, David Meyer, Pierre Busson, Sarah Verhaeren, Sylvain Engels
2009	J	`jnl`	Timing margin evaluation with a simple statistical timing analysis flow. J. Embed. Comput. Vincent Migairou, Robin Wilson, Sylvain Engels, Zeqin Wu, Nadine Azémard, Philippe Maurine
2007	—	`conf`	A Simple Statistical Timing Analysis Flow and Its Application to Timing Margin Evaluation. PATMOS Vincent Migairou, Robin Wilson, Sylvain Engels, Zeqin Wu, Nadine Azémard, Philippe Maurine
2006	J	`jnl`	A comprehensive performance macro-modeling of on-chip RC interconnects considering line shielding effects. Integr. Sylvain Engels, Robin Wilson, Nadine Azémard, Philippe Maurine
2006	J	`jnl`	Logical effort model extension to propagation delay representation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. B. Lasbouygues, Sylvain Engels, Robin Wilson, Philippe Maurine, Nadine Azémard, Daniel Auvergne
2006	—	`conf`	Statistical Characterization of Library Timing Performance. PATMOS Vincent Migairou, Robin Wilson, Sylvain Engels, Nadine Azémard, Philippe Maurine
2003	—	`conf`	Continuous representation of the performance of a CMOS library. ESSCIRC B. Lasbouygues, Joel Schindler, Sylvain Engels, Philippe Maurine, Nadine Azémard, Daniel Auvergne