Sylvain Clerc - RankMe

33 papers A 3C 1Journal 6Unranked 23

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	A Sub-400-nW Real-Time Event-Driven Spectrogram Extraction Unit in 28-nm FD-SOI CMOS for Keyword Spotting Application. IEEE J. Solid State Circuits Soufiane Mourrane, Benoit Larras, Sylvain Clerc, Andreia Cathelin, Antoine Frappé
2024	—	`conf`	Exploration of Low-Energy Floating-Point Flash Attention Mechanism for 18nm FD-SOI CMOS Integration at the Edge. MWSCAS Joaquin Cornejo, Filipe Pouget, Sylvain Clerc, Tifenn Hirtzlin, Benoit Larras, Andreia Cathelin, Antoine Frappé
2023	—	`conf`	A 291nW Real-Time Event-Driven Spectrogram Extraction unit in 28nm FD-SOI CMOS for Keyword Spotting Application. ESSCIRC Soufiane Mourrane, Benoit Larras, Sylvain Clerc, Andreia Cathelin, Antoine Frappé
2023	—	`conf`	Low-Power Event-Driven Spectrogram Extractor for Multiple Keyword Spotting: A proof of concept. NEWCAS Soufiane Mourrane, Benoit Larras, Sylvain Clerc, Andreia Cathelin, Antoine Frappé
2021	—	`conf`	Circuit Monitoring Across Design Life-Cycle in 28nm FD-SOI and 40nm Bulk CMOS technologies. ESSCIRC Sylvain Clerc, Kedar Janardan Dhori, Robin M. Wilson, Rohit Goel, Sébastien Marchal, Franck Pourchon, Christian Dutto, Ricardo Gomez Gomez
2020	—	`conf`	A 3.0μW@5fps QQVGA Self-Controlled Wake-Up Imager with On-Chip Motion Detection, Auto-Exposure and Object Recognition. VLSI Circuits Arnaud Verdant, William Guicquero, Nicolas Royer, Guillaume Moritz, Sébastien Martin, Florent Lepin, Sylvain Choisnet, Fabrice Guellec, Benoît Deschamps, Sylvain Clerc, Jérôme Chossat
2020	—	`conf`	A Performance-Flexible Energy-Optimized Automotive-Grade Cortex-R4F SoC through Combined AVS/ABB/Bias-in-Memory-Array Closed-Loop Regulation in 28nm FD-SOI. VLSI Circuits Ricardo Gomez Gomez, Edwige Bano, Andreia Cathelin, Sylvain Clerc
2020	J	`jnl`	Guest Editorial Special Section on the 45th IEEE European Solid-State Circuits Conference (ESSCIRC). IEEE J. Solid State Circuits Lucien J. Breems, Patrick Reynaert, Sylvain Clerc
2019	—	`conf`	28nm FDSOI Platform with Embedded PCM for IoT, ULP, Digital, Analog, Automotive and others Applications. ESSCIRC Franck Arnaud, Sébastien Haendler, Sylvain Clerc, Rossella Ranica, Anna Gandolfo, Olivier Weber
2019	—	`conf`	28nm FDSOI Platform with Embedded PCM for IoT, ULP, Digital, Analog, Automotive and others Applications. ESSDERC Franck Arnaud, Sébastien Haendler, Sylvain Clerc, Rossella Ranica, Anna Gandolfo, Olivier Weber
2019	A	`conf`	Comparative evaluation of Body Biasing and Voltage Scaling for Low-Power Design on 28nm UTBB FD-SOI Technology. ISLPED Ricardo Gomez Gomez, Edwige Bano, Sylvain Clerc
2017	—	`conf`	A 0.40pJ/cycle 981 μm A-SSCC Martin Cochet, Sylvain Clerc, Guenole Lallement, Fady Abouzeid, Philippe Roche, Jean-Luc Autran
2016	—	`conf`	30% static power improvement on ARM Cortex ESSCIRC Fady Abouzeid, Christophe Bernicot, Sylvain Clerc, Jean-Marc Daveau, Gilles Gasiot, Daniel Noblet, Dimitri Soussan, Philippe Roche
2016	C	`conf`	A 28nm FD-SOI standard cell 0.6-1.2V open-loop frequency multiplier for low power SoC clocking. ISCAS Martin Cochet, Sylvain Clerc, Mehdi Naceur, Pierre Schamberger, Damien Croain, Jean-Luc Autran, Philippe Roche
2016	—	`conf`	On-chip supply power measurement and waveform reconstruction in a 28nm FD-SOI processor SoC. A-SSCC Martin Cochet, Alberto Puggelli, Ben Keller, Brian Zimmer, Milovan Blagojevic, Sylvain Clerc, Philippe Roche, Jean-Luc Autran, Borivoje Nikolic
2015	—	`conf`	28nm FD-SOI technology and design platform for sub-10pJ/cycle and SER-immune 32bits processors. ESSCIRC Fady Abouzeid, Sylvain Clerc, Cyril Bottoni, Benjamin Coeffic, Jean-Marc Daveau, Damien Croain, Gilles Gasiot, Dimitri Soussan, Philippe Roche
2015	—	`conf`	8.4 A 0.33V/-40°C process/temperature closed-loop compensation SoC embedding all-digital clock multiplier and DC-DC converter exploiting FDSOI 28nm back-gate biasing. ISSCC Sylvain Clerc, Mehdi Saligane, Fady Abouzeid, Martin Cochet, Jean-Marc Daveau, Cyril Bottoni, David Bol, Julien De Vos, Dominique Zamora, Benjamin Coeffic, Dimitri Soussan, Damien Croain, Mehdi Naceur, Pierre Schamberger, Philippe Roche, Dennis Sylvester
2015	J	`jnl`	A 460 MHz at 397 mV, 2.6 GHz at 1.3 V, 32 bits VLIW DSP Embedding F MAX Tracking. IEEE J. Solid State Circuits Edith Beigné, Alexandre Valentian, Ivan Miro Panades, Robin Wilson, Philippe Flatresse, Fady Abouzeid, Thomas Benoist, Christian Bernard, Sebastien Bernard, Olivier Billoint, Sylvain Clerc, Bastien Giraud, Anuj Grover, Julien Le Coz, Jean-Philippe Noel, Olivier Thomas, Yvain Thonnart
2015	—	`conf`	Design and performance parameters of an ultra-low voltage, single supply 32bit processor implemented in 28nm FDSOI technology. ISQED Sylvain Clerc, Fady Abouzeid, Darayus Adil Patel, Jean-Marc Daveau, Cyril Bottoni, Lorenzo Ciampolini, Fabien Giner, David Meyer, Robin Wilson, Philippe Roche, Sylvie Naudet, Arnaud Virazel, Alberto Bosio, Patrick Girard
2015	—	`conf`	Frequency and voltage effects on SER on a 65nm Sparc-V8 microprocessor under radiation test. IRPS Cyril Bottoni, Benjamin Coeffic, Jean-Marc Daveau, Gilles Gasiot, Fady Abouzeid, Sylvain Clerc, Lirida A. B. Naviner, Philippe Roche
2014	—	`conf`	27.1 A 460MHz at 397mV, 2.6GHz at 1.3V, 32b VLIW DSP, embedding FMAX tracking. ISSCC Robin Wilson, Edith Beigné, Philippe Flatresse, Alexandre Valentian, Fady Abouzeid, Thomas Benoist, Christian Bernard, Sebastien Bernard, Olivier Billoint, Sylvain Clerc, Bastien Giraud, Anuj Grover, Julien Le Coz, Ivan Miro Panades, Jean-Philippe Noël, Bertrand Pelloux-Prayer, Philippe Roche, Olivier Thomas, Yvain Thonnart, David Turgis, Fabien Clermidy, Philippe Magarshack
2014	J	`jnl`	Particle Monte Carlo modeling of single-event transient current and charge collection in integrated circuits. Microelectron. Reliab. Jean-Luc Autran, Maximilien Glorieux, Daniela Munteanu, Sylvain Clerc, Gilles Gasiot, Philippe Roche
2014	J	`jnl`	Scalable 0.35 V to 1.2 V SRAM Bitcell Design From 65 nm CMOS to 28 nm FDSOI. IEEE J. Solid State Circuits Fady Abouzeid, Audrey Bienfait, Kaya Can Akyel, Anis Feki, Sylvain Clerc, Lorenzo Ciampolini, Fabien Giner, Robin Wilson, Philippe Roche
2013	—	`conf`	Scalable 0.35V to 1.2V SRAM bitcell design from 65nm CMOS to 28nm FDSOI. ESSCIRC Fady Abouzeid, Audrey Bienfait, Kaya Can Akyel, Sylvain Clerc, Lorenzo Ciampolini, Philippe Roche
2013	A	`conf`	Ultra-wide voltage range designs in fully-depleted silicon-on-insulator FETs. DATE Edith Beigné, Alexandre Valentian, Bastien Giraud, Olivier Thomas, Thomas Benoist, Yvain Thonnart, Serge Bernard, Guillaume Moritz, Olivier Billoint, Y. Maneglia, Philippe Flatresse, Jean-Philippe Noel, Fady Abouzeid, Bertrand Pelloux-Prayer, Anuj Grover, Sylvain Clerc, Philippe Roche, Julien Le Coz, Sylvain Engels, Robin Wilson
2012	—	`conf`	28nm CMOS, energy efficient and variability tolerant, 350mV-to-1.0V, 10MHz/700MHz, 252bits frame error-decoder. ESSCIRC Fady Abouzeid, Sylvain Clerc, Bertrand Pelloux-Prayer, Fabrice Argoud, Philippe Roche
2012	—	`conf`	A 0.32V, 55fJ per bit access energy, CMOS 65nm bit-interleaved SRAM with radiation Soft Error tolerance. ICICDT Sylvain Clerc, Fady Abouzeid, Gilles Gasiot, David Gauthier, Dimitri Soussan, Philippe Roche
2012	—	`conf`	A 65nm SRAM achieving 250mV retention and 350mV, 1MHz, 55fJ/bit access energy, with bit-interleaved radiation Soft Error tolerance. ESSCIRC Sylvain Clerc, Fady Abouzeid, Gilles Gasiot, David Gauthier, Philippe Roche
2011	J	`jnl`	40nm CMOS 0.35V-Optimized Standard Cell Libraries for Ultra-Low Power Applications. ACM Trans. Design Autom. Electr. Syst. Fady Abouzeid, Sylvain Clerc, Fabian Firmin, Marc Renaudin, Tiempo Sas, Gilles Sicard
2011	—	`conf`	A 240mV 1MHz, 340mV 10MHz, 40nm CMOS, 252 bits frame decoder using ultra-low voltage circuit design platform. ICECS Sylvain Clerc, Fady Abouzeid, Fabrice Argoud, Abhay Kumar, Rajesh Kumar, Philippe Roche
2010	—	`conf`	A 40nm CMOS 260kb SRAM-bitcell on-chip failure monitoring test scribe with integer-to-current converter. ESSCIRC Brice Lhomme, Yann Carminati, Bertrand Borot, Olivier Callen, Thierry Burdeau, Sylvain Clerc
2009	A	`conf`	A 45nm CMOS 0.35v-optimized standard cell library for ultra-low power applications. ISLPED Fady Abouzeid, Sylvain Clerc, Fabian Firmin, Marc Renaudin, Gilles Sicard
2008	—	`conf`	A 45nm single power supply SRAM supporting low voltage operation down to 0.6V. ESSCIRC Sebastien Barasinski, Ludovic Camus, Sylvain Clerc