Sying-Jyan Wang

92 papers A* 2A 13B 3C 12Misc 2Journal 23Unranked 37

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Security-oriented printed-circuit-board routing with deep reinforcement learning. Integr. Katherine Shu-Min Li, Fang-Chi Wu, Ching-Han Lai, Sying-Jyan Wang
2025	C	`conf`	Design of Reliable and Modeling-Attack Resistant Strong PUFs for Lightweight Applications. ISCAS Sying-Jyan Wang, Gong-Chi Wang, Chi-Yun Chen, Katherine Shu-Min Li
2025	C	`conf`	Masking Based Protection Mechanism for Ascon against CPA Attack. ISCAS Sying-Jyan Wang, Ho Lam Cheung, Katherine Shu-Min Li
2024	J	`jnl`	Enhanced Watermarking for Paper-Based Digital Microfluidic Biochips. ACM Trans. Design Autom. Electr. Syst. Jian-De Li, Sying-Jyan Wang, Katherine Shu-Min Li, Tsung-Yi Ho
2024	J	`jnl`	Reinforcement Learning Double DQN for Chip-Level Synthesis of Paper-Based Digital Microfluidic Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Katherine Shu-Min Li, Fang-Chi Wu, Jian-De Li, Sying-Jyan Wang
2023	J	`jnl`	Design-for-reliability and on-the-fly fault tolerance procedure for paper-based digital microfluidic biochips with multiple faults. Integr. Jian-De Li, Sying-Jyan Wang, Katherine Shu-Min Li, Tsung-Yi Ho
2023	—	`conf`	Implementing OIML R46 Communication Unit for DLMS/COSEM Security Suite 1 and Passing CTT V3.1 Test. ICNSC Chun-Tsai Chien, Chien-Lung Wang, I-En Liao, Sying-Jyan Wang
2023	A	`conf`	Machine-Learning Driven Sensor Data Analytics for Yield Enhancement of Wafer Probing. ITC Nadun Sinhabahu, Katherine Shu-Min Li, Sying-Jyan Wang, J. R. Wang, Matt Ho
2022	—	`conf`	Design-for-Reliability and Probability-Based Fault Tolerance for Paper-Based Digital Microfluidic Biochips with Multiple Faults. ASP-DAC Jian-De Li, Sying-Jyan Wang, Katherine Shu-Min Li, Tsung-Yi Ho
2022	—	`conf`	Improving IJTAG Test Efficiency and Security. VLSI-DAT Sying-Jyan Wang, Yen-Chang Shih, Katherine Shu-Min Li, Chen-Yeh Lin, Song-Kong Chong
2022	—	`conf`	Intrusion Detection and Obfuscation Mechanism for PUF-Based Authentication. ATS Sying-Jyan Wang, Katherine Shu-Min Li, Chen-Yeh Lin, Song-Kong Chong
2022	B	`conf`	Trojan Insertions of Fully Programmable Valve Arrays. ETS Nadun Sinhabahu, Jian-De Li, Katherine Shu-Min Li, Sying-Jyan Wang, Tsung-Yi Ho
2022	A	`conf`	Wafer Defect Pattern Classification with Explainable-Decision Tree Technique. ITC Ken Chau-Cheung Cheng, Katherine Shu-Min Li, Sying-Jyan Wang, Andrew Yi-Ann Huang, Chen-Shiun Lee, Leon Li-Yang Chen, Peter Yi-Yu Liao, Nova Cheng-Yen Tsai
2022	A	`conf`	Yield-Enhanced Probe Head Cleaning with AI-Driven Image and Signal Integrity Pattern Recognition for Wafer Test. ITC Nadun Sinhabahu, Katherine Shu-Min Li, Jian-De Li, J. R. Wang, Sying-Jyan Wang
2021	B	`conf`	Automatic Inspection for Wafer Defect Pattern Recognition with Unsupervised Clustering. ETS Katherine Shu-Min Li, Leon Li-Yang Chen, Ken Chau-Cheung Cheng, Peter Yi-Yu Liao, Sying-Jyan Wang, Andrew Yi-Ann Huang, Nova Cheng-Yen Tsai, Leon Chou, Gus Chang-Hung Han, Jwu E. Chen, Hsing-Chung Liang, Chun-Lung Hsu
2021	A	`conf`	Double DQN for Chip-Level Synthesis of Paper-Based Digital Microfluidic Biochips. DATE Fang-Chi Wu, Jian-De Li, Katherine Shu-Min Li, Sying-Jyan Wang, Tsung-Yi Ho
2021	—	`conf`	Integrated Scratch Marker for Wafer Defect Diagnosis. ITC-Asia Katherine Shu-Min Li, Leon Li-Yang Chen, Peter Yi-Yu Liao, Sying-Jyan Wang, Andrew Yi-Ann Huang, Ken Chau-Cheung Cheng
2021	—	`conf`	Machine Learning Assisted Challenge Selection for Modeling Attack Resistance in Strong PUFs. VLSI-DAT Sying-Jyan Wang, Tzu-Heng Chang, Katherine Shu-Min Li
2021	J	`jnl`	Modeling Attack Resistant PUFs Based on Adversarial Attack Against Machine Learning. IEEE J. Emerg. Sel. Topics Circuits Syst. Sying-Jyan Wang, Yu-Sheng Chen, Katherine Shu-Min Li
2021	A	`conf`	Semi-Supervised Framework for Wafer Defect Pattern Recognition with Enhanced Labeling. ITC Leon Li-Yang Chen, Katherine Shu-Min Li, Xu-Hao Jiang, Sying-Jyan Wang, Andrew Yi-Ann Huang, Jwu E. Chen, Hsing-Chung Liang, Chun-Lung Hsu
2021	A	`conf`	WGrid: Wafermap Grid Pattern Recognition with Machine Learning Techniques. ITC Peter Yi-Yu Liao, Katherine Shu-Min Li, Leon Li-Yang Chen, Sying-Jyan Wang, Andrew Yi-Ann Huang, Ken Chau-Cheung Cheng, Nova Cheng-Yen Tsai, Leon Chou
2020	A	`conf`	Feature Selection for Malicious Traffic Detection with Machine Learning. ICS Sying-Jyan Wang, Cheng Xuan Cai, Yen-Wen Tseng, Katherine Shu-Min Li
2020	Misc	`conf`	Innovative Practice on Wafer Test Innovations. VTS Dyi-Chung Hu, Hirohito Hashimoto, Li-Fong Tseng, Ken Chau-Cheung Cheng, Katherine Shu-Min Li, Sying-Jyan Wang, Sean Y.-S. Chen, Jwu E. Chen, Clark Liu, Andrew Yi-Ann Huang
2020	B	`conf`	PWS: Potential Wafermap Scratch Defect Pattern Recognition with Machine Learning Techniques. ETS Katherine Shu-Min Li, Peter Yi-Yu Liao, Leon Chou, Ken Chau-Cheung Cheng, Andrew Yi-Ann Huang, Sying-Jyan Wang, Gus Chang-Hung Han
2020	A	`conf`	TestDNA-E: Wafer Defect Signature for Pattern Recognition by Ensemble Learning. ITC Leon Li-Yang Chen, Katherine Shu-Min Li, Ken Chau-Cheung Cheng, Sying-Jyan Wang, Andrew Yi-Ann Huang, Leon Chou, Nova Cheng-Yen Tsai, Chen-Shiun Lee
2020	A	`conf`	Wafer-Level Test Path Pattern Recognition and Test Characteristics for Test-Induced Defect Diagnosis. DATE Ken Chau-Cheung Cheng, Katherine Shu-Min Li, Andrew Yi-Ann Huang, Ji-Wei Li, Leon Li-Yang Chen, Nova Cheng-Yen Tsai, Sying-Jyan Wang, Chen-Shiun Lee, Leon Chou, Peter Yi-Yu Liao, Hsing-Chung Liang, Jwu E. Chen
2020	—	`conf`	Watermarking for Paper-Based Digital Microfluidic Biochips. ITC-Asia Jian-De Li, Sying-Jyan Wang, Katherine Shu-Min Li, Tsung-Yi Ho
2019	A*	`conf`	Adversarial Attack against Modeling Attack on PUFs. DAC Sying-Jyan Wang, Yu-Shen Chen, Katherine Shu-Min Li
2019	J	`jnl`	Co-placement optimization in sensor-reusable cyber-physical digital microfluidic biochips. Microelectron. J. Jian-De Li, Chun-Hao Kuo, Guan-Ruei Lu, Sying-Jyan Wang, Katherine Shu-Min Li, Tsung-Yi Ho, Hung-Ming Chen, Shiyan Hu
2019	J	`jnl`	Exploiting distribution of unknown values in test responses to optimize test output compactors. Integr. Sying-Jyan Wang, Kuan-Ting Yeh, Katherine Shu-Min Li
2019	A	`conf`	TestDNA: Novel Wafer Defect Signature for Diagnosis and Yield Learning. ITC Andrew Yi-Ann Huang, Katherine Shu-Min Li, Cheng-Yen Tsai, Ken Chau-Cheung Cheng, Sying-Jyan Wang, Xu-Hao Jiang, Leon Chou, Chen-Shiun Lee
2018	—	`conf`	Digital Rights Management for Paper-Based Microfluidic Biochips. ATS Jian-De Li, Sying-Jyan Wang, Katherine Shu-Min Li, Tsung-Yi Ho
2018	C	`conf`	Register PUF with No Power-Up Restrictions. ISCAS Sying-Jyan Wang, Chin-Hung Lien, Katherine Shu-Min Li
2018	—	`conf`	SOLAR: Simultaneous optimization of control-layer pins placement and channel routing in flow-based microfluidic biochips. VLSI-DAT Jia-Lin Wu, Katherine Shu-Min Li, Jain-De Li, Sying-Jyan Wang, Tsung-Yi Ho
2017	J	`jnl`	Design Methodology of Fault-Tolerant Custom 3D Network-on-Chip. ACM Trans. Design Autom. Electr. Syst. Katherine Shu-Min Li, Sying-Jyan Wang
2017	—	`conf`	Design-for-testability for paper-based digital microfluidic biochips. DFT Jain-De Li, Sying-Jyan Wang, Katherine Shu-Min Li, Tsung-Yi Ho
2017	J	`jnl`	Layout-Aware Optimized Prebond Silicon Interposer Test Synthesis. IEEE Des. Test Katherine Shu-Min Li, Sying-Jyan Wang, Ruei-Ting Gu, Bo-Chuan Cheng
2017	—	`conf`	Testing Clock Distribution Networks. ATS Sying-Jyan Wang, Hsiang-Hsueh Chen, Chin-Hung Lien, Katherine Shu-Min Li
2016	—	`conf`	Congestion- and timing-driven droplet routing for pin-constrained paper-based microfluidic biochips. ASP-DAC Jain-De Li, Sying-Jyan Wang, Katherine Shu-Min Li, Tsung-Yi Ho
2016	—	`conf`	Side-Channel Attack on Flipped Scan Chains. ATS Sying-Jyan Wang, Ting-Jui Choi, Katherine Shu-Min Li
2016	Misc	`conf`	Test and diagnosis of paper-based microfluidic biochips. VTS Jain-De Li, Sying-Jyan Wang, Katherine Shu-Min Li, Tsung-Yi Ho
2016	—	`conf`	Test generation for combinational hardware Trojans. AsianHOST Sying-Jyan Wang, Jhih-Yu Wei, Shih-Heng Huang, Katherine Shu-Min Li
2014	C	`conf`	Fast and accurate statistical static timing analysis. ISCAS Sying-Jyan Wang, Tsung-Huei Tzeng, Katherine Shu-Min Li
2014	—	`conf`	Improving Output Compaction Efficiency with High Observability Scan Chains. ATS Sying-Jyan Wang, Che-Wei Kao, Katherine Shu-Min Li
2014	—	`conf`	Optimized Pre-bond Test Methodology for Silicon Interposer Testing. ATS Katherine Shu-Min Li, Sying-Jyan Wang, Jia-Lin Wu, Cheng-You Ho, Yingchieh Ho, Ruei-Ting Gu, Bo-Chuan Cheng
2013	—	`conf`	A 0.3 V low-power temperature-insensitive ring oscillator in 90 nm CMOS process. VLSI-DAT Yingchieh Ho, Katherine Shu-Min Li, Sying-Jyan Wang
2013	—	`conf`	A Layout-Aware Test Methodology for Silicon Interposer in System-in-a-Package. Asian Test Symposium Katherine Shu-Min Li, Cheng-You Ho, Ruei-Ting Gu, Sying-Jyan Wang, Yingchieh Ho, Jiun-Jie Huang, Bo-Chuan Cheng, An-Ting Liu
2013	J	`jnl`	Delay Test with Embedded Test Pattern Generator. J. Inf. Sci. Eng. Nan-Cheng Lai, Sying-Jyan Wang
2013	—	`conf`	Leakage Monitoring Technique in Near-Threshold Systems with a Time-Based Bootstrapped Ring Oscillator. Asian Test Symposium Yingchieh Ho, Katherine Shu-Min Li, Sying-Jyan Wang
2013	—	`conf`	Low-cost testing of TSVs in 3D stacks with pre-bond testable dies. VLSI-DAT Sying-Jyan Wang, Yu-Siao Chen, Katherine Shu-Min Li
2013	C	`conf`	Synthesis of 3D clock tree with pre-bond testability. ISCAS Sying-Jyan Wang, Cheng-Hao Lin, Katherine Shu-Min Li
2012	—	`conf`	De Bruijn graph-based communication modeling for fault tolerance in smart grids. APCCAS Bo-Chuan Cheng, Katherine Shu-Min Li, Sying-Jyan Wang
2012	C	`conf`	Low-power delay test architecture for pre-bond test. ISCAS Sying-Jyan Wang, Han-Hsuan Hsu, Katherine Shu-Min Li
2012	J	`jnl`	Power-Aware High-Level Synthesis With Clock Skew Management. IEEE Trans. Very Large Scale Integr. Syst. Tung-Hua Yeh, Sying-Jyan Wang
2010	—	`conf`	Thermal Safe High Level Test Synthesis for Hierarchical Testability. Asian Test Symposium Tung-Hua Yeh, Sying-Jyan Wang
2009	J	`jnl`	High-Level Test Synthesis With Hierarchical Test Generation for Delay-Fault Testability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Sying-Jyan Wang, Tung-Hua Yeh
2009	C	`conf`	Level Converting Scan Flip-flops. ISCAS Katherine Shu-Min Li, Ming-Hua Hsieh, Sying-Jyan Wang
2009	C	`conf`	Low Peak Power ATPG for n-Detection Test. ISCAS Sying-Jyan Wang, Kuo-Lin Fu, Katherine Shu-Min Li
2009	J	`jnl`	Scan-Chain Partition for High Test-Data Compressibility and Low Shift Power Under Routing Constraint. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Sying-Jyan Wang, Katherine Shu-Min Li, Shih-Cheng Chen, Huai-Yan Shiu, Yun-Lung Chu
2008	C	`conf`	Design and analysis of skewed-distribution scan chain partition for improved test data compression. ISCAS Sying-Jyan Wang, Shih-Cheng Chen, Katherine Shu-Min Li
2008	J	`jnl`	Layout-aware scan chain reorder for launch-off-shift transition test coverage. ACM Trans. Design Autom. Electr. Syst. Sying-Jyan Wang, Kuo-Lin Peng, Kuang-Cyun Hsiao, Katherine Shu-Min Li
2008	J	`jnl`	Multi-mode-segmented scan architecture with layout-aware scan chain routing for test data and test time reduction. IET Comput. Digit. Tech. Po-Chang Tsai, Sying-Jyan Wang
2008	—	`conf`	On-Chip Test Generation Mechanism for Scan-Based Two-Pattern Tests. ATS Nan-Cheng Lai, Sying-Jyan Wang
2007	A	`conf`	High-level test synthesis for delay fault testability. DATE Sying-Jyan Wang, Tung-Hua Yeh
2007	—	`conf`	Layout-Aware Multi-Layer Multi-Level Scan Tree Synthesis. ATS Sying-Jyan Wang, Xin-Long Li, Katherine Shu-Min Li
2007	C	`conf`	Low Capture Power Test Generation for Launch-off-Capture Transition Test Based on Don't-Care Filling. ISCAS Sying-Jyan Wang, Yan-Ting Chen, Katherine Shu-Min Li
2007	—	`conf`	Low-Capture-Power Test Generation by Specifying A Minimum Set of Controlling Inputs. ATS Nan-Cheng Lai, Sying-Jyan Wang
2007	J	`jnl`	Test Data Compression for Minimum Test Application Time. J. Inf. Sci. Eng. Po-Chang Tsai, Sying-Jyan Wang, Ching-Hung Lin, Tung-Hua Yeh
2007	—	`conf`	Test Data and Test Time Reduction for LOS Transition Test in Multi-Mode Segmented Scan Architecture. ATS Sying-Jyan Wang, Po-Chang Tsai, Hung-Ming Weng, Katherine Shu-Min Li
2006	—	`conf`	Layout-Aware Scan Chain Reorder for Skewed-Load Transition Test Coverage. ATS Sying-Jyan Wang, Kuo-Lin Peng, Katherine Shu-Min Li
2006	J	`jnl`	Low-Power BIST With a Smoother and Scan-Chain Reorder Under Optimal Cluster Size. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Nan-Cheng Lai, Sying-Jyan Wang, Y.-H. Fu
2006	—	`conf`	Multi-Mode Segmented Scan Architecture with Layout-Aware Scan Chain Routing for Test Data and Test Time Reduction. ATS Po-Chang Tsai, Sying-Jyan Wang
2005	—	`conf`	FSM-based programmable memory BIST with macro command. MTDT Po-Chang Tsai, Sying-Jyan Wang, Feng-Ming Chang
2005	—	`conf`	Low power parallel multiplier with column bypassing. ISCAS (2) Mingchen Wen, Sying-Jyan Wang, Yen-Nan Lin
2005	—	`conf`	Test Data Compression with Partial LFSR-Reseeding. Asian Test Symposium Yu-Hsuan Fu, Sying-Jyan Wang
2004	—	`conf`	Low Power BIST with Smoother and Scan-Chain Reorder . Asian Test Symposium Nan-Cheng Lai, Sying-Jyan Wang, Yu-Hsuan Fu
2002	—	`conf`	A Reseeding Technique for LFSR-Based BIST Applications. Asian Test Symposium Nan-Cheng Li, Sying-Jyan Wang
2002	A	`conf`	Retiming-based logic synthesis for low-power. ISLPED Yu-Lung Hsu, Sying-Jyan Wang
2001	J	`jnl`	Distributed Diagnosis in Multistage Interconnection Networks. J. Parallel Distributed Comput. Sying-Jyan Wang
2001	A*	`conf`	Generating Efficient Tests for Continuous Scan. DAC Sying-Jyan Wang, Sheng-Nan Chiou
2000	—	`conf`	Efficient built-in self-test algorithm for memory. Asian Test Symposium Sying-Jyan Wang, Chen-Jung Wei
2000	J	`jnl`	Testability Improvement by Branch Point Control for Conditional Staements With Multiple Branches. J. Inf. Sci. Eng. Sying-Jyan Wang, Chia-Chun Lien
1998	—	`conf`	Testing and Diagnosis of Interconnect Structures in FPGAs. Asian Test Symposium Sying-Jyan Wang, Chao-Neng Huang
1997	J	`jnl`	Distributed Routing in a Fault-Tolerant Multistage Interconnection Network. Inf. Process. Lett. Sying-Jyan Wang
1997	A	`conf`	Test and diagnosis of fault logic blocks in FPGAs. ICCAD Sying-Jyan Wang, Tsi-Ming Tsai
1996	J	`jnl`	Load-Balancing in Multistage Interconnection Networks under Multiple-Pass Routing. J. Parallel Distributed Comput. Sying-Jyan Wang
1996	—	`conf`	Testing And Diagnosis Of Board Interconnects In Microprocessor-Based Systems. Asian Test Symposium Po-Ching Hsu, Sying-Jyan Wang
1994	J	`jnl`	Algorithm-Based Fault Tolerance for FFT Networks. IEEE Trans. Computers Sying-Jyan Wang, Niraj K. Jha
1994	—	`conf`	Synthesis of Sequential Machines with Reduced Testing Cost. EDAC-ETC-EUROASIC Sying-Jyan Wang
1993	J	`jnl`	Design and synthesis of self-checking VLSI circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Niraj K. Jha, Sying-Jyan Wang
1992	C	`conf`	Multiple Input Bridging Fault Detection in CMOS Sequential Circuits. ICCD Niraj K. Jha, Sying-Jyan Wang, Phillip C. Gripka
1991	C	`conf`	Design and Synthesis of Self-Checking VLSI Circuits and Systems. ICCD Niraj K. Jha, Sying-Jyan Wang