Syed Zahid Ahmed

18 papers A 3B 2C 1Misc 1Journal 3Unranked 8
YearRankTypeTitle / Venue / Authors
2019 J jnl
High-throughput parallel DWT hardware architecture implemented on an FPGA-based platform.
J. Real Time Image Process.
Mohammed Shaaban Ibraheem, Khalil Hachicha, Syed Zahid Ahmed, Laurent Lambert, Patrick Garda
2016 A conf
A Low DDR Bandwidth 100FPS 1080p Video 2D Discrete Wavelet Transform Implementation on FPGA (Abstract Only).
FPGA
Mohammed Shaaban Ibraheem, Syed Zahid Ahmed, Khalil Hachicha, Sylvain Hochberg, Patrick Garda
2016 — conf
High frame rate medical quality video compression for tele-EEG.
EMBC
Laurent Lambert, Syed Zahid Ahmed, Khalil Hachicha, Andréa Pinna, Patrick Garda
2016 J jnl
Logarithmic Discrete Wavelet Transform for Medical Image Compression with Diagnostic Quality.
EAI Endorsed Trans. Pervasive Health Technol.
Mohammed Shaaban Ibraheem, Khalil Hachicha, Syed Zahid Ahmed, Sylvain Hochberg, Patrick Garda
2016 — conf
Medical images compression with clinical diagnostic quality using logarithmic DWT.
BHI
Mohammed Shaaban Ibraheem, Syed Zahid Ahmed, Khalil Hachicha, Sylvain Hochberg, Patrick Garda
2015 J jnl
ARC 2014: Towards a Fast FPGA Implementation of a Heap-Based Priority Queue for Image Coding Using a Parallel Index-Aware Tree.
ACM Trans. Reconfigurable Technol. Syst.
Yuhui Bai, Syed Zahid Ahmed, Bertrand Granado
2015 — conf
Synchronizing physiological data and video in a telemedicine application: A multimedia approach.
EMBC
Laurent Lambert, Khalil Hachicha, Syed Zahid Ahmed, Andréa Pinna, Patrick Garda
2014 A conf
A power-efficient adaptive heapsort for fpga-based image coding application (abstract only).
FPGA
Yuhui Bai, Syed Zahid Ahmed, Bertrand Granado
2014 — conf
Accelerating Heap-Based Priority Queue in Image Coding Application Using Parallel Index-Aware Tree Access.
ARC
Yuhui Bai, Syed Zahid Ahmed, Bertrand Granado
2014 Misc conf
Fast and Power Efficient Heapsort IP for Image Compression Application.
FCCM
Yuhui Bai, Syed Zahid Ahmed, Bertrand Granado
2013 — conf
Design and analysis of an FPGA based encoder SoC for locally stationary image source.
DASIP
Yuhui Bai, Syed Zahid Ahmed, Bertrand Granado
2013 B conf
FPGA implementation of Hierarchical Enumerative Coding for locally stationary image source.
FPL
Yuhui Bai, Syed Zahid Ahmed, Bertrand Granado
2013 C conf
FPGA vs DSP: A throughput and power efficiency comparison for Hierarchical Enumerative Coding.
VLSI-SoC
Yuhui Bai, Syed Zahid Ahmed, Imen Mhedhbi, Khalil Hachicha, Cedric Champion, Patrick Garda, Bertrand Granado
2010 — conf
A Dynamic Reconfigurable MRAM based FPGA.
ERSA
Lionel Torres, Yoann Guillemenet, Syed Zahid Ahmed
2010 B conf
Survey of New Trends in Industry for Programmable Hardware: FPGAs, MPPAs, MPSoCs, Structured ASICs, eFPGAs and New Wave of Innovation in FPGAs.
FPL
Syed Zahid Ahmed, Gilles Sassatelli, Lionel Torres, Laurent Rouge
2009 A conf
Exploration of power reduction and performance enhancement in LEON3 processor with ESL reprogrammable eFPGA in processor pipeline and as a co-processor.
DATE
Syed Zahid Ahmed, Julien Eydoux, Laurent Rouge, Jean-Baptiste Cuelle, Gilles Sassatelli, Lionel Torres
2009 — conf
MRAM Based eFPGAs: Programming and Silicon Flows, Exploration Environments, MRAM Current State in Industry and Its Unique Potentials for FPGAs.
ReConFig
Yoann Guillemenet, Syed Zahid Ahmed, Lionel Torres, Alexandre Martheley, Julien Eydoux, Jean-Baptiste Cuelle, Laurent Rouge, Gilles Sassatelli
2008 — conf
Power Consumption Reduction Explorations in Processors by Enhancing Performance Using Small ESL Reprogrammable eFPGAs.
ReConFig
Syed Zahid Ahmed, Julien Eydoux, Michael Fernández, Laurent Rouge, Gilles Sassatelli, Lionel Torres