Syed Suhaib

18 papers C 1Misc 1Journal 7Unranked 8
YearRankTypeTitle / Venue / Authors
2025 J jnl
AssertionForge: Enhancing Formal Verification Assertion Generation with Structured Representation of Specifications and RTL.
CoRR
Yunsheng Bai, Ghaith Bany Hamad, Syed Suhaib, Haoxing Ren
2025 J jnl
FVDebug: An LLM-Driven Debugging Assistant for Automated Root Cause Analysis of Formal Verification Failures.
CoRR
Yunsheng Bai, Ghaith Bany Hamad, Chia-Tung Ho, Syed Suhaib, Haoxing Ren
2024 Misc conf
Domain-Adapted LLMs for VLSI Design and Verification: A Case Study on Formal Verification.
VTS
Mingjie Liu, Minwoo Kang, Ghaith Bany Hamad, Syed Suhaib, Haoxing Ren
2024 J jnl
FVEval: Understanding Language Model Capabilities in Formal Verification of Digital Hardware.
CoRR
Minwoo Kang, Mingjie Liu, Ghaith Bany Hamad, Syed Suhaib, Haoxing Ren
2008 J jnl
A Trace-Based Framework for Verifiable GALS Composition of IPs.
IEEE Trans. Very Large Scale Integr. Syst.
Syed Suhaib, Deepak Mathaikutty, Sandeep K. Shukla
2008 C conf
Formal Transformation of a KPN Specification to a GALS Implementation.
FDL
Syed Suhaib, Bijoy Antony Jose, Sandeep K. Shukla, Deepak Mathaikutty
2007 — conf
Dataflow Architectures for GALS.
FMGALS@MEMOCODE
Syed Suhaib, Deepak Mathaikutty, Sandeep K. Shukla
2007 — —
Formal Methods for Intellectual Property Composition Across Synchronization Domains.
Syed Suhaib
2006 — conf
A Trace Based Framework for Validation of SoC Designs with GALS Systems.
SoCC
Syed Suhaib, Deepak Mathaikutty, Sandeep K. Shukla
2006 — conf
Polychronous Methodology For System Design: A True Concurrency Approach.
HLDVT
Syed Suhaib, Deepak Mathaikutty, Sandeep K. Shukla, Jean-Pierre Talpin
2006 J jnl
Validating Families of Latency Insensitive Protocols.
IEEE Trans. Computers
Syed Suhaib, Deepak Mathaikutty, David Berner, Sandeep K. Shukla
2005 — conf
A Functional Programming Framework for Latency Insensitive Protocol Validation.
FMGALS@MEMOCODE
Syed Suhaib, Deepak Mathaikutty, Sandeep K. Shukla, David Berner, Jean-Pierre Talpin
2005 — conf
System Level Design Methodology for System On Chips using Multi-Threaded Graphs.
SoCC
Syed Suhaib, Deepak Mathaikutty, Sandeep K. Shukla
2005 — conf
Validating families of latency insensitive protocols.
HLDVT
Syed Suhaib, Deepak Mathaikutty, Sandeep K. Shukla, David Berner
2005 J jnl
XFM: An incremental methodology for developing formal models.
ACM Trans. Design Autom. Electr. Syst.
Syed Suhaib, Deepak Mathaikutty, Sandeep K. Shukla, David Berner
2004 J jnl
A Formally Verified Application-Level Framework for Real-Time Scheduling on POSIX Real-Time Operating Systems.
IEEE Trans. Software Eng.
Peng Li, Binoy Ravindran, Syed Suhaib, Shahrooz Feizabadi
2004 — conf
Effects of property ordering in an incremental formal modeling methodology.
HLDVT
Syed Suhaib, Deepak Mathaikutty, Sandeep K. Shukla
2004 — conf
Extreme Formal Modeling (XFM) for Hardware Models.
MTV
Syed Suhaib, Deepak Mathaikutty, Sandeep K. Shukla, David Berner